WS05-4RUL SOT-23-6L. Features IEC COMPATIBILITY (EN ) Transient Voltage Suppressor. SOT-23-6L (Top View) Document: W , Rev: D

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1 Document: W34, Rev: D Transient Voltage Suppressor Features Solid-state silicon-avalanche technology 4Watts Peak Pulse Power per Line (t p =8/μs) Low operating and clamping voltage Up to four I/O Lines of Protection Ultra low capacitance:.pf Low Leakage Low operating voltage:v SOT-3-L IE OMPATIBILITY (EN-4) IE -4- (ESD) ±kv (air), ±8kV (contact) IE -4-4 (EFT) 4A (/ns) IE -4- (Lightning) A (8/μs) Mechanical haracteristics Applications SOT-3-L package Molding compound flammability rating: UL 94V- Marking: Marking ode Packaging: Tape and Reel RoHS/WEEE ompliant Video/Graphics ard Handheld & Portable Electronics P/Notebook USB./IEEE394 ports // Ethernet DVI interfaces Wireless data (WAN/LAN) systems ircuit Diagram Schematic & PIN onfiguration SOT-3-L (Top View) 8 WAYON orporation / 7

2 Absolute Maximum Rating Rating Symbol Value Units Peak Pulse Power ( t p =8/μs ) P PP 4 Watts Peak Pulse urrent ( t p =8/μs ) I pp A Operating Temperature T J - to + Storage Temperature T STG - to + Electrical Parameters (T= ) Symbol Parameter I IPP Maximum Reverse Peak Pulse urrent I F V VRWM IR VBR IT IF VF lamping IPP Working Peak Reverse Voltage Maximum Reverse Leakage VRWM Breakdown IT Test urrent Forward urrent Forward IF V V BR V RWM V F V I R IT I PP Electrical haracteristics Parameter Symbol onditions Minimum Typical Maximum Units Reverse Stand-Off Voltage V RWM Pin to pin. V Reverse Breakdown Voltage V BR I T=mA Pin to pin. V Reverse Leakage urrent I R V RWM=V, T= Pin to pin µa Forward Voltage VF IT=mA. lamping Voltage V I PP=A, t p=8/μs I/O pin to GND. 9 V Junction apacitance j VR = V, f = MHz I/O pin to GND VR = V, f = MHz Between I/O pins 3 pf. pf 8 WAYON orporation / 7

3 Typical haracteristics Figure : Peak Pulse Power vs. Pulse Time Figure : Power Derating urve Ppp Peak Pulse Power - Ppp(KW). 4W 8/µs waveform.., t d Pulse Duration - µs Percent of Rated Power for Ipp Ambient Temperature - T A ( ) Percent Ipp Figure 3: Pulse Waveform e -t 3 Time (µs) td=ipp/ Waveform Paramters tr=8µs td=µs lamping Voltage -V(V) Figure 4: lamping Voltage vs. Peak Pulse urrent Peak Pulse urrent -I pp (A) Figure : apacitance vs. Reverse Voltage Figure : Forward Voltage vs. Forward urrent apacitance j (pf)... f= MHz I/O Pin to Gnd Between I/O Lines Reverse Voltage V R (V) Forward Voltage VF(V) Forward urrent I F (A) Test Waveform Paramters tr=8µs td=µs 8 WAYON orporation 3 / 7

4 Application Information Device onnection Options for Protection of Four High-Speed Data Lines The TVS is designed to protect four data lines from transient over-voltages by clamping them to a fixed reference. When the voltage on the protected line exceeds the reference voltage (plus diode VF) the steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. Data lines are connected at pins, 3, 4 and. The negative reference (R EF ) is connected at pin. This pin should be connected directly to a ground plane on the board for best results. The path length is kept as short as possible to minimize parasitic inductance. The positive reference (R EF ) is connected at pin. The options for connecting the positive reference are as follows: Data Line and Power Supply Protection Using V as reference. To protect data lines and the power line, connect pin directly to the positive supply rail (V cc ). In this configuration the data lines are referenced to the supply voltage. The internal TVS diode prevents over- voltage to the supply rail. I/O I/O V To Protected I Data Line Protection with Bias and Power Supply Isolation Resistor. The can be isolated from the power supply by adding a series resistor between pin and V, A value of kω is recommended. The internal TVS and steering diodes remains biased, providing the advantage of lower capacitance. I/O I/O V k To Protected I 3. In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may be used as the reference. In this case, pin is not connected. The steering diodes will begin to conduct when the voltage on the protected line exceeds the working voltage of the TVS (plus one diode drop). Data Line Protection Using Internal TVS Diode as Reference I/O I/O N To Protected I 8 WAYON orporation 4 / 7

5 Typical Applications Video Interface Protection Video interfaces are susceptible to transient voltages resulting from electrostatic discharge (ESD) and hot plugging cables. If left unprotected, the video interface I may be damaged or even destroyed. Protecting a high-speed video port presents some unique challenges. First, any added protection device must have extremely low capacitance and low leakage current so that the integrity of the video signal is not compromised. Second, the protection component must be able to absorb high voltage transients without damage or degradation. As a minimum, the device should be rated to handle ESD voltages per IE -4-, level 4 (±kv air, ±8kV contact). The clamping voltage of the device (when conducting high current ESD pulses) must be sufficiently low enough to protect the sensitive MOS I. If the clamping voltage is too high, the protected device may latch-up or be destroyed. Finally, the device must take up a relatively small amount of board space, particularly in portable applications such as notebooks and handhelds. The is designed to meet or exceed all of the above criteria. A typical video interface protection circuit is shown in Figure. All exposed lines are protected including R, G, B, H-Sync, V-Sync, and the ID lines for plug and play monitors. VBUS Vcc Vcc USB ontroller VBUS VBUS V BUS D+ D- GND V BUS D+ D- GND USB PO USB PO Figure Video Interface Protection Figure Dual USB Port Protection Universal Serial Bus ESD Protection The may also be used to protect the USB ports on monitors, computers, peripherals or portable systems. Each device will protect up to two USB ports (Figure ). When the voltage on the data lines exceed the bus voltage (plus one diode drop), the internal rectifiers are forward biased conducting the transient current away from the protected controller chip. The TVS diode directs the surge to ground. The TVS diode also acts to suppress ESD strikes directly on the voltage bus. Thus, both power and data pins are protected with a single device. 8 WAYON orporation / 7

6 / Ethernet Protection Ethernet Is are vulnerable to damage from electrostatic discharge (ESD). The internal protection in the PHY chip, if any, often is not enough due to the high energy of the discharges specified by IE -4-. If the discharge is catastrophic, it will destroy the protected I. If it is less severe, it will cause latent failures that are very difficult to find. / Ethernet operates at MHz clock over a twisted pair interface. In a typical system, the twisted pair interface for each port consists of two differential signal pairs: one for the transmitter and one for the receiver, with the transmitter input being the most sensitive to damage. The fatal discharge occurs differentially across the transmit or receive line pair and is capacitively coupled through the transformer to the Ethernet chip. Figure 3 shows how to design the on the line side of a / Ethernet port to provide differential mode protection. The common mode isolation of the transformer will provide common mode protection to the rating of the transformer isolation which is usually >.kv. If more common mode protection is needed, figure 4 shows how to design the on the I side of the / Ethernet circuit to provide differential and common mode protection. The can not be grounded on the line side because the hi-pot test requires the line side not to be grounded. RJ4 TX+ TX+ TX- RX / + ETHERNE T PHY TX- RX+ RX- To Twisted-Pair Network RX- V V 7Ω 7Ω 7Ω 7Ω GN D / Ethernet Differential Protection RJ4 ETHERNE T TRANEIV ER TX+ TX- RX+ RX- To Twisted-Pair Network 7Ω 7Ω 7Ω 7Ω / Ethernet Differential and ommon Mode Protection 8 WAYON orporation / 7

7 E E θ Silicontrol TM Overvoltage Protection Products Outline Drawing SOT-3-L PAKAGE OUTLINE b SOT-3-L DIMENSIONS e e D A A SEE DETAIL A DETAIL A. SYMBOL INHES MILLIMETER MIN MAX MIN MAX A A..4.. A D E E A L e.37(bs).9(bs) e L θ o 8 o o 8 o X DIMENSIONS DIM INHES MILLIMETERS Notes THIS LAND PATTERN IS FOR REFERENE PURPOSES ONLY. ONSULT YOUR MANUFAURING GROUP TO ENSURE YOUR OMPANY'S MANUFAURING GUIDELINES ARE MET. Z.4 3. G Z G..4 P.37.9 Y X.4. Y.43. P (.98) (.) Marking odes 4 Part Number Marking ode U U 3 ONTA INFORMATION SHANGHAI HANGYUAN WAYON IRUIT PROTEION O., LTD. No., Shiwan(7) Road, Pudong District, Shanghai, P.R.hina. Tel: Fax: market@way-on.com WAYON website: For additional information, please contact your local Sales Representative. and are registered trademarks of Wayon orporation. 8 WAYON orporation 7 / 7