Armando Haedo Edwin Campos Marc Latortue. Chapter 11 Instruction Sets: Addressing Modes and Formats

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1 Armando Haedo Edwin Campos Marc Latortue Chapter 11 Instruction Sets: Addressing Modes and Formats

2 Immediate Direct Indirect Register Register Indirect Displacement (Indexed) Stack

3 Simplest form of addressing because Operand is present in instruction Operand = address field e.g. ADD 5 Add 5 to contents of accumulator 5 is operand No memory reference to fetch data Fast Limited range

4 Opcode Instruction Operand Advantage No memory reference besides instruction fetch is required Disadvantage Size of the number is restricted to the size of the address field

5 Operand address is in the address field Effective address (EA) = address field (A) e.g. ADD A Add contents of cell A to accumulator Look in memory at address A for operand Single memory reference to access data No additional calculations to work out effective address Downside is limited address space

6 Opcode Instruction Address A Memory Operand

7 Memory cell pointed to by address field contains the address of (pointer to) the operand EA = (A) Look in A, find address (A) and look there for operand e.g. ADD (A) Add contents of cell pointed to by contents of A to accumulator

8 Advantage Large address space 2 n where n = word length May be nested, multilevel, cascaded e.g. EA = ( (A) ) Multiple memory accesses to find operand Disadvantage Hence slower

9 Opcode Instruction Address A Memory Pointer to operand Operand

10 Operand is held in register named in address filed EA = R Limited number of registers Very small address field needed Shorter instructions Faster instruction fetch

11 No memory access Very fast execution Very limited address space Multiple registers helps performance Requires good assembly programming or compiler writing

12 Opcode Instruction Register Address R Registers Operand

13 EA = (R) Operand is in memory cell pointed to by contents of register R Large address space (2 n ) One fewer memory access than indirect addressing

14 Opcode Instruction Register Address R Memory Registers Pointer to Operand Operand

15 EA = A + (R) Address field hold two values A = base value R = register that holds displacement or vice versa

16 Opcode Register R Instruction Address A Memory Registers Pointer to Operand + Operand

17 A version of displacement addressing R = Program counter, PC EA = A + (PC) i.e. get operand from A cells from current location pointed to by PC c.f locality of reference & cache usage

18 A holds displacement R holds pointer to base address R may be explicit or implicit e.g. segment registers in 80x86

19 A = base R = displacement EA = A + R Good for accessing arrays EA = A + R R++

20 Postindex EA = (A) + (R) Preindex EA = (A+(R))

21 Operand is (implicitly) on top of stack e.g. ADD Pop top two items from stack and add A.k.a. last-in-first-out queue

22 Virtual or effective address is offset into segment Starting address plus offset gives linear address This goes through page translation if paging enabled 12 addressing modes available Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative

23 Based on Intel 8086 processor in 1978 which was full 16-bit design Initial design of x86 processors were designed to be backwards compatible Source of most personal computers and embedded systems Wordsize has been extended twice to 32 and 64 bits Originally referred to as the i386 architecture Most commercially successful for personal computing

24 Variable instruction length, primary two address design Byte-addressing supported Words stored in little-endian order Segment registers (raised memory address limits by 4 bits) Dedicated floating point unit and SIMD (Single Instruction Multiple Data)

25 SIMD and floating point unit have instructions working in parallel on one or two 128 bit words Each word containing 2 or 4 floating point numbers Wide SIMD registers allow x86 processors to load or store 128 bits of memory data into 1 instruction Most registers expressed in opcodes with 3 bits to save encoding space At most 1 operand can be a memory location May also be destination while others can be register or immediate Efficient in instructing cache memory Register-related addressing in referencing operands, especially in stack applications has made the x86 instructions faster and very essential to today s computing needs

26 CISC Design (Complex Instruction Set Computer) Basically means that each set of instructions can execute multiple low-level operations/commands per instruction Low-Level Operations are: Load from memory, arithmetic operation, memory storage Newer x86 processors typically decode and separate instructions into sequences of internal micro operations Benefits: Execute larger subset of instructions, easier to extract parallelism out of code, offers higher performance in multi aspects

27 Floating point unit MMX 3DNow! SSE (Streaming SIMD Extensions) Physical Address Extension (PAE) Virtualization Support

28 Virtual or effective address is offset into segment Starting address plus offset gives linear address This goes through page translation if paging enabled 12 addressing modes available Immediate Register operand Displacement Base Base with displacement Scaled index with displacement Base with index and displacement Base scaled index with displacement Relative

29 Immediate: Operand is included in the instruction Register Operand: Operand is located in a register Displacement: The offset of the operand is part of the instruction as 8-,16- or 32-bit displacement Base: One of 8-,16-, or 32-bit registers contains the effective address Base with Displacement: The instruction contains a displacement to be added to base register

30 Scaled Index with Displacement: The instruction includes a displacement which is added to the index register Base with Index and Displacement: Adds the contents of the base and index registers with the displacement to form the effective address Based Scale Index with Displacement: Adds the contents of the index register and multiplies a scaling factor, contents of base register, and displacement Relative: Displacement is added to PC which points to next instruction

32 Only instructions that reference memory Indirectly through base register plus offset Offset Offset added to or subtracted from base register contents to form the memory address Preindex Memory address is formed as for offset addressing Memory address also written back to base register So base register value incremented or decremented by offset value Postindex Memory address is base register value Offset added or subtracted Result written back to base register Base register acts as index register for preindex and postindex addressing Offset either immediate value in instruction or another register If register scaled register addressing available Offset register value scaled by shift operator Instruction specifies shift size

34 Data Processing Register addressing Value in register operands may be scaled using a shift operator Or mixture of register and immediate addressing Branch Immediate Instruction contains 24 bit value Shifted 2 bits left On word boundary Effective range +/-32MB from PC.

35 Load/store subset of general-purpose registers 16-bit instruction field specifies list of registers Sequential range of memory addresses Increment after, increment before, decrement after, and decrement before Base register specifies main memory address Incrementing or decrementing starts before or after first memory access

37 Layout of bits in an instruction Includes opcode Includes (implicit or explicit) operand(s) Usually more than one instruction format in an Usually more than one instruction format in an instruction set

38 Affected by and affects: Memory size Memory organization Bus structure CPU complexity CPU speed Trade off between powerful instruction repertoire and saving space

39 Number of addressing modes Number of operands Register versus memory Number of register sets Address range Address granularity

45 Stallings chapter 11 Intel and ARM Web sites

46 1. How many addressing modes are there and name them? Seven: Immediate, Direct, Indirect, Register, Register Indirect, Displacement and Stack 2. Match the Addressing: Register Indirect Displacement EA=( (A) ) EA= (R) Indirect EA = A + (R)

47 3. Define displacement addressing? This instruction has two address fields, at least one of which is explicit. The value contained in one address field (value = A) is used directly. The other address field refers to a register whose contents are added to A to produce the effective address. 4. After what processor was the x86 Instruction Set named after? Intel TRUE or FALSE: Base with index and displacement is an addressing mode related to the x86 instruction set? True

48 6. In the immediate addressing mode, what is included in the instruction? The Operand 7. TRUE or FALSE: The x86 wordsize has been extended three times, 32, 64, and 128 bits. False 8. What principle is behind the independence of the other elements in an instruction set from the opcode? Orthoganality 9. In the VAX instruction set Design operands were required to have the same what? Generality in specification

49 cs306/books/artofasm/chapter_6/ch06-1.html uction_set_computer

Computer Organization and Architecture

Computer Organization and Architecture Chapter 11 Instruction Sets: Addressing Modes and Formats Instruction Set Design One goal of instruction set design is to minimize instruction length Another goal