RECONFIGURABLE ARCHITECTURES AND TOOLS TOPIC: APPLICATION MAPPING ONTO XILINX FPGAS WITH ISE

Transcription

1 RECONFIGURABLE ARCHITECTURES AND TOOLS TOPIC: APPLICATION MAPPING ONTO XILINX FPGAS WITH ISE

2 Target FPGA: SPARTAN3E STARTER KIT During this seminar, we will use the Spartan-3E Starter Kit development board. It contains the Spartan-3E XC3S500E FPGA chip. The package is FG320. 2

3 Target FPGA: SPARTAN3E STARTER KIT During this seminar, we will use the Spartan-3E Starter Kit development board. It contains the Spartan-3E XC3S500E FPGA chip. The package is FG320. FPGA 4 press buttons Rotate knob to control position of the illuminated LED Scrolling message 8 LEDs 4 side switches 3

4 Main features The FPGA contains: It includes also: 10,476 logic blocks an LCD 2x16 characters 360Kbits blockram 4 slide switches 72Kbits distributed memory 4 push buttons 20 multiplies 18x18bit and 4DCMs. 8 LEDs Their equivalent number of cells is 500K. 1 VGA output The package has 320 pins 2 serial ports 232 of them are available to designer 1 PS/2 The board contains: 1 10/100 Ethernet PHY 64MB DDR SDRAM A2D and D2A converters 16MB parallel NOR Flash Additional expansion ports 16MB serial SPI Flash 4MB ROM for storing bitstream files 1 CPLD The clock is tuned to 500MHz, whereas there is also a clock input pins. 4

5 XILINX ISE The main screen shows info regarding files and reports Logs, warnings and errors are shown in the bottom Tree-based representation of source files is in upmost-left corner It is possible to insert additional source files, or to edit existing files, with right-click Tree-based representation corresponds to the design hierarchy of entities 5

6 XILINX ISE In the left side, there the available tasks supported by ISE: They depend on the source files Tasks related to physical implementation are shown if the top level entity is selected The main tasks for physical implementation are: Synthesis Implementation (translate, map, place & route) Bitstream generation A report file is retrieved from ach step These reports contain useful info about the design implementation 6

7 XILINX ISE The synthesis output is a netlist file consisted of basic primitives for the specific FPGA device. Primitives can be either physical or logical components that correspond to FPGA blocks The synthesis report contains: Area estimation in term of number of slices Detail number of different primitives (LUT1, LUT2, etc) An estimation regarding the maximum combinational delay (critical path) Note that area and delay estimation are not accurate since: Primitives are clustered in CLBs in next step Delay is tightly firmed to routing connections, which are retrieved after P&R Synthesis can also be performed with other tools (e.g. Leonardo Spectrum) 7

8 Then, application is translated XILINX ISE During this task, netlist files (in EDIF format), are appropriately combined and linked to a new netlist file in Xilinx format It is also possible to use EDIF files, as a starting point for the design EDIF is a industry standard Design constraints (.ucf file) are also read These constraints affects: Mapping between FPGA pins and design ports Timing constraints (e.g. clock and frequency definitions, maximum combinational delay from signal to signal, etc) Spatial constraints over the FPGA These constraints can be inserted either as text or with tools (user constraints sub-tree) If constraint file contains errors, some of them might be reported here, even though these constraints are taken into consideration later in the design flow 8

9 XILINX ISE Next, we perform application mapping During this: An additional netlist optimization is performed Functionalities are appropriately clustered into CLBs This step can fail if part(s) of the source code does not technology mapped properly to the underline FPGA, even though synthesis step does not report any error. 9

10 XILINX ISE After technology mapping, placement and route is performed This is a computational intensive task Alternative placements and routing are evaluated in order to meet design constraints/goals Non acceptable solutions can be derived, since there are: Placements where routing is not feasible Placements where routing does not meet timing constraints P&R algorithms take into account timing/power/area constraints. Reported values regarding area utilization and critical path are higher, as compared to corresponding estimated values from synthesis step 10

11 XILINX ISE Last step deals with bitstream generation The derived bitstream file corresponds to the design that has previously successfully P&R FPGA programming is executed with impact process This task transfers configuration data (in bit level) into programming SRAM memory of the FPGA 11

12 New Project Wizard Select File->New Project from the main menu At the wizard window, we give a name for the new project and click Next button 12

13 New Project Wizard Next, we select the appropriate values regarding our FPGA device Family, device, package, speed Format of source files, synthesis/simulation tool 13

14 Insert design Then, we insert a new source file (in VHDL format) Right-click on the device xc3s500e-4fg320 14

15 Insert design Give the file name, entity name, architecture name, number and type of I/O ports. 15

16 Target application This design transfer the value from a slide switch to an output led Control is performed every 2.62ms (clock period 20ns (or frequency 50MHz) A press button is used for reset entity fpgademo is port(clk: in std_logic; button: in std_logic; switch: in std_logic; led: out std_logic); end fpgademo; architecture fpgademo of fpgademo is signal counter: natural range 0 to 2**17-1; --0 every 2.62ms begin process(clk, button) begin if button='1' then counter<=0; elsif clk'event and clk='1' then counter<=counter+1; if counter=2**17-1 then led<=switch; end if; end if; end process; end fpgademo; 16

17 Source properties 17

18 Constraints file (UCF) Press + icon to show all the available options Execute User Contraints/Edit Contraints (Text) Choose to generate a new file Then, insert the following constraints File with constraints NET "button" LOC = "K17" IOSTANDARD = LVTTL PULLDOWN ; NET "switch" LOC = "L13" IOSTANDARD = LVTTL PULLUP ; #switch 0 NET "led" LOC = "F12" IOSTANDARD = LVTTL SLEW = SLOW DRIVE = 8 ; #led 0 NET "clk" LOC = "C9" IOSTANDARD = LVCMOS33 ; NET "clk" PERIOD = 20.0ns HIGH 40%; 18

19 Constraints file (UCF) With respect to these constraints, we map: Ports of the top level entity in VHDL with FPGA pins This can also be applied with GUI (Assign Package Pins) Their electrical parameters IOSTANDARD for the Ε/Ε standard, PULLDOWN or PULLUP for resolving what occurs if a port does not have input signal, DRIVE for the output current. We also define the clock and period These parameters are defined by the target development board For the purposes of this seminar, we use SPARTAN3E Starter Kit Values are given in the manual 19

20 Select design goals 20

21 Select design goals 21

22 Design implementation We can start design implementation by running Check Syntax at the Synthesize XST sub-tree If errors occur, we correct them and proceed to synthesis Each command is executed with right-click and selecting Run from the drop-down menu 22

23 Design implementation Then, execute each of the design steps sequentially 23

24 Power estimation 24

25 Power estimation It is possible to estimate the power consumption of design For this purpose, a number of parameters has to be defined: Clock frequency, default activity rates, Power is computed at different levels: By clock domain, resource type (logic/signal), I/Os 25

26 Power estimation Note to update power analysis after modifications 26

27 Program FPGA In case there is no error(s),we are ready to program FPGA Connect board with PC through a USB cable Turn-on power supply 27

28 Program FPGA We execute Configure Device (impact) at the Generate Programming File sub-tree Note not to execute many instances simultaneously, since port might be reserved 28

29 Program FPGA Select Configure Devices using Boundary-Scan chain (JTAG) and press Finish button A blue color box with identify succeeded message will be arise 29

30 Program FPGA In the Assign New Configuration File window, we press Cancel All button 30

31 Program FPGA A windows with a chain of 3 programmable modules arises The first module corresponds to the FPGA The rest two are: a 4MB ROM and the CPLD Select (right-click) FPGA module and execute Assign New Configuration File 31

32 Program FPGA Select configuration file (.bit) from the project folder (fpgademo.bit) Press OK at the warning about jtagclk 32

33 Program FPGA Right-click and select Program Press OK at the next window 33

34 Program FPGA If there is no error, a message Program Succeeded will be displayed Move up-down slide switch 0 (most left) at the board and look led 0 (most left) that flash Press button btn_south for reset 34

35 Program FPGA During design implementation it is possible to have reports about the different tasks 35