ECE 5730 Memory Systems

Transcription

1 ECE 5730 Memory Systems Spring 2009 Overview of DRAMs Lecture 11: 1

2 Quiz 6 on Tuesday Announcements Quiz 5 Average = 4.1/10 (ouch!) Exam I Wednesday, March 11, 6:30-9:30pm or 6-9pm or Makeup: Friday, March 13, 12-3pm or Lecture 11: 2

3 Recall the Memory Hierarchy Multiple levels of memory, each optimized for an appropriate cost/performance design point cache hierarchy main memory (MM) { [ov.1] Lecture 11: 3

4 Recall the Memory Hierarchy Multiple levels of memory, each optimized for an appropriate cost/performance design point Technology Bytes per access Latency per access Energy per access Cost per MB On-chip cache s of ps 1 nj $1-100 MM storage component Off-chip cache DRAM (internally fetched) ns ns nj nj per device $1-10 $0.1 Disk 1000 ms nj $0.001 Lecture 11: 4

5 Latency Bandwidth Concurrency Capacity Modularity Power Cost MM Design Tradeoffs Lecture 11: 5

6 High-level DRAM Organization [7.3] Lecture 11: 6

7 High-level DRAM Organization [7.4] Lecture 11: 7

8 MM Using Multiple DRAMs MM bus [10.8] Lecture 11: 8

9 MM Using Multiple DRAMs 256Mb-4Gb 256MB-16GB Bank: Collection of DRAM arrays that are always accessed together Rank: Collection of DRAM chips that are always accessed together DIMM: dual in-line memory module (contains 1-4 ranks) [7.5] Lecture 11: 9

10 The Evolution of the Modern DRAM [12.1] Lecture 11: 10

11 Asynchronous DRAM Really should be called unclocked DRAM Access proceeds in a combinational logic fashion (no flip-flops) To save on packaging costs, address is provided in two phases using the same address inputs Row address to pick the desired row or DRAM page Column address to output a subset of those bits Lecture 11: 11

12 Asynchronous DRAM Row and column address phases sent 1st share the same input pins sent 2nd [7.8] Lecture 11: 12

13 Read access timing Asynchronous DRAM Address control signals (active low) [12.7] Row address strobe (RAS): latches row address and activates the selected row Column address strobe (CAS): latches column address and serves as the output enable Lecture 11: 13

14 Read access timing Asynchronous DRAM Major timing parameters [12.7] RAS to CAS delay (t RCD ): minimum time between assertion of RAS and data available at sense amps CAS access time (t CAS ): maximum time between assertion of CAS and valid data Lecture 11: 14

15 Read access timing Asynchronous DRAM Major timing parameters [12.7] RAS cycle time (t RC ): minimum required time between two assertions of RAS (includes precharge time, t RP ) CAS hold time: minimum time data remains valid after deassertion of CAS Lecture 11: 15

16 Fast Page Mode DRAM Rapid access to bits in the currently open page sent 1st share the same input pins sent 2nd get more bits by just changing the column address! [7.8] Lecture 11: 16

17 Fast Page Mode DRAM [12.6] 4M x 16 FPM DRAM Lecture 11: 17

18 FPM DRAM Read Accesses [12.7] Lecture 11: 18

19 Extended Data Out (EDO) DRAM Output Enable (OE) signal added to control tristate input on output driver Permits CAS to be cycled quicker than FPM Lecture 11: 19

20 EDO DRAM Read Accesses [12.8] Lecture 11: 20

21 Burst EDO DRAM DRAM automatically increments column address internally to burst multiple units of data [12.9] Lecture 11: 21

22 Synchronous DRAM (SDRAM) Asynchronous DRAMs had limited bandwidth and concurrency Limited overlap of address and data phases of consecutive accesses Single bank of arrays SDRAMs greatly increase concurrency and bandwidth by Registering the inputs and outputs Incorporating multiple independent banks Increasing the amount of on-chip control intelligence Lecture 11: 22

23 SDRAM Device Architecture [12.10] Lecture 11: 23

24 SDRAM Commands [Micron00] Lecture 11: 24

25 SDRAM Access Protocol [12.12] Lecture 11: 25

26 Programmable Mode Register [12.11] Lecture 11: 26

27 Double Data Rate (DDR) SDRAM Address and Command buses more heavily loaded than data bus [10.13] Lecture 11: 27

28 Double Data Rate (DDR) SDRAM Run data bus on both edges of the clock DQS: (shared) data strobe signal controlled by the source of the data [12.16] Lecture 11: 28

29 DDR SDRAM I/O Architecture [12.17] 2-bit prefetch architecture Lecture 11: 29

30 DDR2 and DDR3 Increased prefetch length 4 in DDR2 and 8 in DDR3 Some interface signaling changes E.g., differential DQS Some additional commands Lecture 11: 30

31 DDR2 I/O Architecture [12.19] Lecture 11: 31

32 SDRAM and DDRx Comparison [Choudhary08] Lecture 11: 32

33 DRAM Scaling Trends Random row access cycle time increased 7% per year Transfer data rate doubled every three years [12.22] Lecture 11: 33

34 Next Time More on DRAMs Lecture 11: 34