DDR2 Specific SDRAM Functions
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- Clinton Haynes
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1 JEDEC Standard No. 2-C Page DDR2 Specific SDRAM Functions DDR2 SDRAM EMRS2 and EMRS For DDR2 SDRAMs, both bits BA and BA must be decoded for Mode/Extended Mode Register Set commands. Users must initialize all four Mode Registers. The registers may be initialized in any order. Notes:. Background: This is to ensure future compatibility if/when any new feature is assigned to a bit or bits in EMR(2) or EMR(). 2. EMR(2) and EMR(): At this time, there are no features defined which use bit(s) in EMR(2) or EMR(). EMR(2) Programming: * BA2 BA BA A5 ~ A A2 A A A9 A8 A7 A6 A5 A4 A A2 A A * * Extended Mode Register(2) *: EMRS(2) is reserved for future use and all bits except BA and BA must be programmed to when setting the mode register during initialization. EMR() Programming: * BA2 BA BA A5 ~ A A2 A A A9 A8 A7 A6 A5 A4 A A2 A A * * Extended Mode Register() *: EMRS() is reserved for future use and all bits except BA and BA must be programmed to when setting the mode register during initialization. Release
2 JEDEC Standard No. 2-C Page DDR2(x2) SDRAM MR Definition BA2 BA BA A5-A A2 A A A9 A8 A7 A6 A5 A4 A A2 A A * * PD WR DLL TM CAS latency BT Burst length Mode Register A8 DLL Reset No Yes BA BA MRS mode MR EMR() EMR(2) EMR() A2 Active power down exit time Fast exit (use txard) Slow exit (use txards) A7 mode Normal Test Write recovery for autoprecharge A A A9 WR (Optional) 8 (Optional) * 2 A DDR2-4 DDR2-5 DDR2-667 DDR2-8 DDR2-66 Burst Type Sequential Interleave Burst Length A2 A A6 A5 A4 CAS Latency 2 (Optional) (speed bin determined)* 4 5 (speed bin determined)* 6 (speed bin determined)* 7 (speed bin determined)* A BL 4 8 Notes:. BA2 and A-A5 are reserved for future use and must be set to when programming the MR. 2. For DDR2-4/5, WR (write recovery for autoprecharge) min is determined by tck max and WR max is determined by tck min. WR in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer (WR[cycles] = RU{ twr[ns] / tck[ns] }, where RU stands for round up). For DDR2-667/8/66, WR min is determined by tck(avg) max and WR max is determined by tck(avg) min. WR[cycles] = RU{ twr[ns] / tck(avg)[ns] }, where RU stands for round up. The mode register must be programmed to this value. This is also used with trp to determine tdal.. Speed bin determined. Not required on all speed bins. * A2 must be driven by the system to properly program the mode registers. Release 8
3 JEDEC Standard No. 2-C Page..5.5 DDR2(x2) SDRAM EMR() Definition BA2 BA BA A5-A A2 A A A9 A8 A7 A6 A5 A4 A A2 A A * * Qoff * DQS OCD program Rtt* 5 Additive latency Rtt* 5 D.I.C* 6 DLL Extended Mode Register () A DLL BA BA MRS mode MR EMR () EMR (2) EMR () A9 A8 A7 OCD Calibration Program OCD calibration mode exit: main setting Drive () Drive () Adjust mode* 2 OCD Calibration default* A5 A4 A Additive Latency (Optional) 6 (Optional) A2 Qoff (Optional)* 4 Output buffers enabled Output buffers disabled A DQS A (DQS enable) () () Strobe Function Matrix DQS DQS DQS DQS DQS High-Z Notes:. BA2 and A-A5, A are reserved for future use, and must be set to when programming the EMR (). 2. When adjust mode is issued, AL from previously set value must be applied.. After setting to default, OCD mode needs to be exited by setting A9 to A7 to. Refer to the chapter Off-Chip Driver (OCD) Impedance Adjustment for detailed information. 4. Output disabled - DQs, DQSs, DQSs. This feature is used in conjunction with DIMM IDD measurements when IDDQ is not desired to be included. 5. Rtt values are programmed using EMR () [A6, A2] and EMR (2) [A]. 6. Driver impedance values are programmed using EMR () [A] and EMR (2) [A2]. * A2 must be driven by the system to properly program the mode registers. Release 8
4 JEDEC Standard No. 2-C Page DDR2(x2) SDRAM EMR(2) Definition BA2 BA BA A5-A A2 A A A9 A8 A7 A6 A5 A4 A A2 A A * * D.I.C* 6 Rtt* 5 * SRF * DCC* 4 PASR* Extended Mode Register (2) BA BA MRS mode MR A DCC (Optional)* 4 EMR() EMR(2) EMR() A2 A A Partial Array Self Refresh for 4 Banks (Optional) Full array Half Array (BA[:]=&) A7 High Temperature Self Refresh Rate (Optional)* 2 Quarter Array (BA[:]=) Not defined /4 array (BA[:]=, &) Half array (BA[:]=&) Quarter array (BA[:]=) Not defined A2 A A Partial Array Self Refresh for 8 Banks (Optional) Full array Half Array (BA[2:]=,,&) Quarter Array (BA[2:]=&) /8th array (BA[2:] = ) /4 array (BA[2:]=,,,,&) Half array (BA[2:]=,,&) Quarter array (BA[2:]=&) /8th array (BA[2:]=) Notes:. BA2 and A4-A6, A8-A, A-A5 are reserved for future use and must be set to when programming the EMR(2). 2. As industry adoption of high temperature parts proceeds, users need to determine if a DRAM supports High Temperature Self-Refresh Rate mode before attempting to use it in that mode. JEDEC standard DDR2 SDRAM Module user can look at DDR2 SDRAM Module SPD field Byte 49 bit []. If the high temperature self-refresh mode is supported then controller can set the EMR(2)[A7] bit to enable the self-refresh rate in case of higher than 85 C temperature self-refresh operation. For the loose part user, please refer to DRAM Manufacturer s part number and data sheet to check the high temperature self-refresh rate availability.. Optional in DDR2 SDRAM. If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self refresh is entered. Data integrity will be maintained if tref conditions are met and no Self Refresh command is issued.if the PASR feature is not supported, EMR(2)[A-A2] must be set to when programming EMR(2). 4. Optional in DDR2 SDRAM. JEDEC standard DDR2 SDRAM may or may not have DCC (Duty Cycle Corrector) implemented, and in some of the DRAMs implementing DCC, user may be given the controllability of DCC thru EMR(2) [A] bit. JEDEC standard DDR2 SDRAM users can look at manufacturer's data sheet to check if the DRAM part supports DCC controllability. If Optional DCC Controllability is supported, user may enable or disable the DCC by programming EMR(2)[A] accordingly. If the controllability feature is not supported, EMR(2)[A] must be set to when programming EMR(2). 5. Rtt values are programmed using EMR() [A6, A2] and EMR(2) [A]. 6. Driver impedance values are programmed using EMR () [A] and EMR (2) [A2]. * A2 must be driven by the system to properly program the mode registers. Release 8
![(BA[:]=&) A7 High Temperature Self Refresh Rate (Optional)* 2 Quarter Array (BA[:]=) Not defined /4 array (BA[:]=, &) Half array (BA[:]=&) Quarter array (BA[:]=) Not defined A2 A A Partial Array Self](/docs-images/43/2595558/images/page_4.jpg "Refresh for 8 Banks (Optional) Full array Half Array (BA[2:]=,,&) Quarter Array (BA[2:]=&) /8th array (BA[2:] = ) /4 array (BA[2:]=,,,,&) Half array (BA[2:]=,,&) Quarter array (BA[2:]=&) /8th array")
5 JEDEC Standard No. 2-C Page Rtt Programming and Driver Impedance Programming Use A, A2 in EMR(2) for RTT, Ron extension EMR () EMR (2) A6 A2 A Rtt (NOMINAL) ODT d 75Ω 5Ω 5Ω (Optional) 225Ω (Optional) EMR () EMR (2) A A2 Ron (NOMINAL) Full Reduced /4 (Optional) DDR2(x2) SDRAM EMR() Definition Note:. All bits in EMR() except BA and BA are reserved for future use and must be set to when programming the EMR(). BA2 BA BA A5-A A2 A A A9 A8 A7 A6 A5 A4 A A2 A A * * Extended Mode Register() Release 8
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