C8051F350/1/2/3. Notes. 2 Rev. 0.4

Transcription

1 8 k ISP Flash MCU Family Analog Peripherals - 24 or 16-Bit ADC No missing codes % nonlinearity Programmable conversion rates up to 1 ksps 8-Input multiplexer 1x to 128x PGA Built-in temperature sensor - Two 8-Bit Current Output DACs - Comparator Programmable hysteresis and response time Configurable as interrupt or reset source Low current (0.4 µa) On-chip Debug - On-chip debug circuitry facilitates full speed, nonintrusive in-system debug (No emulator required) - Provides breakpoints, single stepping, inspect/modify memory and registers - Superior performance to emulation systems using ICE-Chips, target pods, and sockets - Low Cost, Complete Development Kit Supply Voltage 2.7 to 3.6 V - Typical operating current: MHz; 32 khz - Typical stop mode current:0.1 µa Temperature Range: -40 to +85 C High Speed 8051 µc Core - Pipelined Instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 50 MIPS throughput - Expanded interrupt handler Memory Bytes ( ) On-Chip RAM - 8k Bytes Flash; In-system programmable in 512- byte Sectors Digital Peripherals - 17 Port I/O; All 5 V tolerant with high sink current - Enhanced UART, SMBus, and SPI Serial Ports - Four general purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with three capture/compare modules - Real time clock mode using PCA or timer and external clock source Clock Sources - Internal Oscillator: 24.5 MHz with ± 2% accuracy supports UART operation - External Oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) - Clock multiplier to achieve 50 MHz internal clock - Can switch between clock sources on-the-fly 28-Pin MLP or 32-PIN LQFP Package - 5 x 5 mm PCB footprint with 28-MLP A M U X ANALOG PERIPHERALS TEMP SENSOR 24-bit 1ksps ADC + 8-bit IDAC 8-bit IDAC - VOLTAGE COMPARATOR DIGITAL I/O UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CROSSBAR Port 0 Port 1 P MHz PRECISION INTERNAL OSCILLATOR WITH CLOCK MULTIPLIER HIGH-SPEED CONTROLLER CORE 8KB 8051 CPU 768 B SRAM ISP FLASH (50 MIPS) FLEXIBLE DEBUG POR WDT INTERRUPTS CIRCUITRY Preliminary Rev /04 Copyright 2004 by Silicon Laboratories C8051F350/1/2/3-DS04 This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

2 Notes 2 Rev. 0.4

3 Table of Contents 1. System Overview CIP-51 Microcontroller Fully 8051 Compatible Instruction Set Improved Throughput Additional Features On-Chip Debug Circuitry On-Chip Memory or 16-Bit Analog to Digital Converter (ADC0) Two 8-bit Current-Mode DACs Programmable Comparator Serial Ports Port Input/Output Programmable Counter Array Absolute Maximum Ratings Global DC Electrical Characteristics Pinout and Package Definitions or 16-Bit Analog to Digital Converter (ADC0) Configuration Voltage Reference Selection Analog Inputs Programmable Gain Amplifier Input Buffers Modulator Clock Decimation Ratio Calibrating the ADC Internal Calibration System Calibration Calibration Coefficient Storage Performing Conversions Single Conversions Continuous Conversions ADC Output Error Conditions Offset DAC Burnout Current Sources Analog Multiplexer Bit Current Mode DACS (IDA0 and IDA1) IDAC Output Scheduling Update Output On-Demand Update Output Based on Timer Overflow Update Output Based on CNVSTR Edge IDAC Output Mapping IDAC External Pin Connections Rev

4 7. Voltage Reference Temperature Sensor Comparator Comparator0 Inputs and Outputs CIP-51 Microcontroller Instruction Set Instruction and CPU Timing MOVX Instruction and Program Memory Register Descriptions Power Management Modes Idle Mode Stop Mode Memory Organization and SFRs Program Memory Data Memory General Purpose Registers Bit Addressable Locations Stack Special Function Registers Interrupt Handler MCU Interrupt Sources and Vectors Interrupt Priorities Interrupt Latency Interrupt Register Descriptions External Interrupts Prefetch Engine Reset Sources Power-On Reset Power-Fail Reset / VDD Monitor External Reset Missing Clock Detector Reset Comparator0 Reset PCA Watchdog Timer Reset Flash Error Reset Software Reset Flash Memory Programming The Flash Memory Flash Lock and Key Functions Flash Erase Procedure Flash Write Procedure Non-volatile Data Storage Security Options External RAM Oscillators Programmable Internal Oscillator Rev. 0.4

5 17.2.External Oscillator Drive Circuit Clocking Timers Directly Through the External Oscillator External Crystal Example External RC Example External Capacitor Example Clock Multiplier System Clock Selection Port Input/Output Priority Crossbar Decoder Port I/O Initialization General Purpose Port I/O SMBus Supporting Documents SMBus Configuration SMBus Operation Arbitration Clock Low Extension SCL Low Timeout SCL High (SMBus Free) Timeout Using the SMBus SMBus Configuration Register SMB0CN Control Register Data Register SMBus Transfer Modes Master Transmitter Mode Master Receiver Mode Slave Receiver Mode Slave Transmitter Mode SMBus Status Decoding UART Enhanced Baud Rate Generation Operational Modes Bit UART Bit UART Multiprocessor Communications Serial Peripheral Interface (SPI0) Signal Descriptions Master Out, Slave In (MOSI) Master In, Slave Out (MISO) Serial Clock (SCK) Slave Select (NSS) SPI0 Master Mode Operation SPI0 Slave Mode Operation SPI0 Interrupt Sources Serial Clock Timing Rev

6 21.6.SPI Special Function Registers Timers Timer 0 and Timer Mode 0: 13-bit Counter/Timer Mode 1: 16-bit Counter/Timer Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) Timer bit Timer with Auto-Reload bit Timers with Auto-Reload Timer bit Timer with Auto-Reload bit Timers with Auto-Reload Programmable Counter Array PCA Counter/Timer Capture/Compare Modules Edge-triggered Capture Mode Software Timer (Compare) Mode High Speed Output Mode Frequency Output Mode Bit Pulse Width Modulator Mode Bit Pulse Width Modulator Mode Watchdog Timer Mode Watchdog Timer Operation Watchdog Timer Usage Register Descriptions for PCA C2 Interface C2 Interface Registers C2 Pin Sharing Rev. 0.4

7 List of Figures and Tables 1. System Overview Table 1.1. Product Selection Guide Figure 1.1. C8051F350 Block Diagram Figure 1.2. C8051F351 Block Diagram Figure 1.3. C8051F352 Block Diagram Figure 1.4. C8051F353 Block Diagram Figure 1.5. Development/In-System Debug Diagram Figure 1.6. Memory Map Figure 1.7. ADC0 Block Diagram Figure 1.8. IDAC Block Diagram Figure 1.9. Comparator0 Block Diagram Figure Port I/O Functional Block Diagram Figure PCA Block Diagram Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F350/1/2/ Figure 4.1. LQFP-32 Pinout Diagram (Top View) Figure 4.2. MLP-28 Pinout Diagram (Top View) Figure 4.3. LQFP-32 Package Diagram Table 4.2. LQFP-32 Package Dimensions Figure 4.4. MLP-28 Package Drawing Table 4.3. MLP-28 Package Dimensions Figure 4.5. Typical MLP-28 Landing Diagram Figure 4.6. Typical MLP-28 Solder Paste Diagram or 16-Bit Analog to Digital Converter (ADC0) Figure 5.1. ADC0 Block Diagram Figure 5.2. ADC0 Buffer Control Figure 5.3. ADC0 Offset Calibration Register Coding Figure 5.4. ADC0 Gain Calibration Register Coding Table 5.1. ADC0 Unipolar Output Word Coding (AD0POL = 0) Table 5.2. ADC0 Bipolar Output Word Coding (AD0POL = 1) Figure 5.5. ADC0CN: ADC0 Control Register Figure 5.6. ADC0CF: ADC0 Configuration Register Figure 5.7. ADC0MD: ADC0 Mode Register Figure 5.8. ADC0CLK: ADC0 Modulator Clock Divisor Figure 5.9. ADC0DECH: ADC0 Decimation Ratio Register High Byte Figure ADC0DECL: ADC0 Decimation Ratio Register Low Byte Figure ADC0DAC: ADC0 Offset DAC Register Figure ADC0BUF: ADC0 Input Buffer Control Register Figure ADC0STA: ADC0 Status Register Rev

8 Figure ADC0COH: ADC0 Offset Calibration Register High Byte Figure ADC0COM: ADC0 Offset Calibration Register Middle Byte Figure ADC0COL: ADC0 Offset Calibration Register Low Byte Figure ADC0CGH: ADC0 Gain Calibration Register High Byte Figure ADC0CGM: ADC0 Gain Calibration Register Middle Byte Figure ADC0CGL: ADC0 Gain Calibration Register Low Byte Figure ADC0H: ADC0 Conversion Register (SINC3 Filter) High Byte Figure ADC0M: ADC0 Conversion Register (SINC3 Filter) Middle Byte Figure ADC0L: ADC0 Conversion Register (SINC3 Filter) Low Byte Figure ADC0FH: ADC0 Conversion Register (Fast Filter) High Byte Figure ADC0FM: ADC0 Conversion Register (Fast Filter) Middle Byte Figure ADC0FL: ADC0 Conversion Register (Fast Filter) Low Byte Figure ADC0 Multiplexer Connections Figure ADC0MUX: ADC0 Analog Multiplexer Control Register Table 5.3. ADC0 Electrical Characteristics Table 5.4. ADC0 SINC3 Filter Typical RMS Noise (µv) Bit Current Mode DACS (IDA0 and IDA1) Figure 6.1. IDAC Functional Block Diagram Figure 6.2. IDAC Data Word Mapping Figure 6.3. IDA0CN: IDA0 Control Register Figure 6.4. IDA0: IDA0 Data Word Register Figure 6.5. IDA1CN: IDA1 Control Register Figure 6.6. IDA1: IDA1 Data Word Register Figure 6.7. IDAC Pin Connections Table 6.1. IDAC Electrical Characteristics Voltage Reference Figure 7.1. Reference Circuitry Block Diagram Figure 7.2. REF0CN: Reference Control Register Table 7.1. Voltage Reference Electrical Characteristics Temperature Sensor Figure 8.1. Temperature Sensor Block Diagram Table 8.1. Temperature Sensor Electrical Characteristics Figure 8.2. Single Channel Transfer Function Figure 8.3. Differential Transfer Function Comparator Figure 9.1. Comparator0 Functional Block Diagram Figure 9.2. Comparator Hysteresis Plot Figure 9.3. CPT0CN: Comparator0 Control Register Figure 9.4. CPT0MD: Comparator0 Mode Selection Register Figure 9.5. Comparator Pin Connections Figure 9.6. CPT0MX: Comparator0 MUX Selection Register Table 9.1. Comparator Electrical Characteristics CIP-51 Microcontroller Figure CIP-51 Block Diagram Table CIP-51 Instruction Set Summary Rev. 0.4

9 Figure SP: Stack Pointer Figure DPL: Data Pointer Low Byte Figure DPH: Data Pointer High Byte Figure PSW: Program Status Word Figure ACC: Accumulator Figure B: B Register Figure PCON: Power Control Memory Organization and SFRs Figure Memory Map Table Special Function Register (SFR) Memory Map Table Special Function Registers Interrupt Handler Table Interrupt Summary Figure IE: Interrupt Enable Figure IP: Interrupt Priority Figure EIE1: Extended Interrupt Enable Figure EIP1: Extended Interrupt Priority Figure IT01CF: INT0/INT1 Configuration Register Prefetch Engine Figure PFE0CN: Prefetch Engine Control Register Reset Sources Figure Reset Sources Figure Power-On and VDD Monitor Reset Timing Figure VDM0CN: VDD Monitor Control Figure RSTSRC: Reset Source Register Table Reset Electrical Characteristics Flash Memory Figure Flash Memory Map Figure PSCTL: Program Store R/W Control Figure FLKEY: Flash Lock and Key Register Figure FLSCL: Flash Scale Register Table Flash Electrical Characteristics External RAM Figure EMI0CN: External Memory Interface Control Oscillators Figure Oscillator Diagram Figure OSCICN: Internal Oscillator Control Register Figure OSCICL: Internal Oscillator Calibration Register Figure OSCXCN: External Oscillator Control Register Figure CLKMUL: Clock Multiplier Control Register Figure CLKSEL: Clock Select Register Table Oscillator Electrical Characteristics Port Input/Output Figure Port I/O Functional Block Diagram Figure Port I/O Cell Block Diagram Rev

10 Figure Crossbar Priority Decoder with No Pins Skipped Figure Crossbar Priority Decoder with Crystal Pins Skipped Figure XBR0: Port I/O Crossbar Register Figure XBR1: Port I/O Crossbar Register Figure P0: Port0 Register Figure P0MDIN: Port0 Input Mode Register Figure P0MDOUT: Port0 Output Mode Register Figure P0SKIP: Port0 Skip Register Figure P1: Port1 Register Figure P1MDIN: Port1 Input Mode Register Figure P1MDOUT: Port1 Output Mode Register Figure P1SKIP: Port1 Skip Register Figure P2: Port2 Register Figure P2MDOUT: Port2 Output Mode Register Table Port I/O DC Electrical Characteristics SMBus Figure SMBus Block Diagram Figure Typical SMBus Configuration Figure SMBus Transaction Table SMBus Clock Source Selection Figure Typical SMBus SCL Generation Table Minimum SDA Setup and Hold Times Figure SMB0CF: SMBus Clock/Configuration Register Figure SMB0CN: SMBus Control Register Table Sources for Hardware Changes to SMB0CN Figure SMB0DAT: SMBus Data Register Figure Typical Master Transmitter Sequence Figure Typical Master Receiver Sequence Figure Typical Slave Receiver Sequence Figure Typical Slave Transmitter Sequence Table SMBus Status Decoding UART Figure UART0 Block Diagram Figure UART0 Baud Rate Logic Figure UART Interconnect Diagram Figure Bit UART Timing Diagram Figure Bit UART Timing Diagram Figure UART Multi-Processor Mode Interconnect Diagram Figure SCON0: Serial Port 0 Control Register Figure SBUF0: Serial (UART0) Port Data Buffer Register Table Timer Settings for Standard Baud Rates Using the Internal Oscillator 174 Table Timer Settings for Standard Baud Rates Using an External Oscillator 174 Table Timer Settings for Standard Baud Rates Using an External Oscillator 175 Table Timer Settings for Standard Baud Rates Using an External Oscillator 175 Table Timer Settings for Standard Baud Rates Using an External Oscillator Rev. 0.4

11 Table Timer Settings for Standard Baud Rates Using an External Oscillator Serial Peripheral Interface (SPI0) Figure SPI Block Diagram Figure Multiple-Master Mode Connection Diagram Figure Wire Single Master and Single Slave Mode Connection Diagram Figure Wire Single Master and Slave Mode Connection Diagram Figure Data/Clock Timing Relationship Figure SPI0CFG: SPI0 Configuration Register Figure SPI0CN: SPI0 Control Register Figure SPI0CKR: SPI0 Clock Rate Register Figure SPI0DAT: SPI0 Data Register Figure SPI Master Timing (CKPHA = 0) Figure SPI Master Timing (CKPHA = 1) Figure SPI Slave Timing (CKPHA = 0) Figure SPI Slave Timing (CKPHA = 1) Table SPI Slave Timing Parameters Timers Figure T0 Mode 0 Block Diagram Figure T0 Mode 2 Block Diagram Figure T0 Mode 3 Block Diagram Figure TCON: Timer Control Register Figure TMOD: Timer Mode Register Figure CKCON: Clock Control Register Figure TL0: Timer 0 Low Byte Figure TL1: Timer 1 Low Byte Figure TH0: Timer 0 High Byte Figure TH1: Timer 1 High Byte Figure Timer 2 16-Bit Mode Block Diagram Figure Timer 2 8-Bit Mode Block Diagram Figure TMR2CN: Timer 2 Control Register Figure TMR2RLL: Timer 2 Reload Register Low Byte Figure TMR2RLH: Timer 2 Reload Register High Byte Figure TMR2L: Timer 2 Low Byte Figure TMR2H Timer 2 High Byte Figure Timer 3 16-Bit Mode Block Diagram Figure Timer 3 8-Bit Mode Block Diagram Figure TMR3CN: Timer 3 Control Register Figure TMR3RLL: Timer 3 Reload Register Low Byte Figure TMR3RLH: Timer 3 Reload Register High Byte Figure TMR3L: Timer 3 Low Byte Figure TMR3H Timer 3 High Byte Programmable Counter Array Figure PCA Block Diagram Figure PCA Counter/Timer Block Diagram Table PCA Timebase Input Options Rev

12 Figure PCA Interrupt Block Diagram Table PCA0CPM Register Settings for PCA Capture/Compare Modules Figure PCA Capture Mode Diagram Figure PCA Software Timer Mode Diagram Figure PCA High Speed Output Mode Diagram Figure PCA Frequency Output Mode Figure PCA 8-Bit PWM Mode Diagram Figure PCA 16-Bit PWM Mode Figure PCA Module 2 with Watchdog Timer Enabled Table Watchdog Timer Timeout Intervals Figure PCA0CN: PCA Control Register Figure PCA0MD: PCA Mode Register Figure PCA0CPMn: PCA Capture/Compare Mode Registers Figure PCA0L: PCA Counter/Timer Low Byte Figure PCA0H: PCA Counter/Timer High Byte Figure PCA0CPLn: PCA Capture Module Low Byte Figure PCA0CPHn: PCA Capture Module High Byte C2 Interface Figure C2ADD: C2 Address Register Figure DEVICEID: C2 Device ID Register Figure REVID: C2 Revision ID Register Figure FPCTL: C2 Flash Programming Control Register Figure FPDAT: C2 Flash Programming Data Register Figure Typical C2 Pin Sharing Rev. 0.4

13 1. System Overview C8051F350/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) 24 or 16-bit single-ended/differential ADC with analog multiplexer Two 8-bit Current Output DACs Precision programmable 24.5 MHz internal oscillator 8 kb of on-chip Flash memory 768 bytes of on-chip RAM SMBus/I2C, Enhanced UART, and SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable counter/timer array (PCA) with three capture/compare modules and watchdog timer function On-chip power-on reset, V DD monitor, and temperature sensor On-chip voltage comparator 17 Port I/O (5 V tolerant) With on-chip power-on reset, V DD monitor, watchdog timer, and clock oscillator, the C8051F350/1/2/3 devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for 2.7 V-to-3.6 V operation over the industrial temperature range (-45 to +85 C). The Port I/O and /RST pins are tolerant of input signals up to 5 V. The C8051F350/1/2/3 are available in 28-pin MLP or 32-pin LQFP packaging, as shown in Figure 1.1 through Figure 1.4. Rev

14 Table 1.1. Product Selection Guide MIPS (Peak) Flash Memory RAM Calibrated Internal 24.5 MHz Oscillator Clock Multiplier SMBus/I2C SPI UART Timers (16-bit) Programmable Counter Array Digital Port I/Os 24-bit ADC 16-bit ADC Two 8-bit Current Output DACs Internal Voltage Reference Temperature Sensor Analog Comparator Package C8051F kb LQFP-32 C8051F kb MLP-28 C8051F kb LQFP-32 C8051F kb MLP Rev. 0.4

15 VDD Digital Power GND CP0- AV+ AGND /RST/C2CK VREF+ VREF- AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Analog Power XTAL1 XTAL2 C2D External Oscillator Circuit 24.5MHz 2% Internal Oscillator A M U X POR Debug HW Buffer Brown- Out Clock Multiplier + + PGA Temp Sensor Reset System Clock Offset DAC C o r e 8kbyte FLASH 256 byte SRAM SFR Bus 24-bit ADC0 512 byte XRAM VREF Port 0 Latch UART Timer 0, 1, 2, 3 3-Chnl PCA/ WDT SMBus SPI Bus Port 1 Latch Port 2 Latch 8-bit IDAC0 8-bit IDAC1 X B A R P 0 D r v CP0 + CP0A - P 1 D r v C2D CP0+ P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4/CP0A P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 P2.0/C2D Figure 1.1. C8051F350 Block Diagram Rev

16 CP0+ CP0 + CP0- CP0A - VDD GND AV+ AGND /RST/C2CK VREF+ VREF- AIN0 AIN1 AIN2 AIN3 Digital Power Analog Power XTAL1 XTAL2 AIN4 AIN5 AIN6 AIN7 C2D External Oscillator Circuit 24.5MHz 2% Internal Oscillator A M U X POR Debug HW Buffer Brown- Out Clock Multiplier + + PGA Temp Sensor Reset System Clock Offset DAC C o r e 8kbyte FLASH 256 byte SRAM SFR Bus 24-bit ADC0 512 byte XRAM VREF Port 0 Latch UART Timer 0, 1, 2, 3 3-Chnl PCA/ WDT SMBus SPI Bus Port 1 Latch Port 2 Latch 8-bit IDAC0 8-bit IDAC1 X B A R P 0 D r v AIN4-7 P 1 D r v C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0/AIN4 P1.1/AIN5 P1.2/AIN6 P1.3/AIN7 P1.4/CP0A P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 P2.0/C2D Figure 1.2. C8051F351 Block Diagram 16 Rev. 0.4

17 CP0- VDD GND AV+ AGND /RST/C2CK VREF+ VREF- AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Digital Power Analog Power XTAL1 XTAL2 C2D External Oscillator Circuit 24.5MHz 2% Internal Oscillator A M U X POR Debug HW Buffer Brown- Out Clock Multiplier + + PGA Temp Sensor Reset System Clock Offset DAC C o r e 8kbyte FLASH 256 byte SRAM SFR Bus 16-bit ADC0 512 byte XRAM VREF Port 0 Latch UART Timer 0, 1, 2, 3 3-Chnl PCA/ WDT SMBus SPI Bus Port 1 Latch Port 2 Latch 8-bit IDAC0 8-bit IDAC1 X B A R P 0 D r v CP0 + CP0A - P 1 D r v C2D CP0+ P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0 P1.1 P1.2 P1.3 P1.4/CP0A P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 P2.0/C2D Figure 1.3. C8051F352 Block Diagram Rev

18 CP0+ CP0 + CP0- CP0A - VDD GND AV+ AGND /RST/C2CK VREF+ VREF- AIN0 AIN1 AIN2 AIN3 Digital Power Analog Power XTAL1 XTAL2 AIN4 AIN5 AIN6 AIN7 C2D External Oscillator Circuit 24.5MHz 2% Internal Oscillator A M U X POR Debug HW Buffer Brown- Out x2 + + PGA Temp Sensor Reset System Clock Offset DAC C o r e 8kbyte FLASH 256 byte SRAM SFR Bus 16-bit ADC0 512 byte XRAM VREF Port 0 Latch UART Timer 0, 1, 2, 3 3-Chnl PCA/ WDT SMBus SPI Bus Port 1 Latch Port 2 Latch 8-bit IDAC0 8-bit IDAC1 X B A R P 0 D r v AIN4-7 P 1 D r v C2D P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4/TX P0.5/RX P0.6/CNVSTR P0.7 P1.0/AIN4 P1.1/AIN5 P1.2/AIN6 P1.3/AIN7 P1.4/CP0A P1.5/CP0 P1.6/IDAC0 P1.7/IDAC1 P2.0/C2D Figure 1.4. C8051F353 Block Diagram 18 Rev. 0.4

19 1.1. CIP-51 Microcontroller Fully 8051 Compatible Instruction Set The C8051F35x devices use Silicon Labs proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51 instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. The C8051F35x family has a superset of all the peripherals included with a standard Improved Throughput The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12-to-24 MHz. By contrast, the CIP- 51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51's system clock running at 50 MHz, it has a peak throughput of 50 MIPS. The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that require each execution time. Clocks to Execute 1 2 2/3 3 3/4 4 4/5 5 8 Number of Instructions Additional Features The C8051F350/1/2/3 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. An extended interrupt handler allows the numerous analog and digital peripherals to operate independently of the controller core and interrupt the controller only when necessary. By requiring less intervention from the microcontroller core, an interrupt-driven system is more efficient and allows for easier implementation of multi-tasking, real-time systems. Eight reset sources are available: power-on reset circuitry (POR), an on-chip V DD monitor, a Watchdog Timer, a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external reset pin, and an illegal Flash access protection circuit. Each reset source except for the POR, Reset Input Pin, or Flash error may be disabled by the user in software. The WDT may be permanently enabled in software after a power-on reset during MCU initialization. The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also included, allowing an external crystal, ceramic resonator, capacitor, RC, or CMOS clock source to generate the system clock. A clock multiplier allows for operation at up to 50 MHz. An external oscillator can also be extremely useful in low power applications, allowing the MCU to run from a slow (power saving) source, while periodically switching to the fast internal oscillator as needed. Rev

20 1.2. On-Chip Debug Circuitry The C8051F350/1/2/3 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides nonintrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and modification of memory and registers, breakpoints, and single stepping. No additional target RAM, program memory, timers, or communications channels are required. All the digital and analog peripherals are functional and work correctly while debugging. All the peripherals (except for the ADC and SMBus) are stalled when the MCU is halted, during single stepping, or at a breakpoint in order to keep them synchronized. The C8051F350DK development kit provides all the hardware and software necessary to develop application code and perform in-circuit debugging with the C8051F350/1/2/3 MCUs. The kit includes software with a developer's studio and debugger, an integrated 8051 assembler, and an RS-232 to C2 serial adapter. It also has a target application board with the associated MCU installed and prototyping area, plus the RS- 232 and C2 cables, and wall-mount power supply. The Development Kit requires a Windows 95/98/NT/ME/2000 computer with one available RS-232 serial port. As shown in Figure 1.5, the PC is connected via RS-232 to the Serial Adapter. A six-inch ribbon cable connects the Serial Adapter to the user's application board, picking up the two C2 pins, V DD, and GND. The Serial Adapter takes its power from the application board. For applications where there is not sufficient power available from the target board, the provided power supply can be connected directly to the Serial Adapter. The Silicon Labs IDE interface is a vastly superior developing and debugging configuration, compared to standard MCU emulators that use on-board "ICE Chips" and require the MCU in the application board to be socketed. Silicon Labs' debug paradigm increases ease of use and preserves the performance of the precision analog peripherals. WINDOWS 95/98/NT/ME/2000 Silicon Labs Integrated Development Environment RS-232 Serial Adapter C2 (x2), VDD, GND VDD GND TARGET PCB C8051F350 Figure 1.5. Development/In-System Debug Diagram 20 Rev. 0.4

21 1.3. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit addressable. Program memory consists of 8 kb bytes of FLASH. This memory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. 0x1FFF 0x1E00 0x1DFF PROGRAM/DATA MEMORY (FLASH) RESERVED 8K FLASH (In-System Programmable in 512 Byte Sectors) 0xFF 0x80 0x7F 0x30 0x2F 0x20 0x1F 0x00 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE Upper 128 RAM (Indirect Addressing Only) (Direct and Indirect Addressing) Bit Addressable General Purpose Registers Special Function Register's (Direct Addressing Only) Lower 128 RAM (Direct and Indirect Addressing) 0x0000 0xFFFF EXTERNAL DATA ADDRESS SPACE Same 512 bytes as from 0x0000 to 0x01FF, wrapped on 512-byte boundaries 0x0200 0x01FF 0x0000 XRAM Bytes (accessable using MOVX instruction) Figure 1.6. Memory Map Rev

22 or 16-Bit Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) Sigma- Delta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation filters can be programmed for throughputs of up to 1 khz. An internal 2.5 V reference is available, or a differential external reference can be used for ratiometric measurements. A Programmable Gain Amplifier (PGA) is included, with eight gain settings up to 128x. An analog front-end multiplexer connects the differential inputs to eight external pins, the internal temperature sensor, or AGND. The on-chip input buffers can be used to provide a high input impedance for direct connection to sensitive transducers. An 8-bit offset DAC allows for correction of large input offset voltages. AV+ Burnout Current Sources Internal 2.5V or External VREF Eight External Inputs Temperature Sensor AIN+ AIN- Input Buffers Σ Σ PGA 1x to 128x Modulator SINC 3 Filter Fast Filter AGND 8-Bit Offset DAC Figure 1.7. ADC0 Block Diagram 22 Rev. 0.4

23 1.5. Two 8-bit Current-Mode DACs The C8051F350/1/2/3 devices include two 8-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 ma, 0.5 ma, 1 ma, and 2 ma. A flexible output update mechanism allows for seamless full-scale changes, and supports jitter-free updates for waveform generation. IDAC updates can be performed on-demand, scheduled on a Timer overflow, or synchronized with an external signal. Figure 1.8 shows a block diagram of the IDAC circuitry. Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR 8-bit Digital Input 8 8 Current IDA0 Output Latch 8-bit Digital Input 8 8 Current IDA1 Output Latch Data Write Timer 0 Timer 1 Timer 2 Timer 3 CNVSTR Figure 1.8. IDAC Block Diagram Rev

24 1.6. Programmable Comparator C8051F350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer. The Comparator offers programmable response time and hysteresis and two outputs that are optionally available at the Port pins: a synchronous latched output (CP0), or an asynchronous raw output (CP0A). Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may be used as a wake-up source for the processor. Comparator0 may also be configured as a reset source. A block diagram of the Comparator is shown in Figure 1.9. VDD Interrupt Logic Port I/O Pins Multiplexer + SET D Q - Q CLR SET D Q Q CLR CP0 (synchronous output) GND Reset Decision Tree (SYNCHRONIZER) CP0A (asynchronous output) Figure 1.9. Comparator0 Block Diagram 1.7. Serial Ports The C8051F350/1/2/3 Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 24 Rev. 0.4

25 1.8. Port Input/Output C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be configured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain operation. The weak pull-ups that are fixed on typical 8051 devices may be globally disabled to save power. The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip conter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on the port pins using the Crossbar control resgiters. This allows the user to select the exact mix of generalpurpose port I/O, digital, and analog resources needed for the application. XBR0, XBR1, PnSKIP Registers PnMDOUT, PnMDIN Registers Priority Decoder Highest Priority UART 2 (Internal Digital Signals) CP0 Outputs SPI SMBus SYSCLK PCA Digital Crossbar 8 8 P0 I/O Cells P1 I/O Cells P0.0 P0.7 P1.0 P1.7 Lowest Priority T0, T1 2 8 P0 (P0.0-P0.7) (Port Latches) P1 P2 8 (P1.0-P1.7) (P2.0) P2 I/O Cell P2.0 Figure Port I/O Functional Block Diagram Rev

26 1.9. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. The counter/timer is driven by a programmable timebase that can select between six sources: system clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external clock signal on the External Clock nput (ECI) input pin. Each capture/compare module may be configured to operate independently in one of six modes: Edge- Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit PWM. Additionally, PCA Module 2 may be used as a watchdog timer (WDT), and is enabled in this mode following a system reset. The PCA Capture/Compare Module I/O and the External Clock Input may be routed to Port I/O using the digital crossbar. SYSCLK/12 SYSCLK/4 Timer 0 Overflow ECI SYSCLK External Clock/8 PCA CLOCK MUX 16-Bit Counter/Timer Capture/Compare Module 0 Capture/Compare Module 1 Capture/Compare Module 2 / WDT CEX2 CEX1 CEX0 ECI Crossbar Port I/O Figure PCA Block Diagram 26 Rev. 0.4

27 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings * Parameter Conditions Min Typ Max Units Ambient temperature under bias C Storage Temperature C Voltage on any Pin (except V DD, AV+, and Port I/O) with respect to DGND -0.3 V DD V Voltage on any Port I/O Pin or /RST with respect to DGND V Voltage on V DD with respect to DGND V Voltage on AV+ with respect to AGND V Maximum output current sunk by any Port pin 100 ma Maximum output current sunk by any other I/O pin Maximum output current sourced by any Port pin Maximum output current sourced by any other I/O pin Maximum Total current through V DD, AV+, DGND, and AGND 50 ma 100 ma 50 ma 500 ma * Note: stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev

28 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics -40 to +85 C, 25 MHz System Clock unless otherwise specified. Parameter Conditions Min Typ Max Units Analog Supply Voltage (Note 1) V Analog Supply Current Analog Supply Current with analog sub-systems inactive Analog-to-Digital Supply Delta ( V DD - AV+ ) Internal REF, ADC, IDACs, Comparators all active Internal REF, ADC, IDACs, Comparators all disabled, oscillator disabled TBD TBD ma TBD TBD µa 0.5 V Digital Supply Voltage V Digital Supply Current with CPU active Digital Supply Current with CPU inactive (not accessing Flash) Digital Supply Current (shutdown) Digital Supply RAM Data Retention Voltage TBD TBD Oscillator not running TBD µa 1.5 V SYSCLK (System Clock) (Notes 2 and 3) 0 50 MHz Specified Operating Temperature Range C Note 1: Analog Supply AV+ must be greater than 1 V for V DD monitor to operate. Note 2: SYSCLK is the internal device clock. For operational speeds in excess of 25 MHz, SYSCLK must be derived from the internal clock multiplier. Note 3: SYSCLK must be at least 32 khz to enable debugging. 28 Rev. 0.4

29 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F350/1/2/3 Pin Numbers Name F350 F352 F351 F353 Type Description V DD Power Digital Supply Voltage. Must be tied to +2.7 V to +3.6 V power. DGND Ground Digital Ground. Must be tied to Ground. AV Power Analog Supply Voltage. Must be tied to +2.7 V to +3.6 V power. AGND 9 5 Ground Analog Ground. Must be tied to Ground. /RST 12 8 D I/O Device Reset. Open-drain output of internal POR or V DD monitor. An external source can initiate a system reset by driving this pin low for at least 15 µs. A 1kΩ pull-up to V DD is recommended. See Reset Sources Section. C2CK D I/O Clock signal for the C2 Debug Interface. P2.0/ C2D 11 7 D I/O D I/O Port 2.0. See Port I/O Section for a complete description. Bi-directional data signal for the C2 Debug Interface. P P D I/O or A In D I/O or A In Port 0.0. See Port I/O Section for a complete description. Port 0.1. See Port I/O Section for a complete description. P0.2/ XTAL D I/O or A In A In Port 0.2. See Port I/O Section for a complete description. This pin is the external oscillator return for a crystal or resonator. See Oscillator Section. P0.3/ XTAL P P D I/O A I/O or D In D I/O or A In D I/O or A In Port 0.3. See Port I/O Section for a complete description. This pin is the excitation driver for an external crystal or resonator, or an external clock input for CMOS, capacitor, or RC oscillator configurations. See Oscillator Section. Port 0.4. See Port I/O Section for a complete description. Port 0.5. See Port I/O Section for a complete description. Rev

30 Table 4.1. Pin Definitions for the C8051F350/1/2/3 (Continued) Pin Numbers Name F350 F352 F351 F353 Type Description P0.6/ CNVSTR D I/O or A In D In Port 0.6. See Port I/O Section for a complete description. External Convert Start Input for IDACs (See IDAC Section for complete description). P D I/O or A In Port 0.7. See Port I/O Section for a complete description. P1.0/ AIN D I/O or A In A In Port 1.0. See Port I/O Section for a complete description. ADC0 Input Channel 4 (C8051F351/3 - See ADC0 Section for complete description). P1.1/ AIN D I/O or A In A In Port 1.1. See Port I/O Section for a complete description. ADC0 Input Channel 5 (C8051F351/3 - See ADC0 Section for complete description). P1.2/ AIN D I/O or A In A In Port 1.2. See Port I/O Section for a complete description. ADC0 Input Channel 6 (C8051F351/3 - See ADC0 Section for complete description). P1.3/ AIN D I/O or A In A In Port 1.3. See Port I/O Section for a complete description. ADC0 Input Channel 7 (C8051F351/3 - See ADC0 Section for complete description). P P D I/O or A In D I/O or A In Port 1.4. See Port I/O Section for a complete description. Port 1.5. See Port I/O Section for a complete description. P1.6/ D I/O or A In Port 1.6. See Port I/O Section for a complete description. IDA0 A Out IDAC0 Output (See IDAC Section for complete description). P1.7/ D I/O or A In Port 1.7. See Port I/O Section for a complete description. IDA1 A Out IDAC1 Output (See IDAC Section for complete description). 30 Rev. 0.4

31 Table 4.1. Pin Definitions for the C8051F350/1/2/3 (Continued) Pin Numbers Name F350 F352 F351 F353 Type Description AIN A In AIN A In AIN A In AIN A In AIN A In AIN A In AIN A In AIN A In VREF A I/O VREF A I/O ADC0 Input Channel 0 (See ADC0 Section for complete description). ADC0 Input Channel 1 (See ADC0 Section for complete description). ADC0 Input Channel 2(See ADC0 Section for complete description). ADC0 Input Channel 3 (See ADC0 Section for complete description). ADC0 Input Channel 4 (C8051F350/2 - See ADC0 Section for complete description). ADC0 Input Channel 5 (C8051F350/2 - See ADC0 Section for complete description). ADC0 Input Channel 6 (C8051F350/2 - See ADC0 Section for complete description). ADC0 Input Channel 7 (C8051F350/2 - See ADC0 Section for complete description). VREF Positive Voltage Pin (See VREF Section for complete description). VREF Negative Voltage Pin (See VREF Section for complete description). Rev

32 AIN P1.1 AIN P1.0 AIN0.2 AIN0.3 AIN DGND VDD P P P0.5 AIN P C8051F350 C8051F352 Top View AIN0.5 AIN0.6 AGND AV+ P2.0 / C2D /RST / C2CK P0.0 P0.1 P0.2 / XTAL1 P0.3 / XTAL2 VREF- VREF+ P1.7 / IDA1 P1.6 / IDA0 P1.5 P1.4 P1.3 P1.2 Figure 4.1. LQFP-32 Pinout Diagram (Top View) 32 Rev. 0.4

33 AIN AIN AIN0.2 AIN0.3 AGND C8051F351 C8051F353 Top View AV P2.0 / C2D 7 15 /RST / C2CK P0.0 P0.1 P0.2 / XTAL1 P0.3 / XTAL2 P0.4 P VREF- VREF+ P1.7 / IDA1 P1.6 / IDA0 P1.5 P1.4 P1.3 / AIN0.7 GND P1.2 / AIN0.6 P1.1 / AIN0.5 P1.0 / AIN0.4 DGND VDD P0.7 GND P0.6 Figure 4.2. MLP-28 Pinout Diagram (Top View) Rev

34 32 D D1 E1 E Table 4.2. LQFP-32 Package Dimensions MM MIN TYP MAX A A A b D D e E E PIN 1 IDENTIFIER A2 1 A b A1 e Figure 4.3. LQFP-32 Package Diagram 34 Rev. 0.4

35 b e L Bottom View D2 2 DETAIL D2 6 x e D A x e E A 12 E Side View 13 E R Table 4.2. MLP-28 Package Dimensions MM MIN TYP MAX A A A A b D D E E e L N ND NE R AA BB CC DD A3 e A1 DETAIL 1 AA BB CC DD Figure 4.4. MLP-28 Package Drawing Rev

36 Top View 0.50 mm 0.20 mm 0.20 mm 0.30 mm 0.85 mm 0.50 mm 0.50 mm b L e D 0.10 mm 0.20 mm D mm E mm 0.30 mm 0.50 mm 0.35 mm 0.85 mm 0.10 mm E Figure 4.5. Typical MLP-28 Landing Diagram 36 Rev. 0.4

37 Top View 0.50 mm 0.20 mm 0.20 mm 0.30 mm 0.85 mm 0.50 mm 0.50 mm 0.10 mm 0.20 mm 0.60 mm 0.35 mm 0.60 mm 0.70 mm 0.30 mm b 0.20 mm 0.40 mm L e D2 D E mm 0.30 mm 0.50 mm 0.35 mm 0.85 mm 0.10 mm Figure 4.6. Typical MLP-28 Solder Paste Diagram E Rev

38 38 Rev. 0.4

39 5. 24 or 16-Bit Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) Sigma- Delta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation filters can be programmed for throughputs of up to 1 khz. An internal reference is available, or a differential external reference can be used for ratiometric measurements. A Programmable Gain Amplifier (PGA) is included, with eight gain settings up to 128x. The on-chip input buffers can be used to provide a high input impedance for direct connection to sensitive transducers. An 8-bit offset DAC allows for correction of large input offset voltages. ADC0CN ADC0MD ADC0STA AV+ ADC0BUF AD0ISEL AD0VREF Voltage Reference Control and Calibration ADC0COH:M:L ADC0CGH:M:L AD0BCE AIN+ AIN- Σ Σ PGA Modulator SINC 3 Filter Fast Filter ADC0H:M:L ADC0FH:M:L AD0BCE AGND Input Buffers ADC0DAC 8-Bit Offset DAC AD0POL AD0BCE AD0GN2 AD0GN1 AD0GN0 ADC0CN MDCLK SYSCLK ADC0CLK ADC0DECH:L Figure 5.1. ADC0 Block Diagram Rev

40 5.1. Configuration ADC0 is enabled by setting the AD0EN bit in register ADC0MD (Figure 5.7) to 1. When the ADC is disabled, it is placed in a low-power shutdown mode with all clocks turned off, to minimize unnecessary power consumption. The ADC will retain all of its settings in shutdown mode, with the exception of the AD0SM bits, which are reset to 000b (Idle Mode) Voltage Reference Selection The ADC s voltage reference is selected using the AD0VREF bit in register ADC0CN (Figure 5.5). When set to 1, the ADC uses an external voltage reference source. When cleared to 0, the internal reference is used. A more detailed description of the voltage reference options can be found in Section 7. Voltage Reference on page Analog Inputs The ADC s analog inputs are connected to external device pins or internal voltages as described in Section 5.6. Analog Multiplexer on page 57. They can be configured as either single-ended (one independent input measured with respect to AGND) or differential (two independent inputs measured with respect to each other). For accurate measurements, the ADC inputs must remain within the input range specifications found in Table 5.3. To prevent damage to the device, all external ADC inputs must also remain within the Absolute Maximum ratings for the input pin, given in Table Programmable Gain Amplifier A programmable gain amplifier (PGA) provides amplification settings of 1, 2, 4, 8, 16, 32, 64, and 128 for the ADC inputs. The PGA gain setting is controlled by the AD0GN bits in register ADC0CN (Figure 5.5) Input Buffers Independent input buffers are included for AIN+ and AIN-, as shown in Figure 5.2. Each input has a set of two buffers that can be used to minimize the input current of the ADC for sensitive measurements. The low input buffer can be used when the absolute pin input voltage is in the lower half of the supply range. The high input buffer on each pin can be used when the absolute pin input voltage is in the upper half of the supply range. See Table 5.3 for the input buffer range specifications. The input buffers can also be bypassed, for a direct connection to the PGA inputs. The ADC input buffers are controlled with the ADC0BUF register (Figure 5.12). 40 Rev. 0.4