C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
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1 Full Speed USB Flash MCU Family Analog Peripherals - 10-Bit ADC (C8051F340/1/2/3/4/5/6/7/A/B only) Up to 200 ksps Built-in analog multiplexer with single-ended and differential mode VREF from external pin, internal reference, or V DD Built-in temperature sensor External conversion start input option - Two comparators - Internal voltage reference (C8051F340/1/2/3/4/5/6/7/A/B only) - Brown-out detector and POR Circuitry USB Function Controller - USB specification 2.0 compliant - Full speed (12 Mbps) or low speed (1.5 Mbps) operation - Integrated clock recovery; no external crystal required for full speed or low speed - Supports eight flexible endpoints - 1 kb USB buffer memory - Integrated transceiver; no external resistors required On-Chip Debug - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (No emulator required) - Provides breakpoints, single stepping, inspect/modify memory and registers - Superior performance to emulation systems using ICE-chips, target pods, and sockets Voltage Supply Input: 2.7 to 5.25 V - Voltages from 3.6 to 5.25 V supported using On-Chip Voltage Regulator HIgh Speed 8051 µc Core - Pipelined instruction architecture; executes 70% of Instructions in 1 or 2 system clocks - 48 MIPS and 25 MIPS versions available. - Expanded interrupt handler Memory or 2304 Bytes RAM - 64 or 32 kb Flash; In-system programmable in 512-byte sectors Digital Peripherals - 40/25 Port I/O; All 5 V tolerant with high sink current - Hardware enhanced SPI, SMBus, and one or two enhanced UART serial ports - Four general purpose 16-bit counter/timers - 16-bit programmable counter array (PCA) with five capture/compare modules - External Memory Interface (EMIF) Clock Sources - Internal Oscillator: ±0.25% accuracy with clock recovery enabled. Supports all USB and UART modes - External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin modes) - Low Frequency (80 khz) Internal Oscillator - Can switch between clock sources on-the-fly Packages - 48-pin TQFP (C8051F340/1/4/5/8/C) - 32-pin LQFP (C8051F342/3/6/7/9/A/B/D) - 5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B) Temperature Range: 40 to +85 C ANALOG PERIPHERALS PRECISION INTERNAL OSCILLATORS DIGITAL I/O UART0 CROSSBAR Ext. Memory I/F Port 0 UART1* A + 10-bit SPI Port 1 M ksps - U SMBus X ADC - Port 2 PCA 4 Timers Port 3 TEMP VREG VREF SENSOR Port 4 48 Pin Only C8051F340/1/2/34/5/6/7/A/B Only * C8051F340/1/4/5/8/A/B/C Only USB Controller / Transceiver HIGH-SPEED CONTROLLER CORE 64/32 kb 8051 CPU 4/2 kb RAM ISP FLASH (48/25 MIPS) FLEXIBLE DEBUG POR WDT INTERRUPTS CIRCUITRY Rev /09 Copyright 2009 by Silicon Laboratories C8051F34x
2 2 Rev. 1.4
3 Table of Contents 1. System Overview Absolute Maximum Ratings Global DC Electrical Characteristics Pinout and Package Definitions Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only) Analog Multiplexer Temperature Sensor Modes of Operation Starting a Conversion Tracking Modes Settling Time Requirements Programmable Window Detector Window Detector In Single-Ended Mode Window Detector In Differential Mode Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only) Comparators Voltage Regulator (REG0) Regulator Mode Selection VBUS Detection CIP-51 Microcontroller Instruction Set Instruction and CPU Timing MOVX Instruction and Program Memory Memory Organization Program Memory Data Memory General Purpose Registers Bit Addressable Locations Stack Special Function Registers Register Descriptions Interrupt Handler MCU Interrupt Sources and Vectors External Interrupts Interrupt Priorities Interrupt Latency Interrupt Register Descriptions Power Management Modes Idle Mode Stop Mode Prefetch Engine Reset Sources Power-On Reset Rev
4 11.2.Power-Fail Reset / VDD Monitor External Reset Missing Clock Detector Reset Comparator0 Reset PCA Watchdog Timer Reset Flash Error Reset Software Reset USB Reset Flash Memory Programming The Flash Memory Flash Lock and Key Functions Flash Erase Procedure Flash Write Procedure Non-Volatile Data Storage Security Options External Data Memory Interface and On-Chip XRAM Accessing XRAM Bit MOVX Example Bit MOVX Example Accessing USB FIFO Space Configuring the External Memory Interface Port Configuration Multiplexed and Non-multiplexed Selection Multiplexed Configuration Non-multiplexed Configuration Memory Mode Selection Internal XRAM Only Split Mode without Bank Select Split Mode with Bank Select External Only Timing Non-multiplexed Mode Multiplexed Mode Oscillators Programmable Internal High-Frequency (H-F) Oscillator Internal H-F Oscillator Suspend Mode Programmable Internal Low-Frequency (L-F) Oscillator Calibrating the Internal L-F Oscillator External Oscillator Drive Circuit Clocking Timers Directly Through the External Oscillator External Crystal Example External RC Example External Capacitor Example x Clock Multiplier System and USB Clock Selection Rev. 1.3
5 System Clock Selection USB Clock Selection Port Input/Output Priority Crossbar Decoder Port I/O Initialization General Purpose Port I/O Universal Serial Bus Controller (USB0) Endpoint Addressing USB Transceiver USB Register Access USB Clock Configuration FIFO Management FIFO Split Mode FIFO Double Buffering FIFO Access Function Addressing Function Configuration and Control Interrupts The Serial Interface Engine Endpoint Endpoint0 SETUP Transactions Endpoint0 IN Transactions Endpoint0 OUT Transactions Configuring Endpoints Controlling Endpoints1-3 IN Endpoints1-3 IN Interrupt or Bulk Mode Endpoints1-3 IN Isochronous Mode Controlling Endpoints1-3 OUT Endpoints1-3 OUT Interrupt or Bulk Mode Endpoints1-3 OUT Isochronous Mode SMBus Supporting Documents SMBus Configuration SMBus Operation Arbitration Clock Low Extension SCL Low Timeout SCL High (SMBus Free) Timeout Using the SMBus SMBus Configuration Register SMB0CN Control Register Data Register SMBus Transfer Modes Master Transmitter Mode Master Receiver Mode Rev
6 Slave Receiver Mode Slave Transmitter Mode SMBus Status Decoding UART Enhanced Baud Rate Generation Operational Modes Bit UART Bit UART Multiprocessor Communications UART1 (C8051F340/1/4/5/8/A/B/C Only) Baud Rate Generator Data Format Configuration and Operation Data Transmission Data Reception Multiprocessor Communications Enhanced Serial Peripheral Interface (SPI0) Signal Descriptions Master Out, Slave In (MOSI) Master In, Slave Out (MISO) Serial Clock (SCK) Slave Select (NSS) SPI0 Master Mode Operation SPI0 Slave Mode Operation SPI0 Interrupt Sources Serial Clock Timing SPI Special Function Registers Timers Timer 0 and Timer Mode 0: 13-bit Counter/Timer Mode 1: 16-bit Counter/Timer Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) Timer bit Timer with Auto-Reload bit Timers with Auto-Reload Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge Timer bit Timer with Auto-Reload bit Timers with Auto-Reload USB Start-of-Frame Capture Programmable Counter Array (PCA0) PCA Counter/Timer Capture/Compare Modules Edge-triggered Capture Mode Rev. 1.3
7 Software Timer (Compare) Mode High Speed Output Mode Frequency Output Mode Bit Pulse Width Modulator Mode Bit Pulse Width Modulator Mode Watchdog Timer Mode Watchdog Timer Operation Watchdog Timer Usage Register Descriptions for PCA C2 Interface C2 Interface Registers C2 Pin Sharing Document Change List Contact Information Rev
8 List of Figures 1. System Overview Figure 1.1. C8051F340/1/4/5 Block Diagram Figure 1.2. C8051F342/3/6/7 Block Diagram Figure 1.3. C8051F348/C Block Diagram Figure 1.4. C8051F349/D Block Diagram Figure 1.5. C8051F34A/B Block Diagram Pinout and Package Definitions Figure 4.1. TQFP-48 Pinout Diagram (Top View) Figure 4.2. TQFP-48 Package Diagram Figure 4.3. TQFP-48 Recommended PCB Land Pattern Figure 4.4. LQFP-32 Pinout Diagram (Top View) Figure 4.5. LQFP-32 Package Diagram Figure 4.6. LQFP-32 Recommended PCB Land Pattern Figure 4.7. QFN-32 Pinout Diagram (Top View) Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only) Figure 5.1. ADC0 Functional Block Diagram Figure 5.2. Temperature Sensor Transfer Function Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2.40 V) Figure Bit ADC Track and Conversion Example Timing Figure 5.5. ADC0 Equivalent Input Circuits Figure 5.6. ADC Window Compare Example: Right-Justified Single-Ended Data Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only) Figure 6.1. Voltage Reference Functional Block Diagram Comparators Figure 7.1. Comparator Functional Block Diagram Figure 7.2. Comparator Hysteresis Plot Voltage Regulator (REG0) Figure 8.1. REG0 Configuration: USB Bus-Powered Figure 8.2. REG0 Configuration: USB Self-Powered Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled Figure 8.4. REG0 Configuration: No USB Connection CIP-51 Microcontroller Figure 9.1. CIP-51 Block Diagram Figure 9.2. On-Chip Memory Map for 64 kb Devices Figure 9.3. On-Chip Memory Map for 32 kb Devices Reset Sources Figure Reset Sources Figure Power-On and VDD Monitor Reset Timing Rev. 1.3
9 12. Flash Memory Figure Flash Program Memory Map and Security Byte External Data Memory Interface and On-Chip XRAM Figure USB FIFO Space and XRAM Memory Map with USBFAE set to Figure Multiplexed Configuration Example Figure Non-multiplexed Configuration Example Figure EMIF Operating Modes Figure Non-multiplexed 16-bit MOVX Timing Figure Non-multiplexed 8-bit MOVX without Bank Select Timing Figure Non-multiplexed 8-bit MOVX with Bank Select Timing Figure Multiplexed 16-bit MOVX Timing Figure Multiplexed 8-bit MOVX without Bank Select Timing Figure Multiplexed 8-bit MOVX with Bank Select Timing Oscillators Figure Oscillator Diagram Port Input/Output Figure Port I/O Functional Block Diagram (Port 0 through Port 3) Figure Port I/O Cell Block Diagram Figure Peripheral Availability on Port I/O Pins Figure Crossbar Priority Decoder in Example Configuration (No Pins Skipped) Figure Crossbar Priority Decoder in Example Configuration (3 Pins Skipped) Universal Serial Bus Controller (USB0) Figure USB0 Block Diagram Figure USB0 Register Access Scheme Figure USB FIFO Allocation SMBus Figure SMBus Block Diagram Figure Typical SMBus Configuration Figure SMBus Transaction Figure Typical SMBus SCL Generation Figure Typical Master Transmitter Sequence Figure Typical Master Receiver Sequence Figure Typical Slave Receiver Sequence Figure Typical Slave Transmitter Sequence UART0 Figure UART0 Block Diagram Figure UART0 Baud Rate Logic Figure UART Interconnect Diagram Figure Bit UART Timing Diagram Figure Bit UART Timing Diagram Figure UART Multi-Processor Mode Interconnect Diagram UART1 (C8051F340/1/4/5/8/A/B/C Only) Rev
10 Figure UART1 Block Diagram Figure UART1 Timing Without Parity or Extra Bit Figure UART1 Timing With Parity Figure UART1 Timing With Extra Bit Figure Typical UART Interconnect Diagram Figure UART Multi-Processor Mode Interconnect Diagram Enhanced Serial Peripheral Interface (SPI0) Figure SPI Block Diagram Figure Multiple-Master Mode Connection Diagram Figure Wire Single Master and Slave Mode Connection Diagram Figure Wire Single Master Mode and Slave Mode Connection Diagram Figure Master Mode Data/Clock Timing Figure Slave Mode Data/Clock Timing (CKPHA = 0) Figure Slave Mode Data/Clock Timing (CKPHA = 1) Figure SPI Master Timing (CKPHA = 0) Figure SPI Master Timing (CKPHA = 1) Figure SPI Slave Timing (CKPHA = 0) Figure SPI Slave Timing (CKPHA = 1) Timers Figure T0 Mode 0 Block Diagram Figure T0 Mode 2 Block Diagram Figure T0 Mode 3 Block Diagram Figure Timer 2 16-Bit Mode Block Diagram Figure Timer 2 8-Bit Mode Block Diagram Figure Timer 2 Capture Mode (T2SPLIT = 0 ) Figure Timer 2 Capture Mode (T2SPLIT = 1 ) Figure Timer 3 16-Bit Mode Block Diagram Figure Timer 3 8-Bit Mode Block Diagram Figure Timer 3 Capture Mode (T3SPLIT = 0 ) Figure Timer 3 Capture Mode (T3SPLIT = 1 ) Programmable Counter Array (PCA0) Figure PCA Block Diagram Figure PCA Counter/Timer Block Diagram Figure PCA Interrupt Block Diagram Figure PCA Capture Mode Diagram Figure PCA Software Timer Mode Diagram Figure PCA High Speed Output Mode Diagram Figure PCA Frequency Output Mode Figure PCA 8-Bit PWM Mode Diagram Figure PCA 16-Bit PWM Mode Figure PCA Module 4 with Watchdog Timer Enabled C2 Interface Figure Typical C2 Pin Sharing Rev. 1.3
11 List of Tables 1. System Overview Table 1.1. Product Selection Guide Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings* Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics Table 3.2. Index to Electrical Characteristics Tables Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D Table 4.2. TQFP-48 Package Dimensions Table 4.3. TQFP-48 PCB Land Pattern Dimensions Table 4.4. LQFP-32 Package Dimensions Table 4.5. LQFP-32 PCB Land Pattern Dimensions Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7/A/B Only) Table 5.1. ADC0 Electrical Characteristics Voltage Reference (C8051F340/1/2/3/4/5/6/7/A/B Only) Table 6.1. Voltage Reference Electrical Characteristics Comparators Table 7.1. Comparator Electrical Characteristics Voltage Regulator (REG0) Table 8.1. Voltage Regulator Electrical Specifications CIP-51 Microcontroller Table 9.1. CIP-51 Instruction Set Summary Table 9.2. Special Function Register (SFR) Memory Map Table 9.3. Special Function Registers Table 9.4. Interrupt Summary Reset Sources Table Reset Electrical Characteristics Flash Memory Table Flash Electrical Characteristics External Data Memory Interface and On-Chip XRAM Table AC Parameters for External Memory Interface Oscillators Table Oscillator Electrical Characteristics Port Input/Output Table Port I/O DC Electrical Characteristics Universal Serial Bus Controller (USB0) Table Endpoint Addressing Scheme Table USB0 Controller Registers Table FIFO Configurations Table USB Transceiver Electrical Characteristics SMBus Table SMBus Clock Source Selection Rev
12 Table Minimum SDA Setup and Hold Times Table Sources for Hardware Changes to SMB0CN Table SMBus Status Decoding UART0 Table Timer Settings for Standard Baud Rates Using the Internal Oscillator UART1 (C8051F340/1/4/5/8/A/B/C Only) Table Baud Rate Generator Settings for Standard Baud Rates Enhanced Serial Peripheral Interface (SPI0) Table SPI Slave Timing Parameters Programmable Counter Array (PCA0) Table PCA Timebase Input Options Table PCA0CPM Register Settings for PCA Capture/Compare Modules Table Watchdog Timer Timeout Intervals Rev. 1.3
13 List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select SFR Definition 5.3. ADC0CF: ADC0 Configuration SFR Definition 5.4. ADC0H: ADC0 Data Word MSB SFR Definition 5.5. ADC0L: ADC0 Data Word LSB SFR Definition 5.6. ADC0CN: ADC0 Control SFR Definition 5.7. ADC0GTH: ADC0 Greater-Than Data High Byte SFR Definition 5.8. ADC0GTL: ADC0 Greater-Than Data Low Byte SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte SFR Definition ADC0LTL: ADC0 Less-Than Data Low Byte SFR Definition 6.1. REF0CN: Reference Control SFR Definition 7.1. CPT0CN: Comparator0 Control SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection SFR Definition 7.4. CPT1CN: Comparator1 Control SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection SFR Definition 8.1. REG0CN: Voltage Regulator Control SFR Definition 9.1. DPL: Data Pointer Low Byte SFR Definition 9.2. DPH: Data Pointer High Byte SFR Definition 9.3. SP: Stack Pointer SFR Definition 9.4. PSW: Program Status Word SFR Definition 9.5. ACC: Accumulator SFR Definition 9.6. B: B Register SFR Definition 9.7. IE: Interrupt Enable SFR Definition 9.8. IP: Interrupt Priority SFR Definition 9.9. EIE1: Extended Interrupt Enable SFR Definition EIP1: Extended Interrupt Priority SFR Definition EIE2: Extended Interrupt Enable SFR Definition EIP2: Extended Interrupt Priority SFR Definition IT01CF: INT0/INT1 Configuration SFR Definition PCON: Power Control SFR Definition PFE0CN: Prefetch Engine Control SFR Definition VDM0CN: V DD Monitor Control SFR Definition RSTSRC: Reset Source SFR Definition PSCTL: Program Store R/W Control SFR Definition FLKEY: Flash Lock and Key SFR Definition FLSCL: Flash Scale SFR Definition EMI0CN: External Memory Interface Control SFR Definition EMI0CF: External Memory Configuration SFR Definition EMI0TC: External Memory Timing Control SFR Definition OSCICN: Internal H-F Oscillator Control SFR Definition OSCICL: Internal H-F Oscillator Calibration Rev
14 SFR Definition OSCLCN: Internal L-F Oscillator Control SFR Definition OSCXCN: External Oscillator Control SFR Definition CLKMUL: Clock Multiplier Control SFR Definition CLKSEL: Clock Select SFR Definition XBR0: Port I/O Crossbar Register SFR Definition XBR1: Port I/O Crossbar Register SFR Definition XBR2: Port I/O Crossbar Register SFR Definition P0: Port0 Latch SFR Definition P0MDIN: Port0 Input Mode SFR Definition P0MDOUT: Port0 Output Mode SFR Definition P0SKIP: Port0 Skip SFR Definition P1: Port1 Latch SFR Definition P1MDIN: Port1 Input Mode SFR Definition P1MDOUT: Port1 Output Mode SFR Definition P1SKIP: Port1 Skip SFR Definition P2: Port2 Latch SFR Definition P2MDIN: Port2 Input Mode SFR Definition P2MDOUT: Port2 Output Mode SFR Definition P2SKIP: Port2 Skip SFR Definition P3: Port3 Latch SFR Definition P3MDIN: Port3 Input Mode SFR Definition P3MDOUT: Port3 Output Mode SFR Definition P3SKIP: Port3 Skip SFR Definition P4: Port4 Latch SFR Definition P4MDIN: Port4 Input Mode SFR Definition P4MDOUT: Port4 Output Mode SFR Definition USB0XCN: USB0 Transceiver Control SFR Definition USB0ADR: USB0 Indirect Address SFR Definition USB0DAT: USB0 Data USB Register Definition INDEX: USB0 Endpoint Index USB Register Definition CLKREC: Clock Recovery Control USB Register Definition FIFOn: USB0 Endpoint FIFO Access USB Register Definition FADDR: USB0 Function Address USB Register Definition POWER: USB0 Power USB Register Definition FRAMEL: USB0 Frame Number Low USB Register Definition FRAMEH: USB0 Frame Number High USB Register Definition IN1INT: USB0 IN Endpoint Interrupt USB Register Definition OUT1INT: USB0 Out Endpoint Interrupt USB Register Definition CMINT: USB0 Common Interrupt USB Register Definition IN1IE: USB0 IN Endpoint Interrupt Enable USB Register Definition OUT1IE: USB0 Out Endpoint Interrupt Enable USB Register Definition CMIE: USB0 Common Interrupt Enable USB Register Definition E0CSR: USB0 Endpoint0 Control USB Register Definition E0CNT: USB0 Endpoint 0 Data Count Rev. 1.3
15 USB Register Definition EINCSRL: USB0 IN Endpoint Control Low Byte USB Register Definition EINCSRH: USB0 IN Endpoint Control High Byte USB Register Definition EOUTCSRL: USB0 OUT Endpoint Control Low Byte USB Register Definition EOUTCSRH: USB0 OUT Endpoint Control High Byte USB Register Definition EOUTCNTL: USB0 OUT Endpoint Count Low USB Register Definition EOUTCNTH: USB0 OUT Endpoint Count High SFR Definition SMB0CF: SMBus Clock/Configuration SFR Definition SMB0CN: SMBus Control SFR Definition SMB0DAT: SMBus Data SFR Definition SCON0: Serial Port 0 Control SFR Definition SBUF0: Serial (UART0) Port Data Buffer SFR Definition SCON1: UART1 Control SFR Definition SMOD1: UART1 Mode SFR Definition SBUF1: UART1 Data Buffer SFR Definition SBCON1: UART1 Baud Rate Generator Control SFR Definition SBRLH1: UART1 Baud Rate Generator High Byte SFR Definition SBRLL1: UART1 Baud Rate Generator Low Byte SFR Definition SPI0CFG: SPI0 Configuration SFR Definition SPI0CN: SPI0 Control SFR Definition SPI0CKR: SPI0 Clock Rate SFR Definition SPI0DAT: SPI0 Data SFR Definition TCON: Timer Control SFR Definition TMOD: Timer Mode SFR Definition CKCON: Clock Control SFR Definition TL0: Timer 0 Low Byte SFR Definition TL1: Timer 1 Low Byte SFR Definition TH0: Timer 0 High Byte SFR Definition TH1: Timer 1 High Byte SFR Definition TMR2CN: Timer 2 Control SFR Definition TMR2RLL: Timer 2 Reload Register Low Byte SFR Definition TMR2RLH: Timer 2 Reload Register High Byte SFR Definition TMR2L: Timer 2 Low Byte SFR Definition TMR2H Timer 2 High Byte SFR Definition TMR3CN: Timer 3 Control SFR Definition TMR3RLL: Timer 3 Reload Register Low Byte SFR Definition TMR3RLH: Timer 3 Reload Register High Byte SFR Definition TMR3L: Timer 3 Low Byte SFR Definition TMR3H Timer 3 High Byte SFR Definition PCA0CN: PCA Control SFR Definition PCA0MD: PCA Mode SFR Definition PCA0CPMn: PCA Capture/Compare Mode SFR Definition PCA0L: PCA Counter/Timer Low Byte SFR Definition PCA0H: PCA Counter/Timer High Byte Rev
16 SFR Definition PCA0CPLn: PCA Capture Module Low Byte SFR Definition PCA0CPHn: PCA Capture Module High Byte C2 Register Definition C2ADD: C2 Address C2 Register Definition DEVICEID: C2 Device ID C2 Register Definition REVID: C2 Revision ID C2 Register Definition FPCTL: C2 Flash Programming Control C2 Register Definition FPDAT: C2 Flash Programming Data Rev. 1.3
17 1. System Overview C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS) In-system, full-speed, non-intrusive debug interface (on-chip) Universal Serial Bus (USB) Function Controller with eight flexible endpoint pipes, integrated transceiver, and 1 kb FIFO RAM Supply Voltage Regulator True 10-bit 200 ksps differential / single-ended ADC with analog multiplexer On-chip Voltage Reference and Temperature Sensor On-chip Voltage Comparators (2) Precision internal calibrated 12 MHz internal oscillator and 4x clock multiplier Internal low-frequency oscillator for additional power savings Up to 64 kb of on-chip Flash memory Up to 4352 Bytes of on-chip RAM ( kb) External Memory Interface (EMIF) available on 48-pin versions. SMBus/I2C, up to 2 UARTs, and Enhanced SPI serial interfaces implemented in hardware Four general-purpose 16-bit timers Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer function On-chip Power-On Reset, V DD Monitor, and Missing Clock Detector Up to 40 Port I/O (5 V tolerant) With on-chip Power-On Reset, V DD monitor, Voltage Regulator, Watchdog Timer, and clock oscillator, C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed in-circuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging without occupying package pins. Each device is specified for V operation over the industrial temperature range ( 40 to +85 C). For voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3.0 V is required for USB communication. The Port I/O and RST pins are tolerant of input signals up to 5 V. C8051F340/1/2/3/ 4/5/6/7/8/9/A/B/C/D devices are available in 48-pin TQFP, 32-pin LQFP, or 32-pin QFN packages. See Table 1.1, Product Selection Guide, on page 18 for feature and package choices. Rev
18 Table 1.1. Product Selection Guide Ordering Part Number MIPS (Peak) Flash Memory (Bytes) RAM Calibrated Internal Oscillator Low Frequency Oscillator USB with 1k Endpoint RAM Supply Voltage Regulator SMBus/I2C Enhanced SPI UARTs Timers (16-bit) Programmable Counter Array Digital Port I/Os External Memory Interface (EMIF) 10-bit 200 ksps ADC Temperature Sensor Voltage Reference Analog Comparators Package C8051F340-GQ 48 64k TQFP48 C8051F341-GQ 48 32k TQFP48 C8051F342-GQ 48 64k LQFP32 C8051F342-GM 48 64k QFN32 C8051F343-GQ 48 32k LQFP32 C8051F343-GM 48 32k QFN32 C8051F344-GQ 25 64k TQFP48 C8051F345-GQ 25 32k TQFP48 C8051F346-GQ 25 64k LQFP32 C8051F346-GM 25 64k QFN32 C8051F347-GQ 25 32k LQFP32 C8051F347-GM 25 32k QFN32 C8051F348-GQ 25 32k TQFP48 C8051F349-GQ 25 32k LQFP32 C8051F349-GM 25 32k QFN32 C8051F34A-GQ 48 64k LQFP32 C8051F34A-GM 48 64k QFN32 C8051F34B-GQ 48 32k LQFP32 C8051F34B-GM 48 32k QFN32 C8051F34C-GQ 48 64k TQFP48 C8051F34D-GQ 48 64k LQFP32 18 Rev. 1.3
19 C2D C2CK/RST VDD VREG GND D+ D- VBUS Power-On Reset Supply Monitor Reset Power Net Voltage Regulator XTAL1 XTAL2 Debug / Programming Hardware CIP Controller Core 64/32k Byte ISP FLASH Program Memory System Clock Setup External Oscillator Internal Oscillator Clock Recovery 256 Byte RAM 4/2k Byte XRAM Clock Multiplier Low Freq. Oscillator USB Peripheral Full / Low Speed Transceiver Controller 1k Byte RAM SFR Bus VDD Port I/O Configuration Digital Peripherals UART0 UART1 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Analog Peripherals VREF 10-bit 200ksps ADC Crossbar Control CP1 + VREF - 2 Comparators A M U X Priority Crossbar Decoder External Memory Interface Control Address Data CP0 + - VDD Temp Sensor P1 P2 / P3 P4 Port 0 Drivers Port 1 Drivers Port 2 Drivers Port 3 Drivers Port 4 Drivers AIN0 - AIN19 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6/XTAL1 P0.7/XTAL2 P1.0 P1.1 P1.2 P1.3 P1.4/CNVSTR P1.5/VREF P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 Figure 1.1. C8051F340/1/4/5 Block Diagram Rev
20 C2CK/RST VDD VREG GND C2D Power-On Reset Supply Monitor Reset Power Net Voltage Regulator XTAL1 XTAL2 Debug / Programming Hardware CIP Controller Core 64/32 kb ISP FLASH Program Memory System Clock Setup External Oscillator Internal Oscillator 256 Byte RAM 4/2 kb XRAM Clock Multiplier SFR Bus Port I/O Configuration Digital Peripherals UART0 Timers 0, 1, 2, 3 PCA/WDT SMBus SPI Crossbar Control Priority Crossbar Decoder Port 0 Drivers Port 1 Drivers Port 2 Drivers Port 3 Drivers P0.0 P0.1 P0.2/XTAL1 P0.3/XTAL2 P0.4 P0.5 P0.6/CNVSTR P0.7/VREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D D+ D- VBUS Clock Recovery Low Freq. Oscillator* USB Peripheral Full / Low Speed Transceiver Controller 1 kb RAM VDD Analog Peripherals VREF 10-bit 200 ksps ADC CP1 + VREF - 2 Comparators A M U X CP0 + - VDD Temp Sensor AIN0 - AIN20 *Low Frequency Oscillator option not available on C8051F346/7 Figure 1.2. C8051F342/3/6/7 Block Diagram 20 Rev. 1.3
UART SPI SMBus PCA Timer 0 Timer 1 Timer 2 Timer 3 - + HIGH-SPEED CONTROLLER CORE 16KB ISP FLASH 2304 B SRAM 16 8051 CPU (25MIPS) DEBUG
Full Speed USB, 16k ISP FLASH MCU Family ANALOG PERIPHERALS - 10-Bit ADC Up to 200 ksps Up to 17 or 13 External Single-Ended or Differential Inputs VREF from External Pin, Internal Reference, or VDD Built-in
C8051F350/1/2/3. Notes. 2 Rev. 0.4
8 k ISP Flash MCU Family Analog Peripherals - 24 or 16-Bit ADC No missing codes 0.0015% nonlinearity Programmable conversion rates up to 1 ksps 8-Input multiplexer 1x to 128x PGA Built-in temperature sensor
UART SMBus SPI PCA Timer 0 Timer 1 Timer 2 Timer 3. 10-bit Current DAC VOLTAGE COMPARATOR
Mixed-Signal Byte-Programmable EPROM MCU Analog Peripherals - 10-Bit ADC ( F336/8 only) Up to 200 ksps Up to 20 external single-ended or differential inputs VREF from on-chip VREF, external pin or V DD
10-bit Current DAC VOLTAGE COMPARATOR HIGH-SPEED CONTROLLER CORE
Mixed-Signal Byte-Programmable EPROM MCU Analog Peripherals - 10-Bit ADC ( T630/2/4 only) Up to 500 ksps Up to 16 external inputs VREF from on-chip VREF, external pin, Internal Regulator or V DD Internal
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