On how to efficiently exploit reconfiguration aspects from your design! The FASTER tool chain!

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Millicent Clarke
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1 On how to efficiently exploit reconfiguration aspects from your design! The FASTER tool chain! Parallel and Pervasive Computing Week 2014! August 29, 2014, Milano, Italy! Dirk Stroobandt, Marco D. Santambrogio, Riccardo Cattaneo, Marco Rabozzi,

2 The FASTER Project! Library)w/)SW/ HW)modules XML)descrip6on %)App %)PlaRorm %)HW/SW)par66oning Parallelism) List)of)HDL)func6ons annota6ons) + + (openmp) C)descrip6on High%level)analysis.) Contains)rough/fast) es6ma6on)of) a)power,) b)resources,) c)computa6on)6me Iden6fica6on)of) PR)cores)+) Applica6on) profiling WP2 (front-end) Op6miza6on)for) micro% reconfigura6on) (TLUT,)TCON) (iden6fy)annota6ons) needed)on)c/hdl) Baseline) scheduling)+) Floorplanning WP3 (back-end) Sta6c Region%based Micro%reconfig. Vendor-flow Vendor-flow + relocation UGent + Vendor-flow System GPP Static Area Reconfigurable Area RR1 RR2 Reuse Reference) design Verification SW Param.) change RTSM Full)bitstream) + Set)of)par6al)reconfigura6on) bitstreams SW) tools WP4 (runtime) 2

3 FASTER front-end: goals! Analyze each application and:! Define its components! HW/SW, reconfigurable HW modules,! Estimate, identify, and optimize its performance and constraints on the target reconfigurable computing system! Execution time, floorplanning and placement, HW/SW execution,! How to do it? Identifying:! The partitioning of the input specification in HW/SW components! The implementation(s) of the modules to be realized as HW accelerators! The corresponding level of reconfigurability for HW components! none, micro, region based! The power constraints! The floorplanning constraints! size and shape! The placement requirements! The baseline schedule for application s execution! 3

4 P2C 2014 FASTER front-end: proposed flow! WP2 Everything done by hand Description of the Architecture C2VHDL or VHDL by hand WP2 TG generator XML Designer GUI Pre-Processing T2.1 T2.2 XML Designer GUI High-level analysis App task profiling and identification of rec. cores T2.3 Optimization of app for microrec. core implementation T2.4 Compile-time baseline scheduling and core mapping onto rec. regions T2.2 T2.1 XML Designer GUI Description of the Architecture T2.4 Pre-Processing TG generator XML Designer GUI Compile-time Everything done baseline by hand scheduling and core mapping onto rec. regions CODESIGN CODESIGN High-level analysis App task profiling and identification of rec. cores C2VHDL or T2.3 VHDL by hand Optimization of app for micro-rec.app coredesigners implementation WP4 WP3 T4.1: Evaluate existing T3.2: Floorplanning, T2.4 run-time system support placement and Compile-time baseline for reconfiguration routing scheduling and core mapping onto rec. regions WP4 WP3 T4.1: Evaluate existing run-time system support for reconfiguration T3.2: Floorplanning, placement and routing Pre-Processing WP4 T4.1: Evaluate existing WP3 T3.2: Floorplanning, 4

5 High-level analysis! Identify reconfiguration opportunities! Analyze run-time benefits for stencil computation! Evaluate run-time solutions! High-level analysis Apps profiling and identification of rec. cores Optimization for region- and microreconfiguration Compile-time scheduling and mapping onto reconfigurable regions 5

6 Application task profiling and identification of reconfigurable cores! Analysis of the application to improve the performance by exploiting the cores and the reconfiguration capabilities of the architecture! Task graph restructuring to improve the performance! Generation of the necessary data for the target specifications! Management of multiple implementation per tasks! HW/SW mapping of the resulting tasks on the different components and reconfigurable areas! High-level analysis Apps profiling and identification of rec. cores Optimization for region- and microreconfiguration Compile-time scheduling and mapping onto reconfigurable regions 6

7 Optimization of applications for microreconfigurable core implementation! Optimize the applications for micro-reconfiguration implementation! Study and increase the parameter value 'locality' in time! Research how current applications can be altered to benefit more from micro-reconfiguration! Investigate multi-mode applications! High-level analysis Apps profiling and identification of rec. cores Optimization for region- and microreconfiguration Compile-time scheduling and mapping onto reconfigurable regions 7

8 Compile-time baseline scheduling and core mapping onto reconfigurable regions! Identify the floorplanning constraints (e.g., size and shape) and the corresponding placement requirements! Implement a heuristic reconfiguration-aware scheduler, used as a baseline schedule for application s execution! High-level analysis Apps profiling and identification of rec. cores Optimization for region- and microreconfiguration Compile-time scheduling and mapping onto reconfigurable regions 8

9 Tutorial agenda! Optimization of applications for micro-reconfigurable core implementation! Dirk Stroobandt, Univeristy of Ghent [2pm 3pm]! Application task profiling and identification of reconfigurable cores! Riccardo Cattaneo, Politecnico di Milano [3pm 3.30pm]! Coffee Break 3.30pm 4.00pm! Application task profiling and identification of reconfigurable cores! hands-on experience on theprivate FASTER VM! Riccardo Cattaneo, Politecnico di Milano [4pm 5pm]! Compile-time baseline scheduling and core mapping onto reconfigurable regions! hands-on experience on the online public available FASTER VM! Marco Rabozzi, Politecnico di Milano [4pm - 5pm]! 9

10 Questions! EU Project! Public available tool! 10

Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and

Eli Levi Eli Levi holds B.Sc.EE from the Technion.Working as field application engineer for Systematics, Specializing in HDL design with MATLAB and Simulink targeting ASIC/FGPA. Previously Worked as logic