INTRODUCTION TO MENTOR GRAPHICS DESIGN TOOLS

Transcription

1 INTRODUCTION TO MENTOR GRAPHICS DESIGN TOOLS Mahmut Yilmaz, Erdem S. Erdogan and Matthew B. Roberts Update: Matthew Roberts 08/06/ RUNNING MENTOR GRAPHICS Note: These commands can be run remotely via ssh to one of the DSIL (dsil1.ee.duke.edudsil14.ee.duke.edu) machines. Log into a DSIL workstation using your ECE id and password. Start up a terminal/xterm window. (Right click on desktop -> Open Terminal) At the command prompt, type "cd ~/" and hit Enter to go to your home directory.

2 2. USING ICSTUDIO Open a terminal (Right click on desktop -> Open Terminal) Type: /opt/digital/initial_setup_ece261 Type: source ~/.cshrc Create a folder named EE261CLASS (or anything you want) in your user directory: Type: mkdir directory_name Type icstudio and hit Enter You will see the icstudio window. (Figure-1) Figure 1

3 Go to File->New->Project New project wizard will pop-up. (Figure-2) Click "Next". Figure 2 As project name, enter EE261CLASS (or anything you want) As project location, select the folder you have just created (EE261CLASS) Note: Folder name is not important. Click "Next". (Figure-3) Figure 3

4 You need to set the location map in this step. Click on "Open Library List Editor". (Figure-4) Figure 4 Click on "Import" button. (Figure-5) Go to /ece/digital/share/mgc_hep/technology/ic/ee261_fall_06 Copy the path above, paste it into the browsing window and press Enter to ensure accuracy Select the file named mgc_location_map. Click on "Open". Then, click on "OK". Figure 5

5 Figure 7 Click on "Next". (Figure-8) Figure 8

6 In this step, process rule files will be selected. Click on "Open Settings Editor". (Figure-9) Figure 9 For the fields shown in figure-10, enter/select the following values: Process File: /ece/digital/share/mgc_hep/technology/ic/ee261_fall_06/process/ami_c5 DRC Rules File: /ece/digital/share/mgc_hep/technology/ic/ee261_fall_06/drc/calanadrcc5.rul LVS Rules File: /ece/digital/share/mgc_hep/technology/ic/ee261_fall_06/lvs/calibreext.rul SDL Rules File: /ece/digital/share/mgc_hep/technology/ic/ee261_fall_06/process/sdl_process_rules Figure 10

7 Then, click on OK. (Figure-11) Figure 11

8 Click on "Next" and then "Finish". (You can see the project configuration before clicking the finish button) (Figure-12) Figure 12 NOTE: If you need to change some settings of the project: Go to Tools -> Preferences -> Click on Project tab Go to Tools -> Location Map Editor NOTE: ICStudio opens the last project at start-up. If you want to change this option, Go to Tools -> Preferences -> Click on General tab Change the option for "When starting, open most recently opened project" NOTE: You don't need create a new project for each homework or project. You can work in a single project environment, by adding different libraries. (File->New->Library)

9 3. DESIGN EXAMPLE: NAND3 1- In ICStudio, go to File New Library. Enter "test_library" as the library name. (Figure-13) ICStudio will create a folder for your library under the project folder. Figure Select the newly created test_library folder from Library window. (Figure-14) Then, go to File Import Verilog Figure 14

10 3- Select "Verilog/Symbol" option for "Views to be created". (Figure-15) Figure 15 Fill in the following: View Name: nand3 Verilog Netlist: /ece/digital/share/mgc_hep/technology/ic/mahmutkit/verilog/nand3.v Language: Verilog Click on "Import". (Figure-16) Figure 16 NOTE: The folder /ece/digital/share/mgc_hep/technology/ic/mahmutkit/verilog includes verilog codes for some basic cells.

11 4- In the "create symbol options" window, select AND as shape type. Click "Create Symbol". (Figure-17) Figure Double click on "Symbol" in the "View" pane. (Figure-18) Figure 18

12 6- The generated symbol is AND-3. We need to convert it to NAND-3. (Figure-19) Figure 19 Go to the Menu Bar and select Setup Select Filter click Set All, then click OK. Go also to Setup Grid Display and select Major and Minor Grid points, then click OK. Use the button with a circle (on the left side of the window) to create a small circle. Move the PIN at the output of the gate to right, and place the circle to the left of the PIN. Right click on the green line and select stretch to connect the circle and pin. (Figure-20) Figure 20 Delete vl_logic texts (Select and press Del) Click on Check&Save button (below the menu bar). NOTE: You need to use the undo button on the left side of the screen to undo actions rather than ctrl+z. You can use F2 key to deselect a selected object.

13 Close DA-IC window and return to ICStudio. You will see in the "View" pane that the verilog code is now shown in red color for nand3 (Figure-22). Since we have changed the symbol, we need to compile the verilog code again to check for consistency. Right click the verilog code and select Check HDL. Figure Creating schematic of NAND3: Right click nand3 in the Cell pane, and select "New View". Select "Schematic" as view type and click "Finish". (Figure-23) Figure 23

14 A DA-IC window will be opened. Click on the "Library" button (on the right side of the window).(if you do not have the buttons on the right, click on the button on the left above the green arrow)(figure-24) Click on "MOS" button. (Figure-25) Figure 24 Figure 25

15 Click on NMOS, and enter the following values: W=9, L=1, M=1 (Figure-26) Figure 26 Notes for DA_IC: 1. When you first start DA_IC, press the maximize button in the top right corner to make sure you can see the whole window. 2. Use the esc key to exit wiring mode or any other mode and go back to the default cursor. 3. Use the c key to copy any selected object. 4. To zoom in, hold down the middle-mouse button and draw a diagonal red line to indicate the area you want to zoom into. To zoom out, press the magnifying glass in the tool-bar with a minus sign

16 Place 3 NMOS transistors in this way. (Figure-27) Figure 27

17 Once you have placed 3 NMOS transistors, select PMOS, and enter the following values: W=6, L=1, M=1 Place 3 PMOS transistors above NMOS ones. (Figure-28) Figure 28

18 Click on "Basic Library" button (on the right side of the window). Then, click on "Generic Library". The figure shows the generic library (Figure-29) Figure 29 Click on "Ground" and place it below the NMOS transistors. Click on "VDD" and place it above the PMOS transistors. (Figure-30) Figure 30

19 Click on "portin" and place three input ports on the left side. Click on "portout" and place an output port on the right side. (Figure-31) Figure 31 Select the first input port, press q to edit its name, and name it as A. (Value=A) Similarly, name other input ports as B,C and output port as Q. (Figure-32-33) (Port names should be the same as stated in the verilog code.)

20 Press "w" key to start wiring mode. Then, make the connections. (Figure-32-33) Then, press check&save button (3rd button from the left under the menu bar). Close DA-IC. Figure 32-33

21 8- Digital Simulation of NAND3: Return to ICStudio. In the Cell pane, right click and select new view. (Not on nand3) Enter the name "nand3_digitaltest" and type Schematic. DA-IC window will be opened. (Make sure you select the option to see the buttons on the right) Press "i" key to add instance. Tip: You can get a list of short-cut keys for the current view (e.g. Schematic, Layout) from the Reports Hot Keys menu Select test_library : nand3 symbol (Figure-34) Figure 34

22 (To add ports, use the button with a port symbol on the left side of the window.) Add a portin to the left side, select the port and rename it as IN[2:0] by pressing q add a portout to the right side, rename it as OUT. (Figure-35) Figure 35 Press the "W" (Upper case) key to enter bus mode and add a bus starting from the input port (Figure-36). Make sure that the portin is named as IN[2:0]. Figure 36

23 Press to "w" (lower case) key (wire) and connect the input ports of NAND to the bus. You will asked for bit numbers. Enter 0,1, and 2. Then, press "w" and connect the output of NAND3 to OUT. (Figure-37) Figure 37 Click on the "Check&Save" button. Then, click on the Simulation button with a green triangle on the left side. Click on the New Configuration button. (Figure- 38) Figure 38 Select "Digital_Simulation" and enter the name "digitalsim". Click OK twice to enter simulation mode. (Figure-39) Figure 39

24 In the simulation mode, click on the Session button (1 st button on the left below the toolbar), and select Simulator/Viewer. Click on Advance Setup and select ns as time unit. (Figure-40a). Check Use EZWave waveform viewer. Click on OK twice. Figure 40a Click on the Model Selector button (below the ruler button on the left), click on nand3 on the left and click on Verilog on the right. Close the window and click OK on the popping confirmation window.(figure-40b) Figure 40b Note: If you enter simulation mode a second time, the left-side toolbar will change because it knows you are doing a digital simulation. There will be a button on the left which will do both Netlist and Run functions.

25 Click on the Netlist and Run on the right side to start the simulation. Both EZWave (Figure-41) and Modelsim (Figure-42) windows will be opened. You will do your simulations in Modelsim and see the waves in EZWave. Figure 41 Figure 42

26 In ModelSim, in the Objects pane, right click the signal names IN and OUT and select Add to Wave Selected Signals. You have added these signals to wave window. Go to EZWave window and see. (Figure-43) Figure 43 Return to ModelSim, go to Objects pane again. Right click the signal name IN, click "Force" and enter the signal values 101. Click OK. In ModelSim, above the Objects Pane and to the right, set the Run Length as 1 ns (100ns default value). Press on "Run" button which is on the right side of Run Length box. Go to EZWave, and see the results in wave window. Click the plus icon on the right next to the IN signal to view each individual signal. (Figure-44) Figure 44

27 Return to ModelSim, go to Objects pane again. Right click the signal name IN [2], click "Clock" and enter period 2 ns. Click OK. (Figure-45) Right click the signal name IN [1], click "Clock" and enter period 4 ns. Click OK. Right click the signal name IN [0], click "Clock" and enter period 8 ns. Click OK. Change the Run Length to 8ns. Now, click Run button in ModelSim and go to EZWave to see the results. You should see that only one combination of inputs (3 ones) will produce a zero output. Note: The simulation will start at 1 nanosecond since you already ran a 1 nanosecond simulation. Figure 45

28 NOTE: Adding timing to digital simulations: - Go to Schematic window in DA_IC and see that NAND3 gate has properties called like: TDR_A_Q : A to Q rising signal delay TDF_A_Q : A to Q falling signal delay - Click on NAND3, press q (Figure-46) and enter the wanted delay values there. Click Apply- OK. Figure 46 - Restart the simulation and observe the delay on signals. - If changing the cell properties does not add delays, you need to change your verilog code, and define delays in it. (Default values are set to 0.00ns). To do this, delete the symbol from your schematic and from the view-pane in ICstudio. Double-click the verilog code in the view-pane and change the values (Each one will be listed as a parameter. Units are in ns ). When you save the verilog code and exit, icstudio will ask you to regenerate your symbol like it did when you first imported the code. After you save the symbol, right click the verilog code and select Check HDL like you did before. Paste the new symbol into your schematic and rerun the simulation. NOTE: If you don't want to use EZWave to view the waves in DA_IC simulation mode, go to Session Simulator, and uncheck the option to see the waves in EZWave. Then, you can see the waves in ModelSim. NOTE: If you want to run the simulation a second time, you first need to close DA_IC to close your Ezwave session.

29 9- AMS Simulation: For AMS simulation, return to icstudio. In the Cell pane, right click and select new view. (Not on nand3) Enter the name "nand3_analogtest" and select Schematic for view type. DA-IC window will be opened. Press "i" key to add instance. Select test_library : nand3 symbol (Figure-47) Figure 47

30 Add 3 portin's to the left side, rename them as IN1,IN2 and IN3, add a portout to the right side, rename it as OUT. (Figure-48) Figure 48 Click on the Library button then Basic Library and Generic Lib. Choose VDD to add a VDD instance, Ground to add a Ground instance. Click on Back and then Sources Lib. Click on DC to add the power supply and click on Pulse to add a Pulse source. (Figure-49) Change delay of all pulse sources to 0 and adjust the periods and widths to the desired values (p1: 60ns w1:20ns, p2: 80ns w2:30ns, p3:100ns, w3:40ns). Change the magnitude of DC voltage to 1.2V. (Select a source and press q to change its properties. Make sure you press apply after each change). Note: You may need to zoom in to see the screen-shot. Figure 49

31 Click on "Check&Save" button. Then, click Back once and click on the "Simulation" button. (Figure-50) Figure 50 Select "AMS Simulation" and enter the name "analogsim". Click OK twice to enter simulation mode. (Figure-51) Figure 51

32 Click on the Setup button (2 nd button below the toolbar on the left side of the screen) and select Libraries. Click browse button and choose mos_eldo.lib and click OK twice. (Figure 52) Figure 52

33 Click on Setup Analysis button (below the last button you pressed), check Transient and click on setup button right next to Transient. Add the values to the corresponding places as shown in the figure below. Click OK twice. Note: You may have to scroll down on the original window to find the OK button. (Figure-53). Figure 53 Click on Setup Outputs button (It is on the left side and has one black triangle) and choose Save. Check only Voltages and click OK. (Figure 54) Figure 54

34 Click on the button with a single green triangle and see if any error comes out in the opened two log files. If there is no error, click on View Waves button on the left (which has 2 blue waveforms). An Ezwave window will be opened. Choose the waveforms from the left to plot. Right click on the waveform name and choose plot. By default, each waveform will be plotted on a separate graph. To plot multiple waveforms on the same graph, use Shift+click to select multiple waveforms and select Plot(Overlaid) (Figure 55) Figure 55

35 10 DRC LVS Check: Return to icstudio. Click on the EE261LIB on the left. Choose inv on the right. Right click on the inv choose copy. Click on your library (testlibrary) then click on cell pane and right click paste. Import the verilog for the cell so that you can use it for schematics in the future. Do it the same way as before, using the following settings under Verilog/Symbol View Name: inv Verilog Netlist: /ece/digital/share/mgc_hep/technology/ic/mahmutkit/verilog/inv.v Language: Verilog Right click on Layout view of the inv cell properties, under Custom tab choose schematic as the Connectivity Source and click OK. (Figure-56) Figure 56

36 Click twice on Layout view of the inv cell. IC Station window will be opened. (Figure-57) Figure 57

37 DRC: Click on Calibre Run DRC. Change $MGC_HOME to $CAL_HOME and click OK. (Figure-58) Figure 58 In the opened window, click on Run DRC button, then click OK. (Figure-59) Figure 59

38 The Calibre will run DRC and opens some result windows, look for Calibre Interactive DRC: window. The Total Results Generated = line states the number of DRC errors (Figure 60) Figure 60

39 LVS: Close the previous DRC window and click no on the next dialog box. Click on Calibre Run LVS. Calibre Interactive LVS: window will be opened. Under the Netlist tab choose Export from schematic viewer and click on Run LVS button. Click OK on the 2 dialog boxes that come up. (Figure 61) Figure 61

40 The Calibre will run LVS and opens some result windows. Look for smiling face on the LVS Report File window (Figure 62). Figure 62