Chapter 4 Lecture 3 The Microarchitecture Level Integer JAVA Virtual Machine

Transcription

1 Chapter 4 Lecture 3 The Microarchitecture Level Integer JAVA Virtual Machine This is a limited version of a hardware implementation to execute the JAVA programming language. 1 of 30

2 Review The Data Path Register structure The ALU and ALU available operations Data Path Clocking and Timing External Memory Operation Two separate memory ports, one for data and one for instructions) Reading memories (Cycle latency delays) Reading followed by write memories (Cycle latency delays) Microinstructions Each JAVA instruction is translated or expanded into a sequence of microinstructions that require multiple clock cycles to execute. M or MicroProgram Counter: Internal microcode address register MIR or IR Microinstruction Register: Internal instruction used to control the IJVM Elements of the microinstructions (All instructions whether explicit or implicit): Operands what is the operand that goes on the B Bus Execution what ALU and shift operation is to occur Results where are the execution results to be stored from the C Bus and does it involve memory operations Program Control where is the next instruction determined MicroInstructions Elements 2 of 30

3 MIR Content The MIR Fields: B Bus, ALU & Shift, C Bus and Ext. Mem., Next M B Field: Encoded selection of register file output to B Bus Mem Field: External memory control selection for data and instructions C Field: Bit selection of which registers to write from the C Bus ALU Field: Control bits for the ALU and Shift execution elements JAM: Microprogram control flow bits; allow branching, explicitly or in new instructions Addr: The address to be combined to create the M and define the next Microinstruction Encoded B-Bus Selection with a 4:16 Decoder B-Bus Instruction Field B-Bus Register Selected 0000 MDR MBR (signed) 0011 MBRU (unsigned) 0100 SP 0101 LV 0110 CPP 0111 TOS 1000 O 1001 Unassigned 1010 Unassigned 1011 Unassigned 1100 Unassigned 1101 Unassigned 1110 Unassigned 1111 Unassigned 3 of 30

4 IJVM Programmer s Model and Organization Method Area Constant Pool Local Variable Frame Operand Stack External Program Memory containing the IJVM program to be executed. The internal is a pointer in the Method Area to the next instruction to be executed. The method area is accessed using the with 8-bit instructions and parameters loaded into the MBR. External Data Memory containing compiled constants (e.g. values, strings, pointers, etc.) required by the Methods to execute programs. External Data Memory allocated for the storage of variables for the method being executed. When a method is invoked, a local variable frame of predefined size is established (allocated) for all local variables used by the method External Data Memory used for the storage of temporary operands that are placed on the stack. The Operand Stack maximum size is known when a Method is invoked. This allows proper memory allocation and deallocation. 4 of 30

5 Simplified Example of Local Variable Frames Figure 4-8. Use of a stack for storing local variables. (a) While A is active. (b) After A calls B. (c) After B calls C. (d) After C and B return and A calls D. Process A Active Process A Calls Process B; Process B has 4 local variables Process B Calls Process C; Process C has 2 local variables Process C Completes and returns to B Process B Completes and returns to A Process A Calls Process D; Process D has 5 local variables 5 of 30

6 IJVM s JAVA Instruction Set Architecture (p. 250) IJVM s JAVA Instruction Set Hex Mnemonic Meaning Basic Stack Operations Data Movement Instructions 0x10 BIPUSH byte Push byte onto stack 0x13 LDC_W index Push constant from constant pool onto stack 0x15 ILOAD varnum Push local variable onto stack 0x36 ISTORE varnum Pop word from stack and store in local variable 0x57 POP Delete word on top of stack 0x59 DUP Copy top word on stack and push onto stack 0x5F SWAP Swap the two top words on the stack Operand Arithmetic ALU Instructions 0x60 IADD Pop two words from stack; push their sum 0x64 ISUB Pop two words from stack; push their difference 0x7E IAND Pop two words from stack; push Boolean AND 0x80 IOR Pop two words from stack; push Boolean OR 0x84 IINC varnum const Add a constant to a local variable Branching Flow Control Instructions 0x99 IFEQ offset Pop word from stack and branch if it is zero 0x9B IFLT offset Pop word from stack and branch if it is less than zero 0x9F IF_ICMPEQ offset Pop two words from stack; branch if equal 0xA7 GOTO offset Unconditional branch Misc. Other Instructions 0x00 NOP Do nothing 0xC4 WIDE Prefix instruction; next instruction has a 16-bit index Special Operations Subroutine/ISR Control Instructions 0xB6 INVOKEVIRTUAL disp Invoke a method 0xAC IRETURN Return from method with integer value The operands byte, const, and varnum are 1 byte. The operands disp, index, and offset are 2 bytes. 6 of 30

7 Compiling JAVA to IJVM and operating with the stacks (a) A Java fragment. (b) Java assembly language. (c) The IJVM program. LV+3 LV+2 LV+1 LV k j i LV Reference SP TOS=k CPP+3 CPP+2 CPP+1 CPP XXXX XXXX XXXX CPP Ref The initial local variable frame and constant pool The stack after each instruction. (SP address and TOS values change) 7 of 30

8 Implementing IJVM Instructions The microinstructions may be thought of as a micro-assembly language (MAL). The microcode is defined using a symbolic language or pseudo-code that identify every MIR field required for each and every microinstruction. This may be referred to as register transfer notation (RTN) or register transfer language (RTL) The symbolic microcode consists of a label, an operation, and comments. The label is used to assign the address of the microinstruction in the microcode space. The operation field symbolically represents all MIR control functions. The comment field is used to describe the code, machine state, or machine operations. Allowed ALU Operations Source and Destination: any allowable B-bus or C-bus registers in the MIR. Note: this symbolic code defines the A-bus (H Register Value), B-bus, C-bus, and ALU MIR fields. For a complete instruction, we must also include;, memory read or write, the JAMX bits and the next microinstruction field. (all the bits in the MIR!) Illegal Ops: (1) subtraction is SOURCE-H (2) only one value on B-Bus at a time, use H register (3) MAR is not available to the B-Bus (excluded for some reason?) 8 of 30

9 IADD (0x60h) Pop two words from stack; push their sum Instruction Operation Example JAVA: MAL: IADD main1 and iadd1(0x015) to iadd3 Things to do: Increment the to the next instruction and the next instruction. Use the TOS register value (avoid reading the and move it to the H register. Decrement the SP (SP=SP-1), request the data at the new SP (using MAR=SP) and read in the data (to the MDR) at the new SP location. Add the two registered values (H and MDR). Put the result into TOS register and write it to the memory at the new SP address (MDR using MAR=SP). Note: there are memory access delays that must also be accounted for! Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode (0x60h); get next byte; dispatch iadd1 MAR = SP = SP-1; rd Read in next-to-top word on stack iadd2 H = TOS H = top of stack (op theory) iadd3 MDR = TOS = MDR + H; wr; goto main1 Add top two words; write to top of stack main1 = + 1; ; goto (MBR) MBR holds opcode (0x60h); get next byte; dispatch Similar instructions: ISUB, IAND, IOR 9 of 30

10 Executing the JAVA IADD Instruction in Mic-1 Cycle M main1 iadd1 iadd2 iadd3 main1 INST = +1; ; goto (MBR) MAR= SP = SP-1; rd H= TOS MDR= TOS= MDR+H; wr; goto main1 = +1; ; goto (MBR) Next M gt (iadd1) iadd2 iadd3 main1 gt (MBR) +1 MBR IADD=iadd1 INST MAR rd/wr SP-1 rd SP-1 SP-1 wr MDR (@SP-1) MDR+H SP SP SP-1 LV CPP TOS (@SP) MDR+H H TOS (@SP) 10 of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured

11 Example: adding TOS with a memory and writing back This is the IADD instruction shown at the clock cycle level. (1) (2) (3) CPU CLK MAR Address Bus MAR SP-1 RD# WR# Memory H H TOS Read Latency Write Latency MAR=SP-1; rd; % read delay of one clock cycle required H=TOS; % use delay to load H register MDR=H+MDR; wr; % crate the sum and write on the following clock cycle 11 of 30

12 The IJVM MAL (p ) IJVM Microinstruction 1 (MIC-1) Architecture Language (1 of 4) main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch nop1 goto main1 Do nothing iadd1 MAR = SP = SP-1; rd Read in next-to-top word on stack iadd2 H = TOS H = top of stack iadd3 MDR = TOS = MDR + H; wr; goto main1 Add top two words; write to top of stack isub1 MAR = SP = SP-1; rd Read in next-to-top word on stack isub2 H = TOS H = top of stack isub3 MDR = TOS = MDR - H; wr; goto main1 Do subtraction; write to top of stack iand1 MAR = SP = SP-1; rd Read in next-to-top word on stack iand2 H = TOS H = top of stack iand3 MDR= TOS = MDR AND H; wr; goto main1 Do AND; write to new top of stack ior1 MAR = SP = SP-1; rd Read in next-to-top word on stack ior2 H = TOS H = top of stack ior3 MDR = TOS = MDR OR H; wr; Do OR; write to new top of stack goto main1 dup1 MAR = SP = SP + 1 Increment SP and copy to MAR dup2 MDR = TOS; wr; goto main1 Write new stack word pop1 MAR = SP = SP-1; rd Read in next-to-top word on stack pop2 Wait for new TOS to be read from memory pop3 TOS = MDR; goto main1 Copy new word to TOS swap1 MAR = SP-1; rd Set MAR to SP-1; read 2nd word from stack swap2 MAR = SP Set MAR to top word swap3 H = MDR; wr Save TOS in H; write 2nd word to top of stack swap4 MDR = TOS Copy old TOS to MDR swap5 MAR = SP-1; wr Set MAR to SP-1; write as 2nd word on stack swap6 TOS = H; goto main1 Update TOS 12 of 30

13 IJVM Microinstruction 1 (MIC-1) Architecture Language (2 of 4) bipush1 SP = MAR = SP + 1 MBR = the byte to push onto stack bipush2 = + 1; Increment, next opcode bipush3 MDR = TOS = MBR; wr; goto main1 Sign-extend constant and push on stack iload1 H = LV MBR contains index; copy LV to H iload2 MAR = MBRU + H; rd MAR = address of local variable to push iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write iload4 = + 1; ; wr Inc ; get next opcode; write top of stack iload5 TOS = MDR; goto main1 Update TOS istore1 H = LV MBR contains index; Copy LV to H istore2 MAR = MBRU + H MAR = address of local variable to store into istore3 MDR = TOS; wr Copy TOS to MDR; write word istore4 SP = MAR = SP-1; rd Read in next-to-top word on stack istore5 = + 1; Increment ; next opcode istore6 TOS = MDR; goto main1 Update TOS wide1 = + 1; ; Multiway branch with high bit set goto (MBR OR 0x100) wide_iload1 = + 1; MBR contains 1st index byte; 2nd wide_iload2 H = MBRU << 8 H = 1st index byte shifted left 8 bits wide_iload3 H = MBRU OR H H = 16-bit index of local variable wide_iload4 MAR = LV + H; rd; goto iload3 MAR = address of local variable to push wide_istore1 = + 1; MBR contains 1st index byte; 2nd wide_istore2 H = MBRU << 8 H = 1st index byte shifted left 8 bits wide_istore3 H = MBRU OR H H = 16-bit index of local variable wide_istore4 MAR = LV + H; goto istore3 MAR = address of local variable to store into ldc_w1 = + 1; MBR contains 1st index byte; 2nd ldc_w2 H = MBRU << 8 H = 1st index byte << 8 ldc_w3 H = MBRU OR H H = 16-bit index into constant pool ldc_w4 MAR = H + CPP; rd; goto iload3 MAR = address of constant in pool 13 of 30

14 IJVM Microinstruction 1 (MIC-1) Architecture Language (3 of 4) iinc1 H = LV MBR contains index; Copy LV to H iinc2 MAR = MBRU + H; rd Copy LV + index to MAR; Read variable iinc3 = + 1; Fetch constant iinc4 H = MDR Copy variable to H iinc5 = + 1; Fetch next opcode iinc6 MDR = MBR + H; wr; goto Put sum in MDR; update variable main1 goto1 O = - 1 Save address of opcode. goto2 = + 1; MBR = 1st byte of offset; 2nd byte goto3 H = MBR << 8 Shift and save signed first byte in H goto4 H = MBRU OR H H = 16-bit branch offset goto5 = O + H; Add offset to O goto6 goto main1 Wait for of next opcode iflt1 MAR = SP = SP - 1; rd Read in next-to-top word on stack iflt2 O = TOS Save TOS in O temporarily iflt3 TOS = MDR Put new top of stack in TOS iflt4 N = O; if (N) goto T; else goto Branch on N bit F ifeq1 MAR = SP = SP - 1; rd Read in next-to-top word of stack ifeq2 O = TOS Save TOS in O temporarily ifeq3 TOS = MDR Put new top of stack in TOS ifeq4 Z = O; if (Z) goto T; else goto Branch on Z bit F if_icmpeq1 MAR = SP = SP - 1; rd Read in next-to-top word of stack if_icmpeq2 MAR = SP = SP - 1 Set MAR to read in new top-ofstack if_icmpeq3 H = MDR; rd Copy second stack word to H if_icmpeq4 O = TOS Save TOS in O temporarily if_icmpeq5 TOS = MDR Put new top of stack in TOS if_icmpeq6 Z = O - H; if (Z) goto T; else goto F If top 2 words are equal, goto T, else goto F T O = - 1; goto goto2 Same as goto1; needed for target address F = + 1 Skip first offset byte F2 = + 1; now points to next opcode F3 goto main1 Wait for of opcode 14 of 30

15 IJVM Microinstruction 1 (MIC-1) Architecture Language (4 of 4) invokevirtual1 = + 1; MBR = index byte 1; inc., get 2nd byte invokevirtual2 H = MBRU << 8 Shift and save first byte in H invokevirtual3 H = MBRU OR H H = offset of method pointer from CPP invokevirtual4 MAR = CPP + H; rd Get pointer to method from CPP area invokevirtual5 O = + 1 Save Return in O temporarily invokevirtual6 = MDR; points to new method; get param count invokevirtual7 = + 1; Fetch 2nd byte of parameter count invokevirtual8 H = MBRU << 8 Shift and save first byte in H invokevirtual9 H = MBRU OR H H = number of parameters invokevirtual10 = + 1; Fetch first byte of # locals invokevirtual11 TOS = SP - H TOS = address of OBJREF - 1 invokevirtual12 TOS = MAR = TOS + 1 TOS = address of OBJREF (new LV) invokevirtual13 = + 1; Fetch second byte of # locals invokevirtual14 H = MBRU << 8 Shift and save first byte in H invokevirtual15 H = MBRU OR H H = # locals invokevirtual16 MDR = SP + H + 1; wr Overwrite OBJREF with link pointer invokevirtual17 MAR = SP = MDR; Set SP, MAR to location to hold old invokevirtual18 MDR = O; wr Save old above the local variables invokevirtual19 MAR = SP = SP + 1 SP points to location to hold old LV invokevirtual20 MDR = LV; wr Save old LV above saved invokevirtual21 = + 1; Fetch first opcode of new method. invokevirtual22 LV = TOS; goto main1 Set LV to point to LV Frame ireturn1 MAR = SP = LV; rd Reset SP, MAR to get link pointer ireturn2 Wait for read ireturn3 LV = MAR = MDR; rd Set LV to link ptr; get old ireturn4 MAR = LV + 1 Set MAR to read old LV ireturn5 = MDR; rd; Restore ; next opcode ireturn6 MAR = SP Set MAR to write TOS ireturn7 LV = MDR Restore LV ireturn8 MDR = TOS; wr; goto main1 Save return value on original top of stack 15 of 30

16 IJVM Classes of Instructions (Instruction Set Architecture) Hex Mnemonic Meaning Basic Stack Operations Data Movement Instructions 0x10 BIPUSH byte Push byte onto stack 0x13 LDC_W index Push constant from constant pool onto stack 0x15 ILOAD varnum Push local variable onto stack 0x36 ISTORE varnum Pop word from stack and store in local variable 0x57 POP Delete word on top of stack 0x59 DUP Copy top word on stack and push onto stack 0x5F SWAP Swap the two top words on the stack Operand Arithmetic ALU Instructions 0x60 IADD Pop two words from stack; push their sum 0x64 ISUB Pop two words from stack; push their difference 0x7E IAND Pop two words from stack; push Boolean AND 0x80 IOR Pop two words from stack; push Boolean OR 0x84 IINC varnum const Add a constant to a local variable Branching Flow Control Instructions 0x99 IFEQ offset Pop word from stack and branch if zero 0x9B IFLT offset Pop word from stack and branch if less than zero 0x9F IF_ICMPEQ offset Pop two words from stack; branch if equal 0xA7 GOTO offset Unconditional branch Misc. Other Instructions 0x00 NOP Do nothing 0xC4 WIDE Prefix instruction; next instruction has a 16-bit index Special Operations Subroutine/ISR Control Instructions 0xB6 INVOKEVIRTUAL disp Invoke a method 0xAC IRETURN Return from method with integer value The operands byte, const, and varnum are 1 byte. The operands disp, index, and offset are 2 bytes. 16 of 30

17 DUP (0x59h) Pop the top value from the stack, push it back on the stack and then push another copy. JAVA: MAL: DUP main1 and dup1(0x59h) to dup2 Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch dup1 MAR = SP = SP + 1 Increment SP and copy to MAR dup2 MDR = TOS; wr; goto main1 Write new stack word Similar instructions: BIPUSH (0x10h) Push the supplied byte onto the stack. JAVA: BIPUSH byte MAL: main1 and bipush1(0x010) to bipush3 Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch bipush1 SP = MAR = SP + 1 MBR = the byte to push onto stack bipush2 = + 1; Increment, next opcode bipush3 Similar instructions: MDR = TOS = MBR; wr; goto main1 Sign-extend constant and push on stack 17 of 30

18 Executing the JAVA DUP Instruction in Mic-1 Cycle M main1 dup1 dup2 main1 INST = +1; ; goto (MBR) MAR = SP = SP + 1 MDR = TOS; wr; goto main1 = +1; ; goto (MBR) Next M gt (dup1) dup2 main1 gt (MBR) +1 MBR dup1 INST MAR rd/wr SP+1 wr MDR TOS SP SP SP+1 LV CPP TOS (@SP) H 18 of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured

19 Executing the JAVA BIPUSH Instruction in Mic-1 Cycle M main1 bipush1 bipush2 bipush3 main1 INST = +1; ; goto (MBR) SP = MAR = SP + 1 = + 1; MDR = TOS = MBR; wr; goto main1 = +1; ; goto (MBR) Next M gt (bipush1) bipush2 bipush3 main1 gt (MBR) MBR bipush1 BYTE INST MAR rd/wr SP+1 wr MDR BYTE SP SP SP+-1 LV CPP TOS (@SP) BYTE H 19 of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured

20 After further analysis: the MBR must operate as both gated latch and a clock flip-flop The gated latch is required by the Micro Program Counter. The M address must be used two clock cycles after the next instruction is requested using Main1. The MBR and MBRU data must be available on the B-bus for proper delay propagation and computation aligned to clock edges with 2 cycle delay after. Therefore, the MBR must be two separate fates, a gated D-latch for M and a clocked D flip=flop for the B-Bus!!! (1) CPU CLK I address bus +1 Fetch# Instruction Data Bus Next Inst or byte Fetch Latency MBR Latched by M Main1" MBR Clocked MAIN1: = + 1; ; goto (MBR) % MBR holds opcode; get next byte; dispatch 20 of 30

21 ILOAD (0x15h) Pushing a variable from the Local Variable Memory Space unto the stack JAVA: ILOAD varnum MAL: main1 and iload1(0x015) to iload5 Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch iload1 H = LV MBR contains index; copy LV to H iload2 MAR = MBRU + H; rd MAR = address of local variable to push iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write iload4 = + 1; ; wr Inc ; get next opcode; write top of stack iload5 TOS = MDR; goto main1 Update TOS Similar instructions: ISTORE 21 of 30

22 Executing the JAVA ILOAD Instruction in Mic-1 Cycle M main1 iload1 iload2 iload3 iload4 iload5 main1 INST = +1; ; goto (MBR) H= LV MAR= MBRU + H; rd MAR= SP = SP+1 = +1; ; wr TOS= MDR; goto main1 = +1; ; goto (MBR) Next M gt (iload1) iload2 iload3 iload4 iload5 main1 gt (MBR) MBR iload1 VARNM INST MAR rd/wr LV+VARNM rd SP+1 wr MDR PARAM SP SP SP+1 LV CPP TOS (@SP) PARAM H LV 22 of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured

23 WIDE ILOAD (0xC4 0x15) Pushing a variable from the Local Variable Memory Space unto the stack JAVA: WIDE ILOAD varnum1 varnum2 MAL: main1 and wide_iload1(0x115) to wide_iload4 and iload3 to iload5 Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch wide1 = + 1; ; goto (MBR OR 0x100) Multiway branch with high bit set wide_iload1 = + 1; MBR contains 1st index byte; 2nd wide_iload2 H = MBRU << 8 H = 1st index byte shifted left 8 bits wide_iload3 H = MBRU OR H wide_iload4 MAR = LV + H; rd; goto iload3 H = 16-bit index of local variable MAR = address of local variable to push iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write iload4 = + 1; ; wr Inc ; get next opcode; write top of stack iload5 TOS = MDR; goto main1 Update TOS Similar instructions: WIDE ISTORE, WIDE LDC_W index1 index2 23 of 30

24 Executing the JAVA WIDE ILOAD Instruction in Mic-1 Cycle M main1 wide1 wide_iload1 wide_iload2 wide_iload3 wide_iload4 iload3 INST Next M = +1; ; goto (MBR) gt (wide1) = + 1; ; goto (MBR OR 0x100) (0x00 OR JAMC) +1 = + 1; H = MBRU << 8 H = MBRU OR H MAR = LV + H; rd; goto iload3 MAR= SP = SP+1 wide_iload2 wide_iload3 wide_iload4 iload3 iload MBR wide1 iload1 VAR1 VAR2 MAR rd/wr MDR SP SP LV CPP TOS (@SP) H VAR1<< 8 VAR1<< 8 OR VAR2 LV+H rd 24 of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured

25 IINC (0x84) Increment (add a 2 s comp constant to) a local variable JAVA: IINC varnum1 constant MAL: main1 and iinc1(0x084) to iinc6 Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch iinc1 H = LV MBR contains index; Copy LV to H iinc2 MAR = MBRU + H; rd Copy LV + index to MAR; Read variable iinc3 = + 1; Fetch constant iinc4 H = MDR Copy variable to H iinc5 = + 1; Fetch next opcode iinc6 MDR = MBR + H; wr; goto main1 Put sum in MDR; update variable GOTO (0xA7) Unconditional branch operation JAVA: GOTO offset MAL: main1 and goto1(0x0a7) to goto6 Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch goto1 O = - 1 Save address of opcode. goto2 = + 1; MBR = 1st byte of offset; 2nd byte goto3 H = MBR << 8 Shift and save signed first byte in H goto4 H = MBRU OR H H = 16-bit branch offset goto5 = O + H; Add offset to O goto6 goto main1 Wait for of next opcode 25 of 30

26 IFLT (0x9B) Conditional branch operation based on TOS value JAVA: IFLT offset MAL: main1 and iflt1(0x09b) to iflt4 then T or F Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch iflt1 MAR = SP = SP - 1; rd Read in next-to-top word on stack iflt2 O = TOS Save TOS in O temporarily iflt3 TOS = MDR Put new top of stack in TOS iflt4 N = O; if (N) goto T; else goto F Branch on N bit F = + 1 Skip first offset byte F2 = + 1; now points to next opcode F3 goto main1 Wait for of opcode T O = - 1; ; goto goto2 Same as goto1; needed for target address goto2 = + 1; MBR = 1st byte of offset; 2nd byte goto3 H = MBR << 8 Shift and save signed first byte in H goto4 H = MBRU OR H H = 16-bit branch offset goto5 = O + H; Add offset to O goto6 goto main1 Wait for of next opcode 26 of 30

27 Executing the JAVA IFLT(False) Instruction in Mic-1 Cycle M main1 iflt1 iflt2 iflt3 iflt4 F F2 F3 main1 INST Next M = +1; ; goto (MBR) MAR = SP = SP - 1; rd O = TOS TOS = MDR N = O; if (N) goto T; else goto F = + 1 = + 1; goto main1 = +1; ; goto (MBR) gt (iflt1) iflt2 iflt3 iflt4 F F2 F3 main1 gt (MBR) +1 MBR wide1 Offset_B1 INST MAR rd/wr SPI-1 rd MDR (@SP-1) SP SP SP-1 LV CPP TOS (@SP) (@SP-1) O TOS H of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured

28 Executing the JAVA IFLT(True) Instruction in Mic-1 Cycle etc M main1 iflt1 iflt2 iflt3 iflt4 T goto2 goto3 etc INST = +1; ; goto (MBR) MAR = SP = SP - 1; rd O = TOS TOS = MDR N = O; if (N) goto T; else goto F O = - 1; goto goto2 = + 1; H = MBR << 8 Next M gt (iflt1) iflt2 iflt3 iflt4 F goto2 goto3 goto4 etc MBR wide1 Off_B1 Off_B1 INST MAR rd/wr SPI-1 rd MDR (@SP-1) SP SP SP-1 LV CPP TOS (@SP) (@SP-1) O TOS -1 H Off_B1<<8 28 of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured

29 Define your own instruction (0x??) Description of instruction JAVA: MAL: main1 and Label Operations Comments main1 = + 1; ; goto (MBR) MBR holds opcode; get next byte; dispatch 29 of 30

30 Define your own instruction sequence page for practice. Executing the JAVA Instructions in Mic-1 Cycle M main1 INST = +1; ; goto (MBR) Next M gt (MBR) +1 MBR uinst Next Inst MAR rd/wr MDR SP LV CPP TOS H 30 of 30 Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured