ITU-T G.813 Compliance Test Results for: Si5348. Rev 1.0 August Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 1 of 26

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2 Contents 1. Wander Generation Wander Generation MTIE, G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348: PASS Wander Generation TDEV, G.813 SEC Option1 (Done with Section 1.1) Requirement Compliance RESULTS Si5348: PASS Wander Transfer Transfer Function of the PLL for SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348 SEC Option 1: PASS Wander Tolerance Wander Tolerance G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348: PASS Jitter Tolerance Jitter Tolerance G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348 SEC Option 1: PASS Phase Transient Generation Short Term Phase Transient Response G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348: PASS Phase Transient Generation w/ Signal Interruptions G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348: PASS Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 2 of 26

3 5.4. Phase Discontinuity G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348: PASS Holdover Holdover G.813 SEC Option Input and Output Parameters Requirement Compliance Results Si5348: PASS Free-run Accuracy Free-run Accuracy G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348: PASS Pull-in/Hold-in Pull-in Range G.813 SEC Option Input and Output Parameters Requirement Compliance RESULTS Si5348: PASS Conclusion Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 3 of 26

4 Introduction This report reviews and explains the results of the G.813 SEC Option 1 compliance testing that has been verified for the Si5348 device. This document will give a summary of the test set-ups, as well as the compliance criteria while showing the results from each test. Testing was done using the ANUE 3500, and in some cases other test equipment. The device-under-test (Si5348) was configured and controlled using Silicon Lab s ClockBuilder Pro Software. Each of the tests includes references to the CBPro project files (e.g., Si5348-PullinOption1.slabtimeproj) used to enable the Si543x device to pass each test. The project files (attached to this PDF document) should be used by designers as guidelines to follow when configuring a specific design for G.813 compliance. All CBPro project files are accessible attachments in this report file. Option 1 SEC compliance was tested at 4Hz target loop bandwidth. ITU-T G.813 Standards Matrix Test G.813 Description SEC Opt 1 Compliance Board* 1. Wander Generation 1.1 MTIE, TDEV SEC Option 1, Must not exceed MTIE 7.1a Si TDEV masks 7.1a Si Wander Transfer 2.1 Transfer Function of the PLL SEC Option 1: Look for peaking 9a Si Wander Tolerance 3.1 Wander Tolerance SEC Option 1: File Playback 8.1a Si Jitter Tolerance 4.1 Automated way of injecting noise and monitoring LOL 8.2a Si Phase Transient Generation 5.1 Short Term Phase Transient SEC Option a Si Phase Transient Generation w/ Signal Interruptions SEC Option a Si Phase Discontinuity SEC Option a Si Holdover Performance 6.1 SEC Option a Si Freerun Accuracy 7.1 SEC Option 1 5a Si Pull-in/Hold-in 8.1 Pull-In and Hold-In SEC Option 1 6.1a 6.2a Si5348 Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 4 of 26

5 1. Wander Generation Symmetricom MHz Reference 10MHz BNC ANUE 3500 BOX 25MHz 25MHZ OCXO 12.8MHz IN0 REF Si534x Evaluation Board USB OUT0 PC Figure 1: Wander Generation Test Set-up Equipment Anue 3500 Box Symmetricom MHz Reference Windows 7 PC, Running ClockBuilder Pro DUT: Si5348 OCXO: Rakon STP Wander Generation MTIE, G.813 SEC Option 1 While the PLL is locked to an input clock signal that is wander free, it will not generate wander that exceeds the MTIE mask shown in figure 1/G.813. There is no noise modulation added into the input Input and Output Parameters 10MHz Symmetricom 8040 reference to Anue Box 25MHz Input to DUT generated from Anue Box 25MHz Output from DUT measured by Anue Box Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4 Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 7.1a Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 5 of 26

6 RESULTS Si5348: PASS MTIE LIMIT MTIE Result TDEV LIMIT TDEV Result Figure 2: Si5348 SEC Option 1 Wander Generation MTIE and TDEV Results 1.2. Wander Generation TDEV, G.813 SEC Option1 (Done with Section 1.1) While the PLL is locked to an input clock signal that is wander free, it will not generate wander that exceeds the TDEV mask shown in 7.1a Figure 2/G.813. The wander free clock signal must include band-limited (10 Hz single-poll rolloffs). Use test data from above having collected both MTIE and TDEV at the same Requirement Compliance ITU-T G.813 SEC Option 1, Section 7.1a RESULTS Si5348: PASS Results for Si5348 are shown in graph above in section Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 6 of 26

7 2. Wander Transfer Symmetricom MHz Reference 10MHz BNC ANUE 3500 BOX 25MHz 25MHZ OCXO 12.8MHz IN0 REF Si534x Evaluation Board USB OUT0 PC Figure 3: Wander Transfer Test Set-up Equipment Anue 3500 Box Symmetricom MHz Reference Windows 7 PC, Running ClockBuilder Pro DUT: Si5348 OCXO: Rakon STP Transfer Function of the PLL for SEC Option 1 Wander transfer is determined by the PLL loop BW and peaking. Option 1 has a 1 Hz to 10Hz BW. Option 1 requires <0.2dB of peaking Input and Output Parameters 10MHz Symmetricom 8040 reference to Anue Box 25MHz Input to DUT generated from Anue Box 25MHz Output from DUT measured by Anue Box Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4 Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Section 9a Option 1 Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 7 of 26

8 RESULTS Si5348 SEC Option 1: PASS The peaking is less than 0.04dB from the results. The device has an actual loop bandwidth of 4.46 Hz. Figure 4: Si5348 SEC Option 1 Transfer Function Results. Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 8 of 26

9 3. Wander Tolerance Symmetricom MHz Reference 10MHz BNC ANUE 3500 BOX 25MHz 25MHZ OCXO 12.8MHz IN0 REF Si534x Evaluation Board USB OUT0 PC Figure 5: Wander Tolerance Test Set-up Equipment Anue 3500 Box Symmetricom MHz Reference Windows 7 PC, Running ClockBuilder Pro Si534x Evaluation Board with Si5348 DUT OCXO: Rakon STP3158 Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 9 of 26

10 3.1. Wander Tolerance G.813 SEC Option 1 A PLL that is locked to an input clock must be able to tolerate the wander defined in Figure 5/G.813 SEC Option 1. The definition of tolerate is such that the device will not trigger any alarms (LOS, OOF, LOL) while locked to such an input clock and it will be able to pull-in to such an input clock Input and Output Parameters 10MHz Symmetricom 8040 reference to Anue Box 25MHz Input to DUT generated from Anue Box Input File: TDEV mask shown in Figure 6 of G.813 standard 25MHz Output from DUT measured by Anue Box Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4 Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 8.1a RESULTS Si5348: PASS No alarms (LOL, LOS, or OOF) on the Si5348 were asserted during the file playback process for wander tolerance for SEC Option 1. Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 10 of 26

11 4. Jitter Tolerance Agilent MHz Generator with FM modulation IN0 Si534x Evaluation Board REF USB 12.8MHz OCXO PC Figure 6: Jitter Tolerance Test Set-up Equipment Agilent Signal Generator Windows 7 PC, Running ClockBuilder Pro DUT: Si5348 OCXO: Rakon STP Jitter Tolerance G.813 SEC Option 1 A PLL that is locked to an input clock must be able to tolerate the jitter defined in Figure 9/G.813. The definition of tolerate is that the device will not trigger any alarms (LOS, OOF, LOL) while locked to such an input clock and it will be able to pull-in to such an input clock. SEC Option 1 the DUT is set up with 1-10Hz loop BW Input and Output Parameters 25MHz Input to DUT Generated from Agilent Signal Generator with FM modulation 25MHz Output from DUT Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4 Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 8.2a Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 11 of 26

12 p-p Jitter (ns) RESULTS Si5348 SEC Option 1: PASS Si5348 Jitter Tolerance For SEC Option 1 G813 Mask 4Hz BW Modulation Frequency (Hz) Figure 7: Si5348 SEC Option 1 Jitter Tolerance Results The measured results are shown by the blue trace. They are intended to be above the orange trace representing the mask found in G.813. The results are the maximum input jitter before failure, however these values are largely limited by test equipment, NOT by the device. Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 12 of 26

13 5. Phase Transient Generation Agilent 33600A Silicon Labs Clock Gapper IN0 IN1 REF Si534x Evaluation Board OUT0 USB 12.8MHz OCXO PC Symmetricom MHz Reference BNC ANUE 3500 Box Figure 8: Phase Transient Generation Set-up. Equipment Anue 3500 Box Symmetricom MHz Reference Windows 7 PC, Running ClockBuilder Pro Silicon Labs Clock Gapper the purpose of the clock gapper is to stop the clock going to the Si534x without causing runt pulses or elongated clocks DUT: Si5348 OCXO: Rakon STP3158 AWG: Agilent 33600A set to shut off the clocks for 15 seconds Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 13 of 26

14 5.1. Short Term Phase Transient Response G.813 SEC Option 1 The device is forced into holdover for 15 seconds by the removal of the input clock using the Silabs clock gapper. After the input is removed, the Si534x will use its automatic switching feature to locate another valid input, otherwise, the device goes into holdover. After 15 seconds, the input is returned again using the Silabs clock gapper and holdover is exited automatically. The test is completed after an entry into holdover and exit from holdover has taken place within 15 seconds. The output phase variation, relative to the input reference before it was lost, is bounded by the following requirements: The phase error should not exceed t + 5 x 10-8 x S seconds over any period S up to 15 seconds. t represents two phase jumps that may occur during the transition into and out of the holdover state which both should not exceed 120 ns with a temporary frequency offset of no more than 7.5 ppm. The resultant overall requirement is summarized in figure 12/G.813. This figure is intended to depict the worst case phase movement attributable to an SEC reference clock switch Input and Output Parameters 25MHz Input to DUT from Buffer into IN0 (IN1 Enabled, but no Input present) 25MHz Output from DUT Measured on Anue BNC3 Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4 Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 10.1a Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 14 of 26

15 RESULTS Si5348: PASS MTIE Option 1 LIMIT MTIE Option 1 Si5348 Result Figure 9: Si5348 Short Term Phase Transient SEC Option 1 Results. Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 15 of 26

16 5.3. Phase Transient Generation w/ Signal Interruptions G.813 SEC Option1 An input interruption that does not force a switchover will not cause an output phase transient greater than 120ns with a maximum frequency offset of 7.5ppm in a period of 16ms. The signal will be stretched (gapped) as far as possible to the limit of the switchover and then the output phase transient will be measured Input and Output Parameters 25MHz gapped input from Anue Box through clock gapper into DUT 25MHz Output from DUT Measured on Anue Box Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4 Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 10.3a RESULTS Si5348: PASS MTIE Option 1 LIMIT MTIE Option 1 Si5348 Result Figure 10: Si5348 Clock Gap Interruptions MTIE measurement SEC Option 1. Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 16 of 26

17 5.4. Phase Discontinuity G.813 SEC Option 1 Switching between two input clocks of the same frequency but with different phase (up to 62.5us) will not cause an output phase transient greater than what is outlined in section 10.3a of G.813. There will be two inputs that are 180 degrees out of phase going into the DUT. The idea is to switch between the two inputs with a phase difference of 62.5us. The output will be measured to ensure that the objective in Figure 12 is still met. Automated loop in VB to loop switching the inputs with a 10 second delay. OCXO PC SRS Clock Generator 8kHz 8kHz IN0 IN1 REF Si534x Evaluation Board USB OUT0 25MHz 10MHz Symmetricom MHz Reference 10MHz BNC ANUE 3500 Box Figure 11: Phase Discontinuity Test Set-up Equipment Anue 3500 Box Symmetricom MHz Reference Windows 7 PC, Running ClockBuilder Pro DUT: Si5348 SRS CG635 Clock Generator OCXO: Rakon STP Input and Output Parameters 300kHz Input to DUT Generated from Agilent Signal Generator on IN0 and 180 out of phase IN1 Hitless Switching Enabled 25MHz Output from DUT Measured on Anue BNC3 Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4 Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 10.4a Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 17 of 26

18 RESULTS Si5348: PASS MTIE Option 1 LIMIT MTIE Option 1 Si5348 Result Figure 12: Si5348 SEC Option 1 Phase Discontinuity Result. Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 18 of 26

19 6. Holdover Symmetricom MHz Reference 10MHz BNC ANUE 3500 BOX 25MHz 25MHZ IN0 IN1 Si534x Evaluation Board OUT0 OCXO REF USB PC Figure 13: Holdover Test Set-up. Equipment Anue 3500 Box Symmetricom MHz Reference Windows 7 PC, Running ClockBuilder Pro Si534x Evaluation Board with Si5348 DUT OCXO: Rakon STP Holdover G.813 SEC Option 1 A PLL in holdover will meet the requirements in Figure 14/G.813. The DUT obtains lock from IN0, which contains a valid input clock. Then the input is switched to IN1, which contains no valid input, thus entering holdover and remains in holdover for the remainder of the test Input and Output Parameters 25MHz Input to DUT from Buffer into IN0 (IN1 Enabled, but no Input present) 25MHz Output from DUT Measured on Anue BNC3 Rakon STP3158 Reference Frequency: 12.8 MHz G.813 SEC Option 1: 4Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 10.2a Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 19 of 26

21 7. Free-run Accuracy Symmetricom MHz Reference 10MHz BNC Frequency Counter ANUE 3500 BOX 10MHz 25MHZ IN0 Si534x Evaluation Board OUT0 Frequency Generator +/-4.6ppm REF USB PC Figure 15: Free-run Test Set-up. Equipment Symmetricom MHz Connection Link Windows 7 PC, Running ClockBuilder Pro DUT: Si5348 Agilent 53132A Universal Counter Agilent Signal Generator Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 21 of 26

22 7.1. Free-run Accuracy G.813 SEC Option 1 The free-run frequency will never exceed +/- 4.6ppm. This includes initial power-up or whenever there wasn t enough holdover history accumulated Input and Output Parameters 25MHz Output from DUT Measured on Frequency Counter 12.8MHz Input from Frequency Generator to REF G.813 SEC Option 1: 4Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 5a RESULTS Si5348: PASS Test Conditions REF Input Output Si5348 SEC Option MHz +4.6ppm MHz (25MHz +4.6ppm) Si5348 SEC Option MHz -4.6ppm MHz (25MHz -4.6ppm) Table 1: Si5348 Free-run Accuracy Results Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 22 of 26

23 8. Pull-in/Hold-in Symmetricom MHz Reference 10MHz BNC Frequency Counter ANUE 3500 BOX 10MHz 25MHZ 10MHz Frequency Generator +/-4.6ppm IN0 Si534x Evaluation Board OUT0 Frequency Generator +/-4.6ppm REF USB PC Figure 16: Pull-in/Hold-in Test Set-up Equipment Symmetricom MHz Connection Link Windows 7 PC, Running ClockBuilder Pro DUT: Si5348 Agilent 53132A Universal Counter Agilent Signal Generator Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 23 of 26

24 8.1. Pull-in Range G.813 SEC Option 1 A PLL which is in free-run or holdover within a +/- 4.6 ppm frequency range (based on its TCXO/OCXO) will be able to pull-in to a reference that is within +/- 4.6 ppm frequency. In other words the PLL should be able to pull-in a minimum of +/- 9.2 ppm Input and Output Parameters 25MHz Input to DUT from Frequency Generator 12.8MHz Input from Frequency Generator to REF 25MHz Output from DUT G.813 SEC Option 1: 4Hz Loop Bandwidth Setting on the DUT Requirement Compliance ITU-T G.813 SEC Option 1, Section 5a RESULTS Si5348: PASS Si5348 SEC Option 1 25MHz Input 12.8MHz REF Output -4.6ppm IN0 +4.6ppm MHz (-4.6ppm) +4.6ppm IN0-4.6ppm MHz (+4.6ppm) -4.6ppm IN0-4.6ppm MHz (-4.6ppm) +4.6ppm IN0 +4.6ppm MHz (+4.6ppm) Table 2: Pull-In/Hold-In Results for the Si5348 *For all tests above, no alarms were asserted. Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 24 of 26

25 9. Conclusion The Si5348 is a high performance jitter attenuating clock multiplier which can generate any output frequency from any frequency within its input and output frequency range. The Si5348 device provides the entire clock functionality required for SDH slave clock applications and include the following key features: Programmable loop bandwidth, which can be set to SEC Option 1 Hitless Switching A suite of loss of lock alarms Full compatibility with the free Silicon Labs ClockBuilder Pro software Wander filtering The Si5348 device, along with a compliant TCXO or OCXO, fully meets the requirements set in ITU-T G.813 (03/2002). Rev. 1.0, Aug-2015 Copyright 2015 by Silicon Laboratories Page 25 of 26