Low Temperature Co-fired Ceramic (LTCC) Design Guidelines for RF 3D Package Module Design
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1 Low Temperature Co-fired Ceramic (LTCC) Design Guidelines for RF 3D Package Module Design Purpose The purpose of this document is to give an overview of design guidelines for LTCC (Low Temperature Co-fired Ceramic) material set. Scope This document covers assembly and substrate design guidelines for LTCC and substrates for use with SMD, chip and wire, and flip chip assembly. Process Overview The ceramic modules are built by first placing the chip components using an SMT line. After the surface mount devices are mounted to the module, the final assembly is done on the ceramic back-end manufacturing line. The ceramic back-end process capability includes: -chip attach and underfill arking Depending on the module design, some or all of these process steps may be required. For many features, both standard and advanced design rules are given. The standard rules are generally applicable to designs using LTCC materials. The advanced design rules may not apply to all types of materials and approval by Amkor product management is required before advanced rules are used. Material Properties The following table lists typical material properties for LTCC substrates MATERIAL CTE THERMAL CONDUCTIVITY [ 10-6/K] Yamamula GCS71EAS Hereaus 51555W MATERIAL Yamamula GCS71EAS Hereaus 51555W SPECIFIC HEAT YOUNG'S MODULUS [GPa] SHRINKAGE (X, Y) SHRINKAGE (Z) % 23% 5.2 TBD 17% 23% BENDING STRENGTH [MPa] DIELECTRIC 1MHz,R.T. DIELECTRIC 10GHz,R.T. DIELECTRIC 1MHz,R.T. DIELECTRIC 10GHz,R.T TBD <30 TBD TBD 7.5 TBD <10 TBD VOLUME RESISTIVITY [Ohmm]
2 The coefficient of the thermal change of dielectric constant for GCS series is approximately 50ppm. The following table lists resistivity values for common conductor materials. Ag and PdAg are typically used for conductor traces in LTCC substrates. Au is used in plating of the co-fired top and bottom metallization layers. RESISITIVITY Ag PdAg Au PATTERN METALLIZATION 4mΩ/sq 3.2±0.8mΩ/sq 10mΩ/sq VIA METALLIZATION 0.02mΩ cm TBD TBD Standard Panel Formats MATERIAL LTCC CERAMIC DIMENSION TOLERANCES PANEL SIZE(A) 120 mm (4.7inch) OUTER PANEL DIMENSION MAXIMUM QUADARNT SIZE (B) 60 mm (2.36inch) PATTER PITCH BOARDER ( C ) BOARDER ( C ) 4 mm 4 mm THICKNESS CAVIT STANDARD 0.50% 0.50% 10% 2% ADVANCED % 5% 1% CAMBER STANDARD 0.5% / ADVANCED 0.25%
3 THICKNESS AND SCORE LINE REQUIREMENTS Unit : um A B C DIAMOND DIAMOND SUBSTRATE SCRIBE LINE DEPTH SCRIBE LINE WIDTH THICKNESS GUIDELINES 0.5 C ~ 0.6 C < 50 um 200 ~ 3000 CASTELLATION SMT type packages with a side conductor stripe to facilitate inspection of the board assembly are produced using a castellation notch on the side of the part.
4 Exposed Conductor Layers A B C D E VIA HOLE DIAMETER VIA LANDING PAD DIAMETER TRACE SPACING VIA PITCH LANDING PAD TO TRACE SPACING unit um mil um mil um mil um mil um mil STANDARD F G G H H TRACE TO TRACE TO LANDING PAD LANDING PAD TRACE WIDTH PACKAGE CAVITY TO PACKAGE TO CAVITY EDGE EDGE EDGE EDGE unit um mil um mil um mil um mil um mil STANDARD ADVANCED ADVANCED * Next Stage: Trace Width 25um, Trace Spacing 25um & Via Hole Diameter 30um
5 Buried Conductor Layers A B C D E LANDING PAD VIA HOLE VIA LANDING TRACE VIA PITCH TO TRACE DIAMETER PAD DIAMETER SPACING SPACING unit um mil um mil um mil um mil um mil STANDARD ADVANCED F G G H H TRACE TO TRACE TO LANDING PAD LANDING PAD TRACE WIDTH PACKAGE CAVITY TO PACKAGE TO CAVITY EDGE EDGE EDGE EDGE unit um mil um mil um mil um mil um mil STANDARD ADVANCED
6 Ceramic Flip Chip VIA Technology All Dimensions Unit : um / mil Power/Ground A B C C D Plane VIAs VIA Hole Diameter VIA Capture PAD Isolation Gap with Via in Upper Layer Isolation Gap Without Via in Upper Layer Package Edge to Plane Edge STANDARD 200 / / / / / 16 ADVANCED 95 / / / 4 80 / / 12 Power/Ground Plane VIAs D E E F Cavity Edge To Plane Edge Package Edge to VIA Cavity Edge to VIA Solid Plane STANDARD 300 / / / / 4 ADVANCED 200 / / / 8 80 / 3
7 SMD LAYOUT NON-SOLDERMASK DEFINED SIZE (All Dimensions Unit : um / mil) A B C D E PAD LENGTH PAD SPACE MAXIMUM PAD WIDTH SOLDERMASK PULL-BACK * SOLDERMASK TO TRACE ** CHIP SIZE 2012 (0805) 930 / / / / / 4 CHIP SIZE 1508 (0603) 700 / / / / / 4 CHIP SIZE 1008 (0403) 325 / / / / / 4 CHIP SIZE 1005 (0402) 325 / / / / / 4 CHIP SIZE 0603 (0201) 275 / / / / / 4 CHIP SIZE 0402 (01005) 75 / / 4 SIZE (Alll Dimensions Unit : um / mil) F G H J K SOLDERMASK WEB TO *** PAD TO PACKAGE EDGE PAD TO DIE FLAG **** SMETAL TO METAL CHIP SIZE 2012 (0805) 150 / / / / / 3 CHIP SIZE 1508 (0603) 150 / / / / / 3 CHIP SIZE 1008 (0403) 150 / / / / / 3 CHIP SIZE 1005 (0402) 150 / / / / / 3 CHIP SIZE 0603 (0201) 150 / / / / / 3 CHIP SIZE 0402 (01005) 150 / / / / 3 * VIOLATING THIS GUIDELINE MAY RESULT IN YIELD HIT. ** UNLESS TRACE CAN BE EXPOSED BY DESIGN. *** IF TWO DIFFERENT SIZE S ARE NEXT TO EACH OTHER THEN AN AVERAGED "G" DIMENSION WILL BE USED. **** IF DIE HAS BONDING WIRES ON THE SIDE SEE PAGE xx (CASTELLATION). ***** soldering pad (SMT)design and testing is under developing,will be completed by Q2 end of 2014
8 SMD LAYOUT SOLDERMASK DEFINED SIZE (All Dimensions Unit : um / mil) A B C D E PAD LENGTH PAD SPACE MAXIMUM PAD WIDTH SOLDERMASK OVERLAY * METAL TO TRACE CHIP SIZE 2012 (0805) 930 / / / / 2 75 / 3 CHIP SIZE 1508 (0603) 700 / / / / 2 75 / 3 CHIP SIZE 1008 (0403) 325 / / / / 2 75 / 3 CHIP SIZE 1005 (0402) 325 / / / / 2 75 / 3 CHIP SIZE 0603 (0201) 275 / / / / 2 75 / 3 SIZE (All Dimensions Unit : um) F G H J K SOLDERMASK WEB TO ** PAD TO PACKAGE EDGE PAD TO DIE FLAG *** METAL TO METAL CHIP SIZE 2012 (0805) 150 / / / / / 3 CHIP SIZE 1508 (0603) 150 / / / / / 3 CHIP SIZE 1008 (0403) 150 / / / / / 3 CHIP SIZE 1005 (0402) 150 / / / / / 3 CHIP SIZE 0603 (0201) 150 / / / / / 3 * VIOLATING THIS GUIDELINE MAY RESULT IN YIELD HIT. *** IF TWO DIFFERENT SIZE S ARE NEXT TO EACH OTHER THEN AN AVERAGED "G" DIMENSION WILL BE USED. **** IF DIE HAS BONDING WIRES ON THE SIDE SEE PAGE xx (CASTELLATION).
9 SMD WIRE BONDING Wire Bonding Type HEIGHT (All Dimensions Unit : um / mil) DISTANCE (D1) FROM BOND FINGER TO (BONDING AWAY FROM ) DISTANCE (D2 ) FROM BOND FINGER TO (BONDING TOWARD ) DISTANCE (D3 ) FROM BOND FINGER TO 200 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / 22
10 DIE BONDING All Dimensions Unit :um/mil A A B C D E F Die Flag Die Flag Maximum to Bond Solder Mask Wire Finger Pullback Length Die Edge to Die Flag (Die Thickness < 100) Die Edge to Die Flag (Die Thickness > 100) Wire Separation On Stitch Bond Maximum Wire Angle STANDARD 100 / / / 6 75 / 3 28 / 1 75 / 3 45 Degrees
11 Wire Bonding Options All Dimensions Unit : um / mil A B C E Down Bond Die Edge to Length Die Flag Edge Down Bond Length Wirebond Pad Edge to VIA Pad Edge "D" Die Thickness < / / 10 Down Bond Length / 12 "D" Die Thickness > / / 10 Down Bond Length / 12 "D" Die Thickness > / / 10 Down Bond Length / 12
12 EMBEDDED S A Inductor Designs: space acceptable up to 100um B Layout Drawing Dimensions for Embedded Capacitors Capacitor plates, as large areas of conductors, are acceptable up to 5mm square. Adjacent capacitor plates at maximum size, must be separated by a space equal to the size of the capacitor plate. Maximum conductor coverage is 50% of substrate area. Capacitors are processed using standard screen printing techniques and fired directly onto any layer of the substrate. They may also be buried within or on top of multilayer structures. Electrodes must be of the same material. Typical dielectric thickness is 40 um(minimum). Capacitor tolerance is typically ± 30%. Design options are available to reduce tolerances.
13 C Layout Drawing Dimensions for Embedded Resistors Embedded resistors are available with fired tolerances of 30%, with good tracing to adjacent resistors. The following table is a list of available materials for buried resistors. Ink for Printing Ohms per Square Level R 1 50 Ω Level R Ω Level R 3 1K Ω Level R 4 10K Ω Level R 5 100K Ω All Dimension Unit : um / mil LENGTH MAXIMUM LENGTH WIDTH MAXIMUM WIDTH Overlap 10,000 / / 8 10,000 / / / 4 Standard resistor materials are made from glasses and metal oxides of ruthenium metal. Sheet resistivities are available from milliohms to gigaohms and can be combined on a single substrate. Standard trim tolerances are 10% through 1%, and in some cases to 0.5%. Large numbers of minimum size resistors on a substrate may limit the tolerance to 5% to 10% due to yield considerations. Typical Resistor Characteristics Sheet Resistivities (ohms/square) Range K 10K 100K 1M 10M TCR (PPM/C) Maximum ±300 ±300 ±300 ±300 ±300 ±300 ±300 ±300 Typical 100± ± ± ±200 0±200 0±200 0±200 0±200 Maximum Rated Power Dissipation (mw) Al2O3 Base AlN Base
14 Ceramic Flip Chip Via Technology ( All Dimensions Unit : um) All Dimension Unit : um / mil Die Size A A B B C D Flip Chip VIAs and PADs 1,000 um Top VIA Diameter Bottom VIA Diameter VIA Capture PAD Top VIA Capture Pad Bottom Bottom PAD With no VIA PAD Pitch STANDARD 125 / 5 75 / / / / / 9 ADVANCED 80 / 3 70 / / / 5 75 / / 8 Die Size Flip Chip VIAs and PADs 1,000 um A A B B C D Top VIA Diameter Bottom VIA Diameter VIA Capture PAD Top VIA Capture Pad Bottom Bottom PAD With no VIA PAD Pitch STANDARD 125 / 5 75 / / / / / 9 ADVANCED 80 / 3 70 / / / 5 75 / / 8 * LTCC flip chip metal for attaching die with copper pillar is under developing,will be completed by Q3 of 2014
15 FLIP CHIP DIE PLACEMENT A B C All Dimension DIE EDGE TO DIE EDGE TO DIE TO DIE Unit : um / mil PACKAGE EDGE PAD SPACING STANDARD 2000 / / / 120 ADVANCED 1500 / / / 100
16 LGA PADS NON-SOLDERMASK DEFINED All Dimension Unit : um / mil A B C D E F LGA PAD Pitch LGA PAD Size LGA PAD to Package Edge LGA Solder Mask Pull-Back LGA Solder Mask WEB LGA PAD to Ground Plane 500 / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / 10
17 LGA PADS SOLDERMASK DEFINED All Dimension Unit : um / mil A B C D E F LGA PAD Pitch LGA PAD Size LGA PAD to Package Edge LGA Solder Mask Over-Lay LGA Solder Mask WEB LGA PAD to Ground Plane 500 / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / / / / 4 75 / / / 10
18 BGA PADS NON-SOLDERMASK DEFINED All Dimension Unit : um / mil A B C D BGA PAD Pitch BGA PAD Size BGA Solder Mask Open Size BGA PAD to Package Edge 500 / / / / / / / / / / / / / / / / / / / / / / / / 8
19 BGA PADS SOLDERMASK DEFINED All Dimension Unit : um / mil A B C D BGA PAD Pitch BGA PAD Size BGA Solder Mask Open Size BGA PAD to Package Edge 500 / / / / / / / / / / / / / / / / / / / / / / / / 10
20 Encapsulation The minimum clearance from the top of the highest component or wire loop to the top of the encapsulation is 250 um minimum. When metal shields for EMI/RF requirements are part of the design, consult the design guidelines for shields. Future additions will include guidelines for layout design when using transfer molding as the method of encapsulation.
21 CAVITY PACKAGE DESIGN All Dimension Unit : um / mil A B C D E Shelf Bond Shelf Cavity Thickness Height Depth Base Thickness Die Edge to Cavity Edge STANDARD 400 / / 6 80 / / / 8 ADVANCED 300 / / 3 40 / / / 4 All Dimension Unit : um F G H J Die Bond Line Thickness Thickness Bond Shelf Width BGA/LGA to Cavity Edge STANDARD 500 / 20 TBD TBD 400 / 16 ADVANCED 300 / 12 TBD TBD 400 / 16 * Cavity to Cavity Edge : 300um / LTCC thickness 200um ** Cavity to Cavity Edge : 520um / LTCC thickness 600um
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