DESCRIPTION FEATURES. LT1166 Power Output Stage Automatic Bias System APPLICATIONS TYPICAL APPLICATION

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1 LT Power Output Stage Automatic Bias System FEATURES Set Class AB Bias Currents Eliminates Adjustments Eliminates Thermal Runaway of I Q Corrects for Device Mismatch Simplifies Heat Sinking Programmable Current Limit May Be Paralleled for Higher Current Small SO- or PDIP Package APPLICATIONS U Biasing Power MOSFETs High Voltage Amplifiers Shaker Table Amplifiers Audio Power Amplifiers DESCRIPTION U The LT is a bias generating system for controlling class AB output current in high powered amplifiers. When connected with external transistors, the circuit becomes a unity-gain voltage follower. The LT is ideally suited for driving power MOSFET devices because it eliminates all quiescent current adjustments and critical transistor matching. Multiple output stages using the LT can be paralleled to obtain higher output current. Thermal runaway of the quiescent point is eliminated because the bias system senses the current in each power transistor by using a small external sense resistor. A high speed regulator loop controls the amount of drive applied to each power device. The LT can be biased from a pair of resistors or current sources and because it operates on the drive voltage to the output transistors, it operates on any supply voltage., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION U MPS90.k.k R I TOP = ma SENSE LT N90 Ω I LIM SENSE I BOTTOM = ma R 00pF µf µf R V IRF0 R SENSE 0.Ω R SENSE 0.Ω IRF90 0µF Ω INPUT OUTPUT Unity Gain Buffer Amp Driving Ω Load 0V 0V MPS R N Ω 00pF V 0µF F0 TA0 Figure. Unity Gain Buffer with Current Limit

2 LT ABSOLUTE MAXIMUM RATINGS W W W Supply Current (Pin or Pin )... ma Differential Voltage (Pin to Pin )... ±V Output Short-Circuit Duration (Note )...Continuous Specified Temperature Range (Note )... 0 C to 0 C Operating Temperature Range... 0 C to C Storage Temperature Range... C to 0 C Junction Temperature (Note )... 0 C Lead Temperature (Soldering, 0 sec) C U PACKAGE/ORDER INFORMATION N PACKAGE -LEAD PDIP TOP VIEW SENSE SENSE S PACKAGE -LEAD PLASTIC SO T JMAX = 0 C, θ JA = 00 C/ W (N) T JMAX = 0 C, θ JA = 0 C/ W (S) U W U ORDER PART NUMBER LTCN LTCS S PART MARKING Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS Pin = V, Pin = V, Operating current ma and R IN = 0k, unless otherwise specified. PARAMETER CONDITIONS MIN TYP MAX UNITS Output Offset Voltage Operating Current ma to 0mA 0 0 mv Input Bias Current Operating Current ma to 0mA (Note ) 0 µa Input Resistance Operating Current ma to 0mA (Note ) MΩ V AB (Top) Measure Pin to Pin, No Load 0 mv V AB (Bottom) Measure Pin to Pin, No Load 0 mv Voltage Compliance Operating Current = 0mA (Notes, 9) ± ±0 V Current Compliance Operating Voltage = ±V ± ±0 ma Transconductance (Note ) gm CC Pin = V, Pin = V mho gm EE Pin = V, Pin = V mho gm CC0 Pin = 0V, Pin = 0V mho gm EE0 Pin = 0V, Pin = 0V mho PSRR CC (Note ) 9 db PSRR EE (Note ) 9 db Current Limit Voltage Operating Current ma to 0mA Pin Voltage to Pin.0.. V Pin Voltage to Pin.0.. V The denotes specifications which apply over the full operating temperature range. Note : External power devices may require heat sinking. Note : Commercial grade parts are designed to operate over the temperature range of 0 C to C but are neither tested nor guaranteed beyond 0 C to 0 C. Industrial grade parts specified and tested over 0 C and C are available on special request, consult factory. Note : T J calculated from the ambient temperature T A and the power dissipation P D according to the following formulas: LTCN: T J = T A (P D 00 C/W) LTCS: T J = T A (P D 0 C/W) Note : I TOP = I BOTTOM Note : The input resistance is typically MΩ when the loop is closed. When the loop is open (current limit) the input resistance drops to 00Ω referred to Pin. Note : Maximum T J can be exceeded with 0mA operating current and simultaneous 0V and 0V (0V total). Note : Apply ±00mV to Pin and measure current change in Pin and. Pin is grounded. Note : PSRR CC = gm CC gm CC0 gm CC PSRR EE = gm EE gm EE0 gm EE Note 9: For Linear Operation, Pin must not be less than V or more than 0V from Pin. Similarly, Pin must not be less than V or more than 0V from Pin.

3 LT TYPICAL PERFORMANCE CHARACTERISTICS U W Input Bias Current vs Current Source Mismatch Output Offset Voltage vs Current Source Mismatch Output Offset Voltage vs Temperature INPUT BIAS CURRENT (µa) I TOP = I BOTTOM = 0mA I TOP = I BOTTOM = ma OUTPUT OFFSET VOLTAGE (mv) I TOP = I BOTTOM = 0mA R IN = 0k R IN = k OUTPUT OFFSET VOLTAGE (mv) R L = I TOP = I BOTTOM = ma R IN =.k CURRENT SOURCE MISMATCH (%) I TOP AND I BOTTOM MISMATCH (ma) TEMPERATURE ( C) INPUT BIAS CURRENT (µa) Input Bias Current vs Temperature LT TPC0 R L = I TOP = I BOTTOM = ma R IN =.k TEMPERATURE ( C) LT TPC0 OUTPUT VOLTAGE SWING (V) 0 0 Output Voltage vs Input Voltage R IN =.k C = C = 00pF R L = 0Ω SEE FIGURE R TOP = R BOTTOM = I TOP = I BOTTOM = ma LT TPC INPUT VOLTAGE (V) LT TPC0 GAIN (db) Open-Loop Voltage Gain vs Frequency R L =0Ω V S = ±V R IN =.k I TOP = I BOTTOM = ma C = C = 00pF SEE FIGURE R L = LT TPC FREQUENCY (MHz) LT TPC0 Closed-Loop Voltage Gain vs Frequency Voltage Across Sense Resistors vs Temperature Current Limit Pin Voltage vs Temperature GAIN (db) 0 R L = R L =0Ω V S = ±V R IN =.k I TOP = I BOTTOM = ma C = C = 00pF SEE FIGURE FREQUENCY (MHz) VOLTAGE DROP ACROSS SENSE RESISTORS (mv) SENSE SENSE TEMPERATURE ( C) ILIM PIN VOLTAGE REFERENCED TO VOUT (V) PIN TO PIN PIN TO PIN = ±.V TEMPERATURE ( C) LT TPC0 LT TPC0 LT TPC09

4 LT TYPICAL PERFORMANCE CHARACTERISTICS U W INPUT TRANSCONDUCTANCE (mhos) Input Transconductance vs Supply Voltage C C C C C C gm CC = ±00mV R L = 0 R IN = 0 gm EE 9 0 SUPPLY VOLTAGE (V) LT TPC0 TOTAL HARMONIC DISTORTION (%) 0 0. Total Harmonic Distortion vs Frequency R L = 0Ω P O = W SEE FIGURE FREQUENCY (khz) LT TPC SENSE PIN VOLTAGE REFERENCED TO VOUT (mv) Sense Pin Voltage Referenced to vs Load Current R SENSE = SINKING SOURCING LOAD CURRENT (ma) LT TPC PIN FUNCTIONS U U U (Pin ): Pin establishes the top side drive voltage for the output transistors. Operating supply current enters Pin and a portion biases internal circuitry; Pin current should be greater than ma. Pin voltage is internally clamped to V with respect to and the pin current should be limited to ma maximum. (Pin ): Pin is the input to a unity gain buffer which drives (Pin ). During a fault condition (short circuit) the input impedance drops to 00Ω and the input current must be limited to ma or to limited to less than ±V. (Pin ): Pin of the LT is the output of a voltage control loop that maintains the output voltage at the input voltage. (Pin ): Pin establishes the bottom side drive voltage for the output transistors. Operating supply current exits this pin; Pin current should be greater than ma. Pin voltage is internally clamped to V with respect to and the pin current should be limited to ma maximum. SENSE (Pin ): The Sense pin voltage is established by the current control loop and it controls the output quiescent current in the bottom side power device. Limit the maximum differential voltage between Pin and Pin to ±V during fault conditions. I LIM (Pin ): The negative side current limit, limits the voltage at to during a negative fault condition. The maximum reverse voltage on Pin with respect to is V. I LIM (Pin ): The positive side current limit, limits the voltage at to during a positive fault condition. The maximum reverse voltage on Pin with respect to is V. SENSE (Pin ): The Sense pin voltage is established by the current control loop and it controls the output quiescent current in the top side power device. Limit the maximum differential voltage between Pin and Pin to ±V during fault conditions.

5 LT Overvoltage Protection The supplies (Pin ) and (Pin ) have clamp diodes that turn on when they exceed ±V. These diodes act as ESD protection and serve to protect the LT when used with large power MOS devices that produce high V GS voltage. Current into Pin or Pin should be limited to ±ma maximum. Multiplier Operation Figure shows the current multiplier circuit internal to the LT and how it works in conjunction with power output transistors. The supply voltages V T (top) and V B (bottom) of the LT are set by the required on voltage of the power devices. A reference current I REF sets a constant V BE and V BE. This voltage is across emitter base of Q9 and Q0 which are /0 the emitter area of Q and Q. The expression for this current multiplier is: V BE V BE = V BE9 V BE0 or in terms of current: (I C9 )(I C0 ) = (I REF ) /00 = Constant The product of I C9 and I C0 is constant. These currents are mirrored and set the voltage on the () inputs of a pair of internal op amps. The feedback of the op amps force the same voltage on the () inputs and these voltages then appear on the sense resistors in series with the power devices. The product of the two currents in the power devices is constant, as one increases the other decreases. The excellent logging nature of Q9 and Q0 allows this relation to hold over many decades in current. The total current in Q and Q is actually the sum of I REF and a small error current from the shunt regulator. During high output current conditions the error current from the regulator decreases. Current conducted by the regulator also decreases allowing V T or V B to increase by an amount needed to drive the power devices. Driving the Input Stage Figure shows the input transconductance stage of the LT that provides a way to drive V T and V B. When a positive voltage is applied to R IN, a small input current flows into R and the emitter of Q. This effect causes V O to follow within the gain error of the amplifier. The input current is then mirrored by Q/Q and current supplied to Q s collector is sourced by power device M. The signal current in Q s emitter is absorbed by external resistor R B and this causes V B to rise by the same amount I REF R T M V Q Q R T M V SHUNT REGULATOR Q 0 Q 0 I REF 0 Q9 Q0 V AB V AB Ω V O Ω C EXT R IN Q Q R R Q Q Ω R B V Figure. Constant Product Generator V O Ω Q Q M C EXT R B M V F0 F0 Figure. Input Stage Driving Gates

6 LT as. Similarly for V T, when positive voltage is applied to R IN, current that was flowing in R and Q is now supplied through R IN. This effect reduces the current in mirror Q/ Q. The reduced current has the effect of reducing the drop on R T, and V T rises to make V O track. The open-loop voltage gain V O /( V PIN ) can be increased by replacing R T and R B with current sources. The effect of this is to increase the voltage gain / from approximately 0. to (see Typical Performance Characteristics curves). The use of current sources instead of resistors greatly increases loop gain and this compensates for the nonlinearity of the output stage resulting in much lower distortion. Frequency Compensation and Stability The input transconductance is set by the input resistor R IN and the : current mirrors Q/Q and Q/Q. The resistors R and R are small compared to the value of R IN. Current in R IN appears times larger in Q or Q, which drive external compensation capacitors C EXT and C EXT. These two input signal paths appear in parallel to give an input transconductance of: g m = /R IN The gain bandwidth is: GBW = π(r IN )(C EXT ) Depending on the speed of the output devices, typical values are R IN =.k and C EXT = C EXT = 00pF giving a db bandwidth of.mhz (see Typical Performance Characteristics curves). To prevent instability it is important to provide good supply bypassing as shown in Figure. Large supply bypass capacitors (0µF) and short power leads can eliminate instabilities at these high current levels. The resistors (R and R) in series with the gates of the output devices stop oscillations in the 00MHz region as do the resistors R and R in Figure. Driving Capacitive Loads Ideally, amplifiers have enough phase margin that they don t oscillate but just slow down with capacitive loads. Practically, amplifiers that drive significant power require some isolation from heavy capacitive loads to prevent oscillation. This isolation is normally an inductor in series with the output of the amplifier. A µh inductor in parallel with a 0Ω resistor is sufficient for many applications. Setting Output AB Bias Current Setting the output AB quiescent current requires no adjustments. The internal op amps force V AB = ±0mV between each Sense (Pins and ) to the Output (Pin ). At quiescent levels the output current is set by: I AB = 0mV/R SENSE The LT does not require a heat sink or mounting on the heat sink for thermal tracking. The temperature coefficient of V AB is approximately 0.%/ C and is set by the junction temperature of the LT and not the temperature of the power transistors. Output Offset Voltage and Input Bias Current The output offset voltage is a function of the value of R IN and the mismatch between external current sources I TOP and I BOTTOM (see the Typical Performance Characteristics curves). Any error in I TOP and I BOTTOM match is reduced by the : input current mirror, but is multiplied by the input resistor R IN. Current Limit The voltage to activate the current limit is ±.V. The simplest way to protect the output transistors is to connect the Current Limit pins and to the Sense pins and. A current limit of.a can be set by using Ω sense resistors. To keep the current limit circuit from oscillating in hard limit, it is necessary to add an RC ( and µf) between the Sense pin and the as shown in Figure. The sense resistors can be tapped up or down to increase or decrease the current limit without changing AB bias current in the power transistors. Figure demonstrates

7 LT how tapping the sense resistors gives twice the limit current or one half the limit current. Foldback current limit can be added to the normal or square current limit by including two resistors (0k typical) from the power supplies to the pins as shown in Figure. With square current limit the maximum output current is independent of the voltage across the power R IN SENSE LT SENSE 0.Ω 0.Ω Ω Ω V ()( ) (/)( ) devices. Foldback limit simply makes the output current dependent on output voltage. This scheme puts dissipation limits on the output devices. The larger the voltage across the power device, the lower the available output current. This is represented in Figure, Output Voltage vs Output Current for the circuit of Figure. OUTPUT CURRENT (ma) SQUARE FOLDBACK FOLDBACK SQUARE OUTPUT VOLTAGE (V) LT F0 Figure. Output Current vs Output Voltage V F0 0mA 0k 0pF SENSE µf. LT µf SENSE Figure. Tapping Current Limit Resistors V IRFR0 0Ω ma 0Ω IRFR90 0pF 0mA 0k V F0 Figure. Unity Gain Buffer Amp with Foldback Current Limit Driving the Shunt Regulator It is possible to current drive the shunt regulator directly without driving the input transconductance stage. This has the advantage of higher speed and eliminates the need to compensate the g m stage. With Pin floating, the LT can be placed inside a feedback loop and driven through the biasing current sources. The input transconductance stage remains biased but has no effect on circuit operation. The R L in Figure is used to modulate the op amp supply current with input signal. This op amp functions as a V-to-I with the supply leads acting as current source outputs. The load resistor and the positive input of the op amp are connected to the output of the LT for feedback to set A V = V/V. The capacitor C F eliminates output V OS due to mismatch between I TOP and I BOTTOM, and it also forms a pole at DC and a zero at /R F C F. The zero frequency is selected to give a V/V gain in the op amp before the phase of the MOSFETs degenerate the stability of the loop.

8 LT APPLICATION CIRCUITS Bipolar Buffer Similar to the unity gain buffer in Figure, the LT can be used to bias bipolar transistors as shown in Figure. The minimum operating voltage for the LT is ±V, so it is necessary to bias the part with adequate voltage from the output stage. The simplest way to do this is to use Darlington drivers and series diodes. There are no thermal tracking circuits or adjustments necessary and the LT does not need to be mounted on the heat sink with the power devices. R TOP and R BOTTOM can be used to replace I TOP and I BOTTOM ; see Typical Characteristics curves. V N90 Ω N90 R TOP 0µF V 00pF I TOP = ma N C F R F R IN R L I T SENSE I LIM LT I LIM SENSE M Ω Ω.k.k SENSE LT 00pF SENSE I BOT = ma IN00 0Ω 0Ω IN00 N90 TIP9 Ω Ω TIP0 0Ω I B M V N N Ω R BOTTOM 0µF F0 F0 V Figure. Current Source Drive Figure. Bipolar Buffer Amp

9 LT Adding Voltage Gain The circuit in Figure 9 adds voltage gain to the circuit in Figure. At low frequency the LT is in the feedback loop of the LT0 so the gain error and the V OS are reduced and the closed-loop gain is 0V/V. V LT00-. 0Ω 0µF MPS90. 00pF ma IRF0 LT0 C F 00pF 0.µF 9k LT µf V T SENSE I LIM µf SENSE 0.µF V BOT ma. 00pF MPS 0.Ω 0.Ω IRF90 Ω VOUT LT00. 0Ω 909Ω V 0µF F09 00pF Figure 9. Power Op Amp A V = 0 INPUT 0V INPUT 0V OUTPUT 0V OUTPUT 0V F0 F Figure 0. Power Amp Driving Ω Load Figure. Power Amp at A Current Limit 9

10 LT A Adjustable Voltage Reference The circuit in Figure uses the LT in a feedback loop with the LT to make a voltage reference with an attitude. This V reference can drive ±A and maintain 0.% tolerance at the output. If other output voltages are desired, external resistors can be used instead of the LT s internal k resistors. HIGH VOLTAGE APPLICATION CIRCUITS In order to use op amps in high voltage applications it is necessary to use techniques that confine the amplifier s common mode voltage to its output. The following applications utilize amplifiers operating in suspended-supply operation (Figure ). See Linear Technology Magazine Volume IV Number for a discussion of suspended supplies. The gain setting resistors used in suspendedsupply operation must be tight tolerance or the gain will be wrong. For example: with % resistors the gain can be as far off as %, but with 0.% resistors that error is cut to less than %. Using the values shown in Figure, the formula for computing the gain is: R(R9 R0) A V = =. (R R9) (R R0) V V IRF0 SENSE R TOP k k R MID REF.V GND/SENSE V LT COL V GND FORCE k LT I LIM I LIM SENSE µf µf Ω Ω IRF90 0µF Figure. ±A, V Voltage Reference F R IN R 0k OUT R9 9. R0 F Figure. Op Amp in Suspended-Supply Operation 0

11 Parallel Operation Parallel operation is an effective way to get more output power by connecting multiple power drivers. All that is required is a small ballast resistor to ensure current sharing between the drivers and an isolation inductor to keep the drivers apart at high frequency. In Figure one power slice can deliver ±A at 00V PK, or 00W RMS into Ω. The addition of another slice boosts the power output to 00W RMS into Ω and the addition of two or more drivers theoretically raises the power output to 00W RMS into Ω. Due to IR loss across the sense 0V AC V LT00-..V.V LT00-. V ~ ~ DIODE BRIDGE R 90Ω R R 90Ω R9* 9. C 0.µF R* 0k C 000µF V C 000µF V 0µF 0µF R0* LT0 R* 9 R 00Ω C 00pF V C 0µF V C 0µF V V 0µH LT resistors, the FET R ON resistance at 0A, and some sagging of the power supply, the circuit of Figure actually delivers 0W RMS into Ω. Performance photos and a THD vs frequency plot are included in Figure through. Frequency compensation is provided by the k input resistor, 0µH inductor and the nf compensation capacitors. The common node in the auxiliary power supplies is connected to amplifier output to generate the floating ±V supplies. FB FB R IN k nf SENSE LT SENSE nf R N90 N90 R POWER SLICE POWER SLICE R C µf C µf R R R 00V 00V IRF0 R 0.Ω R 0.Ω IRF90 R 0.Ω L** 0.µH Ω L***.µH 0A FAST-BLOW AUXILARY SUPPLIES F *0.% RESISTORS ** TURNS T- (MICROMETALS) *** TURNS T0- (MICROMETALS) Figure. 0W Shaker Table Amplifier

12 LT F Figure. 0.% THD at 0kHz, P O = 0W, R L = Ω TOTAL HARMONIC DISTORTION (%).0 0. P O = 0W R L = Ω F Figure. khz Square-Wave, C L = µf k FREQUENCY (Hz) 00k Figure. Clipping at Hz, R L = Ω F Figure. THD vs Frequency LT F 00W Audio Power Amplifier The details of a low distortion audio amplifier are shown in Figure 9. The LT0, designated U, was chosen for its good CMRR and is operated in suspended-supply mode at a closed-loop gain of.v/v. The ±V supplies of U are effectively bootstrapped by the output at point D and are generated as shown in Figure. A V P-P signal at will cause an 0V PP output at point A. Resistors to 0 set the gain of.v/v of U, while C compensates for the additional pole generated by the CMRR of U. The rest of the circuit (point A to point D) is an ultralow distortion unity-gain buffer. The main component in the unity-gain buffer is U (LT). This controller performs two important functions, first it modifies the DC voltage between the gates of M and M by keeping the product of the voltage across R0 and R constant. Its secondary role is to perform current limit, protecting M and M during short circuit. The function of U is to drive the gates of M and M. This amplifier s real output is not point C as it appears, but rather the Power Supply pins. Current through R is used to modulate the supply current and thus provide drive to and. Because the output impedance of U (through its supply pins) is very high, it is not able to drive the capacitive inputs of M and M with the combination of speed and accuracy needed to have very low distortion at 0kHz. The purposes of U are to drive the gate capacitance of M and M through its low output impedance and to reduce the nonlinearty of the M and M transconductance. R, C set a frequency above which U no longer looks after U and U, but just looks after itself as its gain goes through unity. R/R and C/C are compensation components for the CMRR feedthough. Curves showing the performance of the amplifier are shown in Figures 0 through.

13 LT LT009-. R U LT0 LT009-. VIN R 00Ω SENSE ILIM U LT VOUT ILIM SENSE R 00Ω R R9 C0 µf C µf R M IRF0 R0 0.Ω R 0.Ω M IRF90 C 0.µF L µh R 0Ω C µf F C 0pF R* 0k R* U LT0 R0* R9* 9.k * 0.% RESISTORS ** SEE POWER SUPPLY OF FIGURE A U LT R R C 0pF C 0pF C 0pF B R.k R N90 R 0k R.k C 00pF N90 R Figure 9. 00W Audio Amplifier C µf R 0Ω C R 0Ω R 0Ω C µf C9 0.0µF C 0.0µF V** V** R 0V 0V C 0.µF D C µf

14 LT R L = Ω f = khz Figure 0. Square Wave Response Into Ω F0 F R L = Ω f = 0kHz Figure. 00W 0kHz Sine Wave and Its Distortion TOTAL HARMONIC DISTORTION (%) R L = Ω POWER OUT = 00W k FREQUENCY (Hz) LT F 00k Figure. THD vs Frequency

15 LT W SI PLIFIED SCHEMATIC W Q Q I REF SENSE Q Q R 00Ω R 00Ω Q Q SHUNT REGULATOR Q 0 Q 0 I REF 0 Q9 Q0 V AB V AB SENSE Q Q SS PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. N Package -Lead PDIP (Narrow 0.00) (LTC DWG # 0-0-0) 0.00* (0.0) MAX 0. ± 0.0* (. ± 0.) (.0.) (..) 0.0 ± 0.00 (.0 ± 0.) (0.9 0.) ( ) 0.0 (.) TYP 0.00 (0.) MIN 0.00 ± 0.00 (.0 ± 0.) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.00 INCH (0.mm) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0. (.) MIN 0.0 ± 0.00 (0. ± 0.0) 0.0 (0.0) MIN N 09

16 LT PACKAGE DESCRIPTION U Dimensions in inches (millimeters) unless otherwise noted. S Package -Lead Plastic Small Outline (Narrow 0.0) (LTC DWG # 0-0-0) * (.0.00) (.9.9) ** (.0.9) (0.0 0.) (0. 0.0) 0 TYP (..) (0.0 0.) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.00" (0.mm) PER SIDE (0. 0.) 0.00 (.0) BSC SO 09 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT00 Fast ±0mA Power Buffer Ideal for Boosting Op Amp Output Current LT0 Off-Line Switching Regulator Generate High Power Supplies LT0 0mA/0MHz Current Feedback Amplifier C-Load TM Op Amp with Shutdown and 900V/µs Slew Rate LT0 A/0MHz Current Feedback Amplifier C-Load Op Amp with Shutdown and 00V/µs Slew Rate LT0A 0A High Efficiency Switching Regulator Use as Battery Boost Converter LT0 0MHz, 00V/µs Op Amp ±V, Ideal for Driving Capacitive Loads LT 0MHz, 00V/µs Op Amp ±V, Very High Speed, C-Load C-Load is a registered trademark of Linear Technology Linear Technology Corporation LT/GP 9 K PRINTED IN USA 0 McCarthy Blvd., Milpitas, CA 90- (0) -900 FAX: (0) -00 TELEX: 99-9 LINEAR TECHNOLOGY CORPORATION 99

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