Secure Virtualization on Single- and Multi-core ARM Processors

Transcription

1 Secure Virtualization on Single- and Multi-core ARM Processors Brad Suessmith Senior VP & GM TRANGO Virtual Processors John Goodacre ARM Multiprocessing Program Manager ARM Limited

2 Agenda Company and market overview Introduction to virtualization Single-core systems Technical overview Use cases Multi-core systems Technical overview Use cases ARMv7MP virtualization enhancements Summary

3 TRANGO Overview TRANGO Company Headquartered in Grenoble, France Sales and support offices in US, Europe, and Japan Technology created by former CPU designer TRANGO Hypervisor Secure virtualization IP for SoC vendors and OEMs Support ARMv4, ARMv5, ARMv6 architectures Secure Execution of multiple Operating Systems and lications on single- and multi-core platforms ELSYS Design Holdings SoC hardware and software design services 35M annual revenue 500 engineers

4 Target Markets Wireless Handset Point of Sales Terminal Security GPL enabler Real-time capability BOM reduction Complex software enabler BOM reduction Maintain security Faster certification GPL enabler Network Equipment Consumer Electronics Automotive Infotainment Load balancing Quality of service Device management enabler Software re-use Security GPL enabler BOM reduction Complex software enabler Real-time capability Complex software enabler Increase revenues, add new product features with faster time-to-market and lower costs

6 Typical Heterogenous System Operating System RTOS Security app Certified app CPU CORE CPU CORE CPU CORE CPU CORE Memory Memory Memory Memory Peripherals Peripherals Peripherals Peripherals High cost: development, validation, silicon area Long time to market

7 Heterogenous SoC with Virtualization Operating System RTOS Security app Certified app TRANGO Hypervisor CPU CORE Memory Peripherals Availability of high-performance ARM CPUs enables consolidation of functions Decreased development, validation, silicon area, time to market

8 Emulation vs. Virtualization Emulation Full-Virtualization Paravirtualization Ported OS Native / unmodified OS Operating System Operating System running on a emulated ISA RTOS Operating System Security app RTOS Full Virtualization Layer TRANGO Hypervisor CPU CORE CPU CORE Emulation Layer Memory Memory CPU CORE ISA Peripherals Peripherals Emulate ISA Execute non-native OS & apps Execute multiple unmodified OS s on single CPU High overhead & large memory footprint Suitable for servers/desktops Security app Small overhead & memory footprint Execute multiple ported OS s on single CPU Real-time performance Best fit for embedded applications

9 Terminology Hypervisor Coined by IBM Also known as a Virtual Machine Monitor VMM: Virtual Machine Monitor VM: Virtual Machine Container or sandbox that guest OS and applications execute in Not directly related to Java JVM VPU: Virtual Processor Unit TRANGO term for guest OS view of virtual machine VM/OS VM/OS VM/OS VM VM VM VMM/Hypervisor Hardware

11 Technical Overview Hard Real-Time Multimedia Open sofware Security/ReliabilityCritical Functions TRANGO Virtual User Mode TRANGO Hypervisor Secure Virtualization Design inspired by RISC Virtual Machine isolation Run any OS, RTOS, application GPL and open-source license isolation Software CPU Kernel mode Hardware Secured RTOS Secured TRANGO Virtual Kernel Mode Secured Software CPU User Mode Open OS Linux Windows CE TRANGO Hypervisor ARM CPU CORE HARDWARE PERIPHERALS ARM CPUs ARM9/ARM10/ARM11 families Multi-core MPU or MMU required! Features 25-30KB code size < 2% performance overhead User application binary compatibility No emulation Paravirtualization

12 VM VPRs R/W RO CPU Kernel Mode CPU User Mode Hypervisor ISA Interrupts Hypercalls Exceptions Hypervisor Privileged Operations Interrupts Exceptions Hardware User Instructions

13 Security Architecture SW Privileged Mode Virtual Kernel Mode Virtual User Mode Virtual Kernel Mode MMU barrier Virtual User Mode MMU barrier SW Unprivileged Mode Strongly Partitioned Spaces Virtual User Mode Virtual Kernel Mode Privileged/Unprivileged Barrier TRANGO Hypervisor (25-30KB) Only TRANGO Hypervisor has access to CPU privileged mechanisms (mode, MMU...) Virtual Machine isolation ensured by the MMU/MPU & managed by the Hypervisor All events (interrupts, exceptions) are trapped by the Hypervisor

14 TRANGO Leverages TrustZoneTM Normal Secure User GSM Stack Operating System Priviliged Monitor TRANGO Hypervisor operates in Monitor Mode Security critical VMs run on-chip Protection against hardware attacks Control of AMBATM AXI S/NS bit Normal VMs run off-chip Privileged mode not used STIP

15 Eclipse Tools Suite Features: Intuitive and user friendly graphical interface VM development project System integration project Integrated project builders Shared network connection to boards Remote launch Remote Virtual Machine consoles Real-time system monitoring JTAG-like secure debug Command line interface option Flexible development framework

17 Security...there are serious problems with the design and implementation of security on the iphone. The most glaring is that all processes of interest run with administrative privileges. This implies that a compromise of any application gives an attacker full access to the device. Security Evaluation of le s iphone. White paper by Charlie Miller, Jake Honoroff, and Joshua Mason from Independent Security Evaluators July 19, 2007

18 Proposed Secure iphone Architecture Security Critical Functions Multimedia Open Software TRANGO Virtual User Mode Quick Time Safari Web Browser Software CPU Kernel Mode Hardware Voic itunes Media Keys Contacts TRANGO Virtual Kernel Mode FairPlay DRM Software CPU User Mode TRANGO Hypervisor ARM CORE HARDWARE PERIPHERALS OS X

19 Basic Single-Core Wireless Smartphone Today's Smartphone Telecom Telecom Stack Stack CPU Core Telecom Peripherals Smartphone with TRANGO lication Stack CPU Core USB Telecom Telecom Stack Stack TRANGO HYPERVISOR CPU Core Camera... lication Stack Telecom Peripherals Camera USB... Bill of materials reduction with use of a single core Integration of standard Rich OS (Windows Mobile, Symbian, Linux, etc.) Legacy software re-use Robust device platform architecture with HW resource partitioning

20 Advanced Single-core Smartphone Today's Smartphone Telecom Telecom Stack Stack CPU Core Telecom Peripherals Open OS CPU Core USB Camera... Smartphone with TRANGO Telecom Telecom Stack Stack Open OS Security Stack TRANGO HYPERVISOR CPU Core Telecom Peripherals USB Camera... Key Crypto Isolated security stack Secure deployment of new services: DRM, crypto, e-commerce, updates... Scalable over full spectrum of wireless handsets and services

21 NTT DoCoMo: OSTI Specification Standard Handset Features Customized Features Always-on and Highly Reliable Environments Open Environment Environment #1: Core services proprietary code Critical code for security app (DRM...) Environment #2: Build on Operator OS User personal data Operator services Enterprise/User OS Enterprise managed environment Enterprise business applications User personalized game software Secure core services OEM/Operator Enterprise OS / OS Open OS TRANGO Hypervisor lication processor HW peripherals Improved Performance: 1,000,000 times faster than OS switching (switch time is 2μs vs 2s) Better CPU optimization and power management compared to a dual-core SoC Scalable security Reduce Architecture Associated Costs: BOM reduction, e.g. silicon area Development and validation

22 Point-of-Sale Terminals Dual-core/chip System Single-core System with TRANGO EMV lication EMV lication PCI-PED lication lication CPU Security CPU Critical HW and SW for PCI-PED Certification PCI-PED lication TRANGO HYPERVISOR Architecture Certification process Dual-Core/Chip E.g. ARM7 + ARM9 Single-Core with TRANGO E.g. ARM9 Equivalent certification process Additional features Modular and scalable architecture Cost 30% BOM reduction Keypad LCD Ethernet UART (USB)... Smart Card Keypad LCD Ethernet UART (USB)... Smart Card CPU Core

23 GPL Code Isolation GPL constraints: GPL-isolated Proprietary SW Player... GPL requirements: Deliver source code Provide update capability Proprietary s&drivers HARDWARE PERIPHERALS v3: Provide way to update and reflash applications in product Enable execution of Linux in a separated environment, TRANGO: TRANGO Hypervisor CPU CORE v2: Disclosure of Linux-based product source code (Linux kernel, drivers and modules) Protect proprietary IP & critical product features Secure GPL-based product business models Ensure compliance with GPL license and GPL spirit Continue to benefit from open-source software

24 Migration from Legacy OS Binary Compatibility for lications Validated legacy OS Re-use Isolated Proprietary Code from GPL Market Standard OS Integration Legacy OS Standard / commercial OS TRANGO Hypervisor CPU CORE HW peripherals Reuse legacy code & ensure continuity with existing services Reduce migration costs to new SMP OS

25 Software Packaging SoC Manufacturer Basic SW platform Drivers Telecom stack BSP OEM / ODM Payment, broadcast, DRM, specialized services... Operator A packaged system solution provides benefits across the whole value chain: Modularity Cost reduction Easier S&M Secure Operator Services Rich OS Linux Windows CE Symbian TRANGO Hypervisor CPU CORE Peripherals Protection of proprietary software Increased profits Legacy Drivers

27 Multi-Core Technical Overview Virtual Kernel mode Firmware update Software CPU User mode VPU A Software CPU Kernel mode Hardware VPU A SMP OS VPU B VPU D SMP OS VPU C VPU B Monitoring / Secure Virtual User mode VPU D VPU E VPU C VPU E TRANGO #1 TRANGO #2 ARM CORE #1 ARM CORE #2 HARDWARE PERIPHERALS VPU F VPU F

28 Multi-core Hypervisor Detail Single-core hypervisors + comms: One TRANGO hypervisor per CPU core Virtual User mode Enables hardware and peripheral partitioning Virtual Kernel mode Software CPU Kernel mode SMP OS SMP OS TRANGO Hypervisor RISC CPU MULTI-CORES Monitoring / Secure Firmware Update Software CPU User mode Provide multi-vpu architecture, capable of running multi-core (SMP) Operating Systems Hardware HARDWARE PERIPHERALS Same hypervisor properties Same validation, reliability and predictability Virtual Processing Unit VPU A Software CPU Kernel mode VPU B VPU C VPU D VPU E TRANGO TRANGO ARM CORE ARM CORE Hardware HARDWARE PERIPHERALS VPU F

30 Basic Multi-core System Proprietary lication Firmware Update RTOS Virtualization layer ARM CORE #1 ARM CORE #2 ARM CORE #3 HARDWARE PERIPHERALS One execution environment per core Under-utilized CPU core resources ARM CORE #4

31 Hypervisor-enabled Multi-core System (1) SMP SMP RTOS Proprietary lication Firmware Update TRANGO #1 TRANGO #2 TRANGO #3 TRANGO #4 ARM CORE #1 ARM CORE #2 ARM CORE #3 ARM CORE #4 HARDWARE PERIPHERALS Support of SMP OS and RTOS CPU core resource sharing Dynamic allocation of CPU resources Optimal load balancing

32 Hypervisor-enabled Multi-core System (2) VPU A VPU A Proprietary lication Firmware Update SMP SMP RTOS VPU B VPU B VPU C VPU C VPU D VPU D VPU E VPU E VPU F VPU F VPU G VPU G TRANGO #1 TRANGO #2 TRANGO #3 TRANGO #4 ARM CORE #1 ARM CORE #2 ARM CORE #3 ARM CORE #4 HARDWARE PERIPHERALS One TRANGO Hypervisor per core Each Hypervisor can create multiple virtual processors Execution Environment can share resources from different CPU cores

33 Hypervisor-enabled Multi-core system (3) VPU A SMP SMP RTOS VPU B VPU C VPU D Proprietary lication Firmware Update VPU E VPU G Switched off core VPU A VPU B VPU C VPU D VPU E VPU G TRANGO #1 TRANGO #2 TRANGO #3 TRANGO #4 ARM CORE #1 ARM CORE #2 ARM CORE #3 ARM CORE #4 HARDWARE PERIPHERALS Ability to switch off core CPU resources dynamically allocated according to Execution Environment requirements

34 Hypervisor-enabled Multi-core System (4) VPU A Proprietary lication Firmware Update SMP SMP RTOS VPU B VPU D VPU G Switched off cores VPU A VPU B VPU D VPU G TRANGO #1 TRANGO #2 TRANGO #3 TRANGO #4 ARM CORE #1 ARM CORE #2 ARM CORE #3 ARM CORE #4 HARDWARE PERIPHERALS Ability to migrate all Execution Environments to one core CPU resources dynamically allocated according to Execution Environment requirements Large power savings

35 Silent Linux Health Monitor Multi-core: High RAS Active Linux TRANGO Hypervisor ARM CORE ARM CORE ARM CORE ARM CORE HARDWARE PERIPHERALS Redundancy of OS s on the same hardware If Active Linux fails, Health Monitor activates Silent Linux On-the-fly updates with very low down time: Health Monitor updates Silent Linux in the background Then switches Active Linux/Silent Linux

37 Paravirtualization Enhancements to the ARMv7 Architecture John Goodacre, Program Manager, Multiprocessing, ARM Ltd 2nd October 2007

38 ARM Multicore Technology ARMv7 is the instruction set architecture (ISA) common to the ARM Cortex processors ARMv7 MP Extensions for next generation multicore processors Hardware cache coherence Enhanced communication Hardware processor coherence Multicore paravirtualization Targeting both increased processing efficiency and software simplification

39 ARM TrustZone and GIC Architectures Previously extended the ARM architecture to include additional privilege levels for the execution of an additional OS within the secured software domain Along with ARMv7MP the architecture has been further extended to manage and secure processor interrupts between the normal and secured software domains Known as the ARM Generic Interrupt Controller ( GIC ) Architecture Together, a TrustZone and GIC enabled ARMv7MP processor can: Restrict and control interrupts between the two software domains Partition and control access to system resource between the normal/secure domains Host management software within the secured domain without altering the normal OS Interrupts GIC provides an architected way to isolate and control which software domain receives which interrupts GIC normal/secure routing TrustZone adds a second OS context to allow trusted programs and data to be safely separated from the open operating system and applications Normal domain Secure domain

40 ARMv7MP: Improved Paravirtualization Today s Paravirtualization solutions Provide the ability to run multiple independent OS/RTOS on a single processor Requires a notable modification of a OS port to appropriately defer all privileged operations to a virtual machine manager (VMM) managing processor resource sharing ARMv7MP processors ARM TrustZone Architecture Enable concurrent execution of multiple paravirtualized operating systems Providing improved real-time response and dynamic load balancing Allows the open OS to maintain their User and Privilege states and run the VMM in the privilege contexts of the secured software domain Provides an AMBA architecture mechanism to signal TrustZone context accesses to peripherals and any system based memory protection units Cache state is maintained and secured between the open and TrustZone OS context during virtualization traps and request forwarding ARM GIC Architecture Allows the VMM to manage and arbitrate access to drivers for each open OS Together providing an accelerated and simplified paravirtualization solution

41 Conclusions The ARMv7 MP extensions set to further enhance ARM multicore processors Hardware support for Processor Coherence Extending L1 cache coherence to system accelerators Enhanced support for OS paravirtualization Increasing performance scalability and further reducing the power associated with maintaining SMP ARMv7: The ISA architecture of the ARM Cortex processors

43 Summary Consolidation of multiple CPU cores into one Partitioning of execution environments Improved security GPL code isolation Improved software packaging Multiprocessor systems Reduced cost Improved load-balancing & CPU utilization Increased RAS Power savings through dynamic VM allocation ARM adding architectural hardware support Improve performance Minimize guest OS modifications