Paolo Maistri. September 8, Personal Information 2. Education and Studies 2. Academic Activities and Affiliations 3

Transcription

1 CURRICULUM VITAE ET STUDIORUM Paolo Maistri September 8, 2008 TABLE OF CONTENTS Personal Information 2 Education and Studies 2 Academic Activities and Affiliations 3 Teaching Activities 4 Teaching Assistance Other Teaching Activities Scientific Activities 5 Peerreviews Oral Presentations ConferencePartecipations Publications 7 International Journals International ConferenceProceedings Theses Book Chapters

2 PERSONAL INFORMATION First Name: Paolo Last Name: Maistri Birth date: June 4th, 1977 Birth place: Milano, Italy Citizenship: Italian Work Address TIMA Laboratory 46, avenue Félix Viallet F Grenoble, Francia Phone: +33(0) Fax: +33(0) Personal Address 38, avenue Félix Viallet F Grenoble, Francia Mobile: +33(0) Languages Italian: native English: fluent French: medium EDUCATION AND STUDIES 07/1995 First Certificate in English (FCE), at Oxford School, Verona, Italy; final grade: B. 05/1999 Test of English as a Foreign Language (TOEFL), at Politecnico di Milano, Milano, Italy; final grade: 263/ / /2001 Master of Science in Computer Science and Electrical Engineering at the University of Illinois at Chicago(UIC), Chicago(IL), USA. Thesis title: Algorithm Analysis for Elliptic Curve Cryptography. Advisor: Prof. V. Piuri. Summary: This work deals with the public-key Elliptic Curve Cryptosystems (ECCs) and evaluates the performance tradeoff between a dedicated unit and an external cryptographic accelerator, connected by means of a dedicated bus. The model is developed at the architecture level. 09/ /2001 Degree in Computer Engineering at Politecnico di Milano, Milano, Italy; final grade: 100/100. Thesis title: Algorithm Analysis for Elliptic Curve Cryptography. Advisor: Prof. V. Piuri. Reviewer: Prof. L. Breveglieri. 2

3 Summary: This work deals with the use of alternative coordinate systems for Elliptic Curves, in particular the Hessian and Jacobian coordinate systems. These were selected to avoid power attacks against ECC. A software implementation (in C language) was developed to compare the performance with respect to affine and homogeneous systems. 03/ /2006 PhD in Information Technology at the Dipartimento di Elettronica e Informazione(Department of Electronics and Computer Science) of Politecnico di Milano, Milano, Italy; final grade: B. Thesis title: Cryptographic Algorithms and Architectures and their Connections with Errors and Reliability. Advisor: Prof. L. Breveglieri. Reviewer: Prof. R. Leveugle(TIMA Laboratory, Grenoble, France). Jury: Prof. Mandrioli Dino, Prof. Blanchini Franco, Prof. Ciaccia Paolo, Prof. Duval Erik. Summary: In this work, cryptographic algorithms and architecture are extended with error detection capabilities by means of codes, to counteract data corruption and to protect against fault attacks. A taxonomy of the main results in Differential Fault Analysis is given, focusinginthelatestfaultattacksagainstaesandrsa.hence,acomplete model is developed for the AES encryption algorithm to describe the error propagation [B15][B17]; an error detection mechanism, based onparitycode,hasbeendesigned[a3]andthenimplementedintwo sample architectures. Overheads and coverage rate were evaluated on VHDL and C code, respectively, and compared to most recent solution currently published in the literature [B10][B11]. The approach was then generalized to symmetric block ciphers and some software models (DES, RC5, IDEA) were implemented to validate the conclusions about suggested code, frequency of checkpoint, redundancy level[b12][b13]. A fault detection mechanism was also implemented in an RSA architecture, which can be particularly exposed to fault attacks. A software model was implemented to evaluate the error coverage of the code, while a VHDL design was developed to evaluate theoverheadsinterms of areaandlatency [B7]. ACADEMIC ACTIVITIES AND AFFILIATIONS 01/ /2002 Contract researcher at the Dipartimento di Elettronica e Informazione of Politecnico di Milano, Milano, Italy. 03/ /2003 Research grant in the European project MEDEA+ CryptoSoc (MEDEA Label A304), at the Dipartimento di Elettronica e Informazione of Politecnico di Milano, Milano, Italy. 03/ /2006 Contract researcher in the Italian project FIRB N. RBNE0193K5 MAIS Multichannel Adaptive Information Systems at the Dipartimento di Elettronica e Informazione of Politecnico di Milano, Milano, Italy. 04/ /2006 Contract researcher at the Dipartimento di Elettronica e Informazione of Politecnico di Milano, Milano, Italy. 06/ /2008 Post-Doc researcher at the TIMA Laboratory, Grenoble, France. 3

4 TEACHING ACTIVITIES TEACHING ASSISTANCE 03/ /2003 Teaching assistance in Informatica II (Computer Science II) held by Prof.ssa Milano, Italy (40 hours). 09/ /2004 Teaching assistance in Metodi e Tecnologie per il Trattamento delle Immagini (Methods and Technologies for Image Processing) held by Prof. R. Negrini for the degree in Computer Engineering, Politecnico di Milano, Milano, Italy (20 hours). 03/ /2004 Teaching assistance in Informatica II (Computer Science II) held by Prof.ssa Milano, Italy (40 hours). 09/ /2005 Teaching assistance in Metodi e Tecnologie per il Trattamento delle Immagini (Methods and Technologies for Image Processing) held by Prof. R. Negrini for the degree in Computer Engineering, Politecnico di Milano, Milano, Italy (20 hours). 09/ /2005 Teaching assistance in Reti Logiche A (Digital Design) held by Prof.ssa Milano, Italy (20 hours). 03/ /2005 Teaching assistance in Informatica II (Computer Science II) held by Prof.ssa Milano, Italy (40 hours). 09/ /2006 Teaching assistance in Reti Logiche A (Digital Design) held by Prof.ssa Milano, Italy (20 hours). 03/ /2006 Teaching assistance in Informatica II (Computer Science II) held by Prof.ssa Milano, Italy (40 hours) /2008 Teaching assistance in Hardware and embedded systems held by Prof. Régis Leveugle for the Master M2 Crypto, Institut Polytechnique Grenoble, Grenoble, France(20 hours). OTHER TEACHING ACTIVITIES 03/ /2002 Assistant for Computer Laboratory for Informatica II held by Prof. Luca Breveglieri for the degree in Automation Engineering at Politecnico di Milano, Milano, Italy. 09/ /2003 Computer Laboratory for Informatica I held by Prof. Luca Breveglieri for the degree in Automation Engineering at Politecnico di Milano, Milano, Italy. 09/ /2004 Computer Laboratory for Informatica I held by Prof. Luca Breveglieri for the degree in Automation Engineering at Politecnico di Milano, Milano, Italy. 4

5 SCIENTIFIC ACTIVITIES PEER REVIEWS 2008 IEEE International Conference on Circuits and Systems for Communications IEEE Transaction on Computers Workshop on Fault Diagnosis and Tolerance in Cryptography IET Circuits, Devices & Systems International Conference on Design, Automation and Test in Europe(DATE) International Conference on Application-Specific Systems, Architectures and Processors (ASAP). ORAL PRESENTATIONS 07/2002 On the Propagation of Faults and their Detection in a Hardware Implementation of the Advanced Encryption Standard at the International Conference on Application-Specific Systems, Architectures and Processors, San José(CA), USA. 06/2003 Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm at the International Conference on Application-Specific Systems, Architectures and Processors, The Hague, Olanda. 06/2004 Detecting Faults in Integer and Finite Field Arithmetic Operations for Cryptography, at the Workshop on Fault Diagnosis and Tolerance in Cryptography, Firenze, Italia. 08/2004 Efficient Hardware-Based Fault Diagnosis Scheme for AES, at the Rump Session of the International Workshop on Cryptographic Hardware and Embedded Systems(CHES), Boston (MA), USA. 09/2004 Detecting Faults in Four Symmetric Key Block Ciphers at the International Conference on Application-Specific Systems, Architectures and Processors, Galveston(TX), USA. 10/2004 An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost, at the International Symposium on Defect and Fault Tolerance in VLSI Systems, Cannes, Francia. 10/2004 Dissemination and Architecture Review, at the Final Review of CryptoSoC - Cryptographic System on a Chip, Paris, Francia. 09/2005 Incorporating Error Detection in an RSA Architecture, at the 2nd Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2005), Edinbourgh, Scotland(UK). 10/2005 Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard, at the 20th International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Monterey(CA), USA. 5

6 07/2006 A Note on Error Detection in an RSA Architecture by means of Residue Codes, at the 12th IEEE International On-Line Testing Symposium (IOLTS), Como, Italy. 09/2007 Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections at the 22nd International Symposium on Defect and Fault Tolerance in VLSI Systems(DFT), Rome, Italy. 09/2007 A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection at the International Workshop on Fault Diagnosis and Tolerance in Cryptography(FDTC), Wien, Austria. 07/2008 Software Self-Testing of a Symmetric Cipher with Error Detection Capability at the 14th IEEE International On-Line Testing Symposium 2008(IOLTS 2008), to appear. CONFERENCE PARTECIPATIONS 13rd International Conference on Application-Specific Systems, Architectures and Processors (ASAP), San José (CA), USA, th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), The Hague, Netherlands, Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), Firenze, Italy, Workshop on Cryptographic Hardware and Embedded Systems (CHES), Boston (MA), USA, th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Galveston(TX), USA, th International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, France, Workshop on Cryptographic Hardware and Embedded Systems (CHES), Edinbourgh, Scotland(UK), nd International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC 2005), Edinbourgh, Scotland(UK), th International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Monterey(CA), USA, th IEEE International On-Line Testing Symposium (IOLTS), Como, Italy, nd International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Rome, Italy, th International Workshop on Fault Diagnosis and Tolerance in Cryptography(FDTC), Wien, Austria, th IEEE International On-Line Testing Symposium (IOLTS), Rhodes, Greece,

7 PUBLICATIONS Note: In most of the following publications the authors are listed in alphabetic order. INTERNATIONAL JOURNALS A1. P. Maistri, R. Leveugle. Double-Data-Rate Computation as a Countermeasure against Fault Analysis ; Computers, IEEE Transactions on, DOI /TC , accepted for future publication. A2. L. Breveglieri; I. Koren; P. MAISTRI. An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers ; Computers, IEEE Transactions on, Volume: 56, Issue: 5, Pages: , May A3. G. Bertoni; L. Breveglieri; I. Koren; P. MAISTRI; V. Piuri. Error analysis and detection procedures for a hardware implementation of the Advanced Encryption Standard ; Computers, IEEE Transactions on, Volume: 52, Issue: 4, Pages: , April INTERNATIONAL CONFERENCE PROCEEDINGS B1. P. Maistri, R. Leveugle. Software BIST Capabilities of a Symmetric Cipher ; 15th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2008), to appear, B2. P. Maistri, C. Excoffon, R. Leveugle. Software Self-Testing of a Symmetric Cipher with Error Detection Capability ; 14th IEEE International On-Line Testing Symposium (IOLTS 2008), pp , B3. C. Excoffon, P. Maistri, R. Leveugle. Software-Based BIST Capabilities of the Advanced Encryption Standard ; European Test Symposium (ETS 2008). Digital Proceedings, B4. P. Maistri, R. Leveugle. Multi-cycle Fault Injections in Error Detecting Implementations of the Advanced Encryption Standard ; International Design and Test Workshop (IDT). Proceedings. pp , B5. P. Maistri, P. Vanhauwaert, R. Leveugle. Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections ; Defect and Fault Tolerance in VLSI Systems, Proceedings. 20th IEEE International Symposium on, pp , B6. P. Maistri, P. Vanhauwaert, R. Leveugle. A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection ; Fault Diagnosis and Tolerance in Cryptography (FDTC 2007), pp , B7. L. Breveglieri, I. Koren, Paolo Maistri, M. Ravasio. Incorporating Error Detection in an RSA Architecture ; Fault Diagnosis and Tolerance in Cryptography (FDTC 2006), pp , B8. L. Breveglieri, I. Koren, Paolo Maistri. A Fault Attack Against the FOX Cipher Family ; Fault Diagnosis and Tolerance in Cryptography (FDTC 2006), pp , B9. L. Breveglieri, P Maistri, I Koren. A Note on Error Detection in an RSA Architecture by Means of Residue Codes ; International On-Line Testing Symposium (IOLTS 2006), pp ,

8 B10. L. Breveglieri, I. Koren, P. Maistri. Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard ; Defect and Fault Tolerance in VLSI Systems, Proceedings. 20th IEEE International Symposium on, pp , B11. G. Bertoni; L. Breveglieri; I. Koren; P. MAISTRI; An efficient hardware-based fault diagnosis scheme for AES: performances and cost ; Defect and Fault Tolerance in VLSI Systems, Proceedings. 19th IEEE International Symposium on, Pages: , Oct B12. L. Breveglieri; I. Koren; P. Maistri; Detecting faults in four symmetric key block ciphers ; Proceedings. Application-Specific Systems, Architectures, and Processors, Proceedings. IEEE International Conference on, Pages: , Sep B13. L. Breveglieri; I. Koren; P. Maistri; Detecting Faults in Integer and Finite Field Arithmetic Operations for Cryptography ; Workshop on FDTC: Fault Diagnosis and Tolerance in Cryptography, Supplemental Volume of the Proceedings of the Conference on Dependable Systems and Networks, Pages , June B14. A. Antola; G. Bertoni; L. Breveglieri; P. Maistri; Parallel Architectures for Elliptic Curve Cryptoprocessors over Binary Extension Fields ; The 46th IEEE Midwest Symposium On Circuits and Systems. Proceedings B15. G. Bertoni; L. Breveglieri; I. Koren; P. Maistri; V. Piuri; Detecting and locating faults in VLSI implementations of the Advanced Encryption Standard ; Defect and Fault Tolerance in VLSI Systems, Proceedings. 18th IEEE International Symposium on, Pages: , Nov B16. G. Bertoni; L. Breveglieri; I. Koren; P. Maistri; V. Piuri; Concurrent fault detection in a hardware implementation of the RC5 encryption algorithm ; Application-Specific Systems, Architectures, and Processors, 2003.Proceedings. IEEE International Conference on, Pages: , June B17. G. Bertoni; L. Breveglieri; I. Koren; P. Maistri; V. Piuri; A Parity Code Based Concurrent Fault Detection for Implementations of the Advanced Encryption Standard ; Defect and Fault Tolerance in VLSI Systems, Proceedings. 17th IEEE International Symposium on, Pages:51-59, Nov B18. G. Bertoni; L. Breveglieri; I. Koren; P. Maistri; V. Piuri; Modelling and Studying Faults In The Advanced Encryption Standard ; Application-Specific Systems, Architectures, and Processors, Proceedings. IEEE International Conference on, luglio THESES C1. P. Maistri. Algorithm Analysis for Elliptic Curve Cryptography. Master Thesis, Electrical and Computer Engineering, University of Illinois at Chicago, Chicago (IL), USA, C2. P. Maistri. Algorithm Analysis for Elliptic Curve Cryptography. Degree Thesis, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy, C3. P. Maistri. Cryptographic Algorithms and Architectures and their Connections with Errors and Reliability. PhD Thesis, Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy,

9 BOOK CHAPTERS C1. D. Barretta, L. Breveglieri, P. MAISTRI, M. Monchiero, L. Negri, A. Pagni, G. Palermo, M. Sami, C. Silvano, O. Villa, R. Zafalon; Low Power Architectures for Mobile Systems, Mobile Information Systems and Infrastructure and design for flexibility and adaptivity, Capitolo 7, C2. G. Bertoni; L. Breveglieri; I. Koren; P. MAISTRI; Error Analysis and Detection Procedures for AES, Industry Days , ISBN , pp , Grenoble, September 8, 2008 Paolo Maistri 9