Networked Embedded Systems: Design Challenges

Transcription

1 Networked Embedded Systems: Design Challenges Davide Quaglia Electronic Systems Design Group University of Verona 3 a giornata nazionale di Sintesi Logica, Verona, Jun 21, 2007

2 Outline Motivation Networked embedded systems Design trends Design challenges Application-driven top-down design flow Case study Conclusions For discussion 3 Giornata della Sintesi Logica, Verona Jun 21,

3 Motivation Application complexity grows up! HAN BAN BAN gateway mobile phone wireless sensor network ADSL modem user profile wide area network mobile phone service center web browser 3 Giornata della Sintesi Logica, Verona Jun 21,

4 Networked embedded systems Network Network device 4 Wired network Network device 2 Wired network Network device 5 Wireless network Network device 3 Network device 6 Network interface I/O interface ASIC Network device 0 System CPU Memory bus 3 Giornata della Sintesi Logica, Verona Jun 21,

5 Networked embedded systems HW/SW systems designed to perform specific applications Communications play a key role Examples Mobile phones IP phones Switches and routers Wireless sensor nodes 3 Giornata della Sintesi Logica, Verona Jun 21,

6 Cross-layer design Design trends ISO/OSI is too inefficient Complex many-to-many topologies Ad-hoc instead of tree-based topologies 3 Giornata della Sintesi Logica, Verona Jun 21,

7 Design challenges Fidelity in simulation Debugging Complex applications Heterogeneous nodes Need for interoperability Complex application rules Need for high level programming 3 Giornata della Sintesi Logica, Verona Jun 21,

8 Application-driven top-down design flow Application requirements SW HW Network System/Network partitioning Un-partitioned model of the whole application Refinement simulation & validation Un-partitioned model of the system to be designed Model of the SW HW/SW partitioning Synthesis Model of the HW Model of the network Model of the network Deployment Refinement simulation & validation Refinement simulation & validation Application + O.S. Actual HW Network 3 Giornata della Sintesi Logica, Verona Jun 21,

9 Application designers want to know Reliability Performance 3 Giornata della Sintesi Logica, Verona Jun 21,

10 Application designers should look at Reliability Node availability Packet loss/error rate Performance Throughput Delay 3 Giornata della Sintesi Logica, Verona Jun 21,

11 Application designers should act on Reliability Node availability Packet loss/error rate Performance Throughput Delay #nodes, power consumption, battery capacity radio channel, position, redundant paths HW/SW complexity protocols, association time, duty cycle 3 Giornata della Sintesi Logica, Verona Jun 21,

12 Simulation for Sys/Net partitioning System description language (SystemC) both for nodes and network Fast simulation Good model for HW and SW components Raw model of the packet switched network Network simulator (NS-2) Fast simulation Good network models Lack of reuse for synthesis of HW and SW 3 Giornata della Sintesi Logica, Verona Jun 21,

13 Simulation for Sys/Net partitioning (2) SystemC + NS-2 Fast creation of models Good HW/SW/network models High re-use for synthesis Slow simulation due to synchronization 3 Giornata della Sintesi Logica, Verona Jun 21,

14 Experiment 1: SC+NS model 3 Giornata della Sintesi Logica, Verona Jun 21,

15 Performance of the SC+NS CPU time of the system-level simulation as a function of the number of nodes in the WSN. 3 Giornata della Sintesi Logica, Verona Jun 21,

16 Experiment 2: SC w.r.t. NS 3 Giornata della Sintesi Logica, Verona Jun 21,

17 Conclusions Development of complex applications over embedded system Design flow presented Requirements -> Metrics -> Design options System/Network simulation alternatives Experimental results on simulation SystemC + NS SystemC w.r.t. NS 3 Giornata della Sintesi Logica, Verona Jun 21,

18 For discussion Applications based on networked embedded systems share some key aspects with HW and SW systems Several simple elements working together Single goal Can EDA methodologies be applied to them to simplify design process? 3 Giornata della Sintesi Logica, Verona Jun 21,

19 Thank you!