DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit

Transcription

1 DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit General Description The LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can perform all the possible 16 logic operatio on two variables and a variety of arithmetic operatio Connection Diagram Features Y Y Y Dual-In-Line Package June 1992 Provides 16 arithmetic operatio add subtract compare double plus twelve other arithmetic operatio Provides all 16 logic operatio of two variables exclusive-or compare AND NAND OR NOR plus ten other logic operatio Full lookahead for high speed arithmetic operation on long words DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit TL F Order Number DM54LS181J DM54LS181W or DM74LS181N See NS Package Number J24A N24A or W24C Pin Names A0 A3 B0 B3 S0 S3 M C n F0 F3 A e B G P Description Operand Inputs (Active LOW) Operand Inputs (Active LOW) Function Select Inputs Mode Control Input Carry Input Function Outputs (Active LOW) Comparator Output Carry Generate Output (Active LOW) Carry Propagate Output (Active LOW) Carry Output C1995 National Semiconductor Corporation TL F 9821 RRD-B30M115 Printed in U S A

2 Absolute Maximum Ratings (Note) Supply Voltage Input Voltage Operating Free Air Temperature Range DM74LS Storage Temperature Range 7V 7V 0 Ctoa70 C b65 Ctoa150 C Recommended Operating Conditio Symbol Parameter DM54LS181 Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditio table will define the conditio for actual device operation DM74LS181 Min Max Min Nom Max V CC Supply Voltage V V IH High Level Input Voltage 2 2 V V IL Low Level Input Voltage V I OH High Level Output Current b0 4 b0 4 ma I OL Low Level Output Current 4 8 ma T A Free Air Operating Temperature b C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditio Min Typ (Note 1) V I Input Clamp Voltage V CC e Min I I eb18 ma b1 5 V V OH High Level Output V CC e Min I OH e Max DM Voltage V IL e Max DM V OL Low Level Output V CC e Min I OL e Max DM Voltage V IH e Min DM Max I OL e 4 ma V CC e Min DM I I Input Current Max V CC e Max V I e 7V M input 0 1 Input Voltage V I e 10V (DM54) A n B n 0 3 S n 0 4 C n 0 5 I IH High Level Input Current V CC e Max V I e 2 7V M input 20 A n B n 60 S n 80 C n 100 I IL Low Level Input Current V CC e Max V I e 0 4V M input b0 4 A n B n b1 2 S n b1 6 C n b2 0 I OS Short Circuit V CC e Max Output Current (Note 2) Units Units V V ma ma ma b20 b100 ma I CC Supply Current V CC e Max B n C n egnd DM54 35 S n M A n e4 5V DM74 37 Note 1 All typicals are at V CC e 5V T A e 25 C Note 2 Not more than one output should be shorted at a time and the duration should not exceed one second ma 2

3 Switching Characteristics DM54 DM74LS Symbol Parameter Conditio C L e 15 pf Units Propagation Delay M e GND 27 C n to 20 Propagation Delay M e GND 26 C n to F 20 Propagation Delay M S 1 S 2 egnd 29 A or B to G (Sum) S 1 S 3 e4 5V 23 Propagation Delay M S 0 S 3 egnd 32 A or B to G (Diff) S 1 S 2 e4 5V 26 Propagation Delay M S 1 S 2 egnd 30 A or B to P (Sum) S 0 S 3 e4 5V 30 Propagation Delay M S 0 S 3 egnd 30 A or B to P (Diff) S 1 S 2 e4 5V 33 Propagation Delay M S 1 S 2 egnd 32 A i or B i to F i (Sum) S 0 S 3 e4 5V 25 Propagation Delay M S 0 S 3 egnd 32 A i or B i to F i (Diff) S 1 S 2 e4 5V 33 Propagation Delay M e 4 5V 33 A or B to F (Logic) 29 Propagation Delay M S 1 S 2 egnd 38 A or B to (Sum) S 0 S 3 e4 5V 38 Propagation Delay M S 0 S 3 egnd 41 A or B to (Diff) S 1 S 2 e4 5V 41 Propagation Delay M S 0 S 3 egnd 50 A or B to A e B S 1 S 2 e4 5V 62 R L e 2kXto 5 0V Min Max 3

4 Sum Mode Test Table I Symbol Function Inputs S0 e S3 e 4 5V S1 e S2 e M e 0V Other Input Input Other Data Inputs Output Same Bit Test Apply Apply Apply Apply Test 4 5V GND 4 5V GND A i B i None B i A i None A and B A and B A B None None B A None None C n C n A None B B A C n B None A B A C n A None B B A C n B None A B A C n All All Any F C n None None A B or Diff Mode Test Table II Symbol Function Inputs S1 e S2 e 4 5V S0 e S3 e M e 0V F i F i P P G G Other Input Input Other Data Inputs Output Same Bit Test Apply Apply Apply Apply Test 4 5V GND 4 5V GND A None B A B C n B A None A B C n A None B None B A None None A B None None B None A None A None B A B C n B A None A B C n A B None None B None A None C n None None 4 All A and B None F i F i P P G G A e B A e B

5 Logic Mode Test Table III Symbol Function Inputs S1 e S2 e M e 4 5V S0 e S3 e 0V Other Input Input Other Data Inputs Output Same Bit Test Apply Apply Apply Apply Test 4 5V GND 4 5V GND A B None None B A None None Any F Any F Functional Description The LS181 is a 4-bit high speed parallel Arithmetic Logic Unit (ALU) Controlled by the four Function Select inputs (S0 S3) and the Mode Control input (M) it can perform all the 16 possible logic operatio or 16 different arithmetic operatio on active HIGH or active LOW operands The Function Table lists these operatio When the Mode Control input (M) is HIGH all internal carries are inhibited and the device performs logic operatio on the individual bits as listed When the Mode Control input is LOW the carries are enabled and the device performs arithmetic operatio on the two 4-bit words The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the output or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate) In the ADD mode P indicates that F is 15 or more while G indicates that F is 16 or more In the SUBTRACT mode P indicates that F is zero or less while G indicates that F is less than zero P and G are not affected by carry in When speed requirements are not stringent it can be used in a simple ripple carry mode by connecting the Carry output ( ) signal to the Carry input (C n ) of the next unit For high speed operation the device is used in conjunction with the 9342 or 93S42 carry lookahead circuit One carry lookahead package is required for each group of four LS181 devices Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths The A e B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode The A e B output is open-collector and can be wired-and with other A e B outputs to give a comparison for more than four bits The A e B signal can also be used with the signal to indicate A l B and A k B The Function Table lists the arithmetic operatio that are performed without a carry in An incoming carry adds a one to each operation Thus select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied Because subtraction is actually performed by complementary addition (1s complement) a carry out mea borrow thus a carry is generated when there is no underflow and no carry is generated when there is underflow As indicated this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs For either case the table lists the operatio that are performed to the operands labeled iide the logic symbol Function Table Mode Select Active LOW Operands Active HIGH Operands Inputs F n Outputs F n Outputs Logic Arithmetic Logic Arithmetic S3 S2 S1 S0 (M e H) (M e L) (C n e L) (M e H) (M e L) (C n e H) L L L L A A minus 1 A A L L L H AB AB minus 1 A a B A a B L L H L A a B AB minus 1 AB A a B L L H H Logic 1 minus 1 Logic 0 minus 1 L H L L A a B A plus (A a B) AB A plus AB L H L H B AB plus (A a B) B (A a B) plus AB L H H L A Z B A minus B minus 1 A Z B A minus B minus 1 L H H H A a B A a B AB AB minus 1 H L L L AB A plus (A a B) A a B A plus AB H L L H A Z B A plus B A Z B A plus B H L H L B ABplus (A a B) B (A a B) plus AB H L H H A a B A a B AB AB minus 1 H H L L Logic 0 A plus A Logic 1 A plus A H H L H AB AB plus A A a B (A a B) plus A H H H L AB ABminus A A a B (A a B) plus A H H H H A A A Aminus 1 Each bit is shifted to the next most significant position Arithmetic operatio expressed in 2s complement notation 5

6 Logic Symbols Active High Operands TL F Active Low Operands V CC e Pin 24 GND e Pin 12 TL F

7 Logic Diagram TL F

8 8

9 Physical Dimeio inches (millimeters) Package (J) Order Number DM54LS181J NS Package Number J24A 24-Lead Molded Dual-In-Line Package (N) Order Number DM74LS181N NS Package Number N24A 9

10 DM54LS181 DM74LS181 4-Bit Arithmetic Logic Unit Physical Dimeio inches (millimeters) (Continued) Package (W) Order Number DM54LS181W NS Package Number W24C LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a) are intended for surgical implant support device or system whose failure to perform can into the body or (b) support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with itructio for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax (a49) th Floor Straight Block Tel Arlington TX cnjwge tevm2 c com Ocean Centre 5 Canton Rd Fax Tel 1(800) Deutsch Tel (a49) Tsimshatsui Kowloon Fax 1(800) English Tel (a49) Hong Kong Fran ais Tel (a49) Tel (852) Italiano Tel (a49) Fax (852) National does not assume any respoibility for use of any circuitry described no circuit patent licees are implied and National reserves the right at any time without notice to change said circuitry and specificatio