BADGE. Documentation. Slices 1 IOB 2 GCLK BRAM

Transcription

1 BitSim Accelerated Graphics Display Engine May 7, 2008 Product Specification BitSim AB S:t Eriksgatan Stockholm Sweden Phone: Fax: URL: Features AllianceCORE Facts Documentation Design File Formats Constraints Files Verification Instantiation Templates Reference Designs & Application Notes Additional Items Provided with Core User Guide, Programmers Guide, Product Briefs, Technical Notes EDIF netlist, VHDL.ucf VHDL Test Bench, Command files VHDL BADGER-Ref Design, API, Decompression Windows CE, Linux device drivers, Simulation Tool Used Provides Hardware-Accelerated Graphics and Text for Embedded Systems Modular Design that ensures scalability and cost effective implementations Text/Graphics overlay on Video Scalable Text & 2D Acceleration (incl. BitBLT with Raster Operations) Support for Multiple Video sources Up to 4096 x 4096 pixels display resolution Color depth up to 24 bits per pixel Anti-aliasing, high quality graphics JPEG and Deflate options for Data Compression/ Decompression - * New * CPU-data buses of 32, 16 and 8-bit supported, or serial busses API - Easy to use Reference Design available for evaluation and development - * New * SW Utilities Easy development of graphics for the target system- * New * ModelSim (Mentor Graphics) Support Support provided by BitSim AB API for non OS users. Table 1: Example Implementation Statistics for Xilinx FPGAs Fmax Family Example Device (MHz) Slices 1 IOB 2 GCLK BRAM MULT/ DSP48/E DCM / Design CMT MGT Tools Spartan -3x XC3S N/A ISE i Virtex -4 XC4LV N/A ISE i Virtex -5 XC5VLX N/A ISE i Notes: 1) Actual slice count dependent on percentage of unrelated logic see Mapping Report File for details 2) Assuming all core I/Os and clocks are routed off-chip May 7, Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc.

2 Host Host Interface Video Display Controller Display Memory Interface Memory Figure 1: BADGE Block Diagram Features (continued) Alpha Blending (2 types) Scalable Layer support Supports multi-buffered frame memory flicker fee Programmable frame rate Sprites - Hardware-cursor support Supports parallel LVTTL, serial LVDS and DVI compatible TFT-interfaces Supports Display Power Sequencing Supports DE Only Mode, for displays which do not use hsync and vsync inputs Support of Portrait mode Windows CE drivers available (4.2, 5 & 6) Linux drivers (accelerated Frame Buffer for Linux) A Test Pattern Generator is included, for display debug purpose Fully synchronous, synthesizable and technology independent RTL code Adaptable for any processor, i.e. MicroBlaze, PowerPC, XScale, 386EX, Freescale, Renesas, NEC, Fujitsu, etc. Applications Medical Instrumentation Industrial Equipment Defense Automotive Test and Measurement Instrumentation Gaming and Amusement Machines General Description 2 May 7, 2008

3 BitSim General Description Brief BitSim Accelerated Display Graphics Engine, BADGE, accelerates graphics and drive displays in Embedded Systems. BADGE provides Text and 2D acceleration. BADGE can handle multiple video sources and overlays graphics and text on video. BADGE can be scaled and adapted to fit both high performance requirements as well as fitted into highly cost optimized applications. BADGE provides a solution for products with life cycles longer than consumer products. The FPGA enables a design platform that can be used for multiple products. BADGE allows the designer to reuse processor solutions and still take full advantage of the latest development in display technology and memory technology. BADGE enables advanced graphics without the cost or power increase of a high performance processor. Example of tasks: Draw pixels, lines and rectangles Write text of various fonts, sizes and colors Copy, resize and recolor objects of any shape Do Bit Block Transfers BitBLT and Raster Operations, ROP Draw/Move graphical objects e.g. sprites Analog and Digital Video BADGE acts as a Graphic Accelerator between the host processor and the LCD/TFT displays. BADGE includes a number of s (Graphics Processing Units). See fig 1.These work in parallel for generating the accelerated graphics in the graphics memory. Each have a specialized functionality. There are s for drawing, copying, scaling etc. BADGE provides graphics acceleration for drawing common shapes, such as lines, rectangles and text. Shapes that are seldom used can be drawn in the traditional way by software. BADGE can accelerate, Bit Block Transfers, BitBLT, and copy operations combined with Raster Operations. This is an effective method to copy an object of any shape. It can also be used to create basic animations. BADGE is a modular design, meaning that in a certain system, only the s with the required functionality have to be included. Other s can be omitted in order to save cost, power and size. This way it possible to tailor-make BADGE for a specific application and make a trade-off between hardwareaccelerated features using larger silicon area or non-accelerated software generated graphics. The external graphics memory is scaled to match requirement of the application. It is used for storing the displayed image, other images and graphical objects, such as text fonts and symbols. There are different variants of memory controllers available, aimed at different memory sizes and types. A variety of host controllers aimed at different CPU buses and display controller aimed at different display interface types. The adaptation makes it possible to tailor BADGE for a large span of need. May 7,

4 Functional Description Host Interface The host controller interface handles the communication with the host CPU. A large variety of host CPU buses can be supported. To interface BADGE to a particular host CPU bus, a host controller variant for the particular bus is instantiated in BADGE. Available is interfaces for range of host controllers such as: Xilinx MicroBlaze and PowerPC, Intel XScale and 386, Freescale PowerPC and Coldfire, Renesas H & M, NEC, Fujitsu. Some applications allow for Serial Host interfaces such as SPI, I2C, CAN or a basic RS232 link. Memory Interface The memory controller handles the interface to external graphics memory. It includes an arbiter, which administrates all data traffic between the s and the graphics memory. Several different memory types can be supported. To interface BADGE to a particular memory type, a memory controller variant for the particular memory type is instantiated in BADGE. Currently available memory controllers are SDRAM, DDR, SRAM and ZBT-SRAM. Other memory interfaces can be supported on request. Display Controller The display controller handles the interface to the LCD/TFT display. It reads image data from the graphics memory and outputs it to the display together with display clock, sync and enable signals. The display controller provides a sprite, a hardware cursor. A Color Look Up Table, CLUT, can be implemented to save memory and memory bandwidth. Optionally a selectable numbers of hardware layers can be implemented. Multiple displays are supported. The interface to the display can either be a parallel LVTTL, serial LVDS or optional a DVI compatible interface. A combination of interfaces is also possible. s The Graphics Processing Units in BADGE performs the accelerated graphics operations. When running in a system, the host CPU issues graphics commands to the host controller block. This block routes the command to the associated with the command, and then the executes the command. Examples of available s are: CHR The Character is used to accelerate text drawing with various fonts, sizes and colors. Anti aliased fonts are supported. Simple Commands relieves the Host processor complex text rendering operations. RCC The Rectangle Copy performs rectangle copying (e.g. BitBLT ) including Raster OPerations (ROP). ROP is normally used in Graphical User Interfaces (GUI), for example inverting and shadowing of icons. Animations and other 2D effects are easy to create with this block. SPD The Simple Pixel Drawing is used for drawing points, lines and rectangles, with specified color. IPU The Inflate Unit decompresses material that is stored with compress Deflate to minimize storage size and transfer time. IPU versions for serial parallel memory are available. 4 May 7, 2008

5 JPU The JPEG Unit decompresses JPEG material. Regular photos use this HW acceleration to be decompressed and available with very low delay. JPU versions for serial parallel memory are in development. VPU The Video Processing Unit is used for generating graphics overlay on a video signal. The video signal is fed to BADGE, and then BADGE synchronizes with that video signal and overlays graphics or text. BitSim BADGE accepts analog video signals, such as composite video (CVBS), S-video or RGB as input. In addition, digital uncompressed video signals, such as SDI, are supported. The NTSC and PAL detection is automatic. The picture can be positioned to any part of the screen. Both basic and advanced scaling options are available. The VPU converts the received ITU-R BT.656 into 16-bit RGB format. A multiplexer switches between BADGE graphics and video from the VPU, on a pixel-by-pixel basis. For analog video, a composite video decoder or ADC is required external to the FPGA. For SDI, an external deserializer is required. The output from the decoder/adc or deserializer should comply with ITU-R BT.601/656, which is the format that BADGE accepts as input. The input data is selectable between 8-bit width at 27 MHz, or 16-bit width at 13.5 MHz. An optional configuration uses an alpha blender instead of the multiplexer. The alpha blender makes it possible to gradually mix different percentages of video respective graphics within the same pixel.description of each block in the Figure 1 block diagram. Core Modifications BADGE is currently available in four base configurations, with additional options for data compression and scaling. BADGE can be adapted and modified to meet a wide range of needs. The result is highly optimized implementations meeting targets for high performance, or highly compact solutions. Contact BitSim AB to discuss adaptation and modifications. Configuration BADGE Lite BADGE 2D BADGE Video BADGE Full Description The Display-Controlling device Pixel-by-pixel access HW Cursor Adds 2D & Text Acceleration Adds Video Lite, 2D & Video Examples New Host interfaces: new CPUs, PCI, Serial Interfaces, etc New memory interfaces, or display interfaces New s adding new functionality must contact you to perform them. Multiple displays or non-standard displays. Core I/O Signals The core signal I/O has not been fixed to specific device pins to provide flexibility for interfacing with user logic (except for example reset- and clock-pins). Descriptions of signal I/O for an example application with 32-bit OPB host interface; 32-bit SDRAM memory interface and LVDS Display interface are provided in Table 2. May 7,

6 Table 2: Core I/O Signals. Signal Signal Direction Description Signal Group (optional) Clocks and reset reset_n Input Global reset Clk Input Core clock for logic clk_180 Input Inverted core clock for logic clk_mem Input Memory controller clock clk_lvdsp Input Serial LVDS interface data clock clk_lvdsn Input Inverted serial LVDS interface data clock OPB Host Interface OPB_Abus[31..0] Input Address OPB_Dbus[31..0] Input Data to BADGE OPB_RNW Input Read / Write OPB_BE[3..0] Input Byte Enables OPB_select Input Select OPB_seqAddr Input Sequential Address sl_dbus[31..0] Output Data to CPU sl_xferack Output Transfer Acknowledge sl_errack Output Error Acknowledge sl_retry Output Retry sl_toutsup Output Time out supress Irq Output Interrupt request to host CPU LVDS Display Interface TXclkp Output Display Clock positive TXclkn Output Display Clock negative TXp[3..0] Output Data positive TXn[3..0] Output Data negative Memory Interface MEM_Clk Output Memory clock MEM_Cke Output Clock Enable MEM_Cs_n Output Chip Select MEM_Ras_n Output Row Address Strobe MEM_Cas_n Output Column Address Strobe MEM_We_n Output Write Enable MEM_Address[11..0] Output Address MEM_Bank[1..0] Output Bank Select MEM_Data[31..0] Input/Output Data MEM_Pixelmask[1..0] Output Pixel Mask Other Phaseshift_enable Output Memory clock phase shift change enable (Optional) Phaseshift_incdec Output Memory clock phase shift increase / decrease (Optional) 6 May 7, 2008

7 BitSim Verification Methods The BADGE core has been closely validated with VHDL test benches, verifying the complete functionality. BADGE has been in used in Xilinx devices in customer products since Recommended Design Experience User should be familiar with basic HDL design methodology as well as Xilinx design flow including instantiation of Xilinx netlist, implementation and simulation. Available Support Products For application without an operating system the BADGE API can be used. This provides a C-level interface to BADGE. BADGE device drivers for Windows CE and Linux are available. BADGE SW Library provides a good starting point for driver development. Ordering Information This product is available directly from Xilinx Alliance Program member BitSim. Please contact BitSim for pricing and additional information about this product using the contact information on the front page of this datasheet. Related Information Xilinx Programmable Logic For information on Xilinx programmable logic or development system software, contact your local Xilinx sales office, or: Xilinx, Inc Logic Drive San Jose, CA Phone: Fax: URL: May 7,