Data Sheet. IC timers 555 and 556. Features. Typical Absolute maximum ratings - C-MOS

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1 Data Pack Issued November 00 0 Data Sheet I timers and range of I timers suitable for monostable or astable operation. In the monostable mode these timers are capable of producing accurate delays over a very wide range. In the astable mode a wide frequency coverage is coupled with variable duty cycle capability. These versatile devices provide effective solutions for many timing and pulse circuit applications. The timer is a dual version of the single timer. The -MOS versions offer improved characteristics for particular applications. For further information on timers and their applications, please refer to the Technical Library section of the current S catalogue for suitable reference books. Typical bsolute maximum ratings - bipolar Supply voltage V current 00m Power dissipation 00mW Operating temperature 0 to 0 Storage temperature to 0 Lead temperature (0 sec) 00 Features Bipolar and -MOS versions Low external component count Wide operating voltage range Low power and supply current. Typical bsolute maximum ratings - -MOS Supply voltage V current 00m Power dissipation, 00m W 00mW Operating temperature 0 to 0 Storage temperature - to 0 Lead temperature (0 sec) 00 Note: Due to the S structure inherent in the MOS process used to fabricate these devices, connecting any terminal to a voltage greater than V 0.V or less than V -0.V may cause destructive latchup. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple systems, the supply of the -MOSI must be turned on first. Bipolar pin out diagrams -MOS pin out diagrams Ground. V -. V.. V 0 0 Ground V -

2 0 Figure Schematic diagrams omparator Stage V ef omparator Flip - Flop ontrol voltage omparator - - omparator B MOS n Drivers V - Bi polar Ground Figure Basic modes of operation Monostable stable 0n or V Pin numbers shown for timers B 0n or V Figure Load connection options urrent Source: urrent Sink: or V or V Load Load I Source I Sink

3 0 Operation input This input is used to initiate a monostable timing period. ing occurs on the negative going edge B of the pulse shown in the diagram below, at a voltage level less that of the or V supply rail. The trigger pin must be returned to a level above of the or V supply rail before the end of the set timing period T. Should the trigger pulse interval t be greater than the timing period T then the output will remain in the active state (output high) for time t. Once triggered the trigger input is disabled and any trigger pulses occurring during the timing period T have no effect on the set time. The necessity to return the trigger input to a voltage above of the or V rail and because the trigger input impedance is very high and hence susceptible to external noise, a.c. coupling of this pin is desirable. The figure below shows an arrangement for a.c. coupling of the trigger input. Figure a or V / V or V Figure b 0k B 0k t Edge B triggers circuit or V trigger I/P input The reset function is used to return the timer out-put to the steady state (output low) when interruption of a monostable timing period is required. When not required the reset should be connected to V or V. This avoids a false reset occurring. Figure input V or V Normally biased to Vss or V onnection to causes reset operation s can be seen from the timer schematics on Page the open circuit voltage at the control pin is set at or V by the internal resistors. This resistor network sets the threshold comparator trip level at supply and the trigger comparator at supply. By imposing an external voltage on this pin the comparator reference levels may be shifted above or below the nominal levels hence affecting the timing in both the monostable and astable modes. In the monostable mode this pin can be swung between % to 0% of or V. In the astable mode a variation of % to 00% of the supply rail is possible. This feature extends the versatility of the timer to voltage controlled oscillators, pulse width modulators etc. For applications where this facility is not required the control voltage terminal should be decoupled to by a 0nF capacitor. The -MOS I s, in most applications, will not require the control voltage terminal to be decoupled and should be left unconnected. The output voltage dependence on load current in sink and source modes is shown in Figure. n a.c.coupling of trigger input The minimum pulse width required for triggering and propagation delay versus voltage of trigger pulse are shown in Figure for both the bipolar and -Mos timers.

4 0 Timing formulae Monostable operation: T. sec in F in Ω stable operation: T 0. ( B ) sec in F & B in Ω T 0. B sec f =. T T ( B ) Figure Timing modes T Monostable mode Hz TIME stable mode Timing capacitor - Important The capacitor employed must have a leakage current less than 0. I th for satisfactory operation. Suitable types are silvered mica, polycarbonate, polystyrene, polypropylene, but not ceramic disc which are unstable in capacitance for network applications, or electrolytics due to high leakage current. Technical hints The bipolar timers have a totem pole type outputstage and during switching, large current spikes can appear on the supply line. Effective by-passing is necessary to eliminate noise retriggering the input and a µf tantalum capacitor mounted close to the device supply pins is suggested.to prevent the possibility of double triggering when driving TTL loads a nf capacitor connected between the timer output and ground should be found suitable. pplications Figure Time delay or V μ T T TIME The minimum recommended values for the timing resistors are = kω & B = kω. These values are consistent with reliable operation at extremes of supply voltage, however, at inter-mediate levels lower value resistors may prove satisfactory. The maximum value of these resistors is governed by the typical value of threshold current and varies for each of the timers. max. or ( B )max. = 0.V s Ω th x 0 where V s = or V to V in volts I th = current in n for the timer I. The duty cycle in the astable mode is: T = B x00% T T B The minimum duty cycle using the recommended values is approximately %. By adding a diode across B the charging path for the timing capacitor changes from ( B ) to ( D ) hence t <0. ( B ) and duty cycles from to % are possible. Figure Duty cycle STT TO TIME D/P (De-energised during timming) 0n N00 Figure Load options O -MOS elay coil ESET TO LOD or V N N00 O/P V D T/H Trig S D eg. IN Energised during timming) elay coil N

5 0 Figure 0 Touch control k Min Input or -MOS or -MOS L 0 k k Min V or V 0n B Input The value of kω resistor is suitable for industrial or public environments. With lower ambient noise, a higher value of resistor may be necessary. Figure Tone burst generator The Dual Timer makes an excellent ToneBurst Generator. The first half is connected as a one shot and the second half as an oscillator. The pulse established by the one shot turns on the oscillator allowing a burst of pulses to be generated Figure Sequential timing One feature of the Duel Timer is that by utilising both halves it is possible to obtain sequential timing. By connecting the output of the first half to the input of the second half via a nf coupling capacitor sequential timing may be obtained. Delay T is determined by the first half and T by the second half delay. 0k IN n L or V ( to V) 0 or -MOS or -MOS BL 0k n The first half of the timer is started by momentarily connecting pin to ground. When it has timed out (determined by. ) the second half begins.(its time duration is determined by. ). Figure Missing pulse detector Using the circuit shown below, the timing cycle is continuously reset by the pulse train. change in frequency, or a missing pulse, allows completion of the timing cycle which causes a change in the output level. For this application, the time delay should be set to be slightly longer than the normal time between pulses. Figure Simple pulse generator 0k 00k (V) 00 N 0k k 00 k (V) or -MOS V t T Figure Pulse width modulation (PWM) In this application, the timer is connected in themonostable mode as shown below. The circuit is triggered with continuous pulse train and the threshold voltage is modulated by the signal applied to the control voltage terminal (pin ). This has the effect of modulating the pulse width as the control voltage varies. V or ( to V) 00k 0n B0 0n Pulse width (t) adjusted by V Pulse repetition frequency ( T) adjustment by V ircuit as shown gives t = 0 0ms T = 00 0ms 0 PULSE TIN OUTPUT L or -MOS MODULTION

6 0 Figure Pulse position modulation (PPM) This application uses the timer connected for astable (freerunning) operation, shown below, with a modulating signal again applied to the control terminal. Now the pulse position varies with the modulating signal, since the threshold voltage and hence the time delay is varied. To calibrate: adjust V for known reading against signal generator using circuit shown and values in table. Minimum input pulses from slotted opto switch or Proximity detector should be > ms. t slow speeds needle will flicker. For very slow speeds use more than one hold on disc and multiply reading in table by number of holes OUTPUT L V or ( to V) or -MOS B pm Tachometer pulse per sec (or Hz on sig. gen.) Figure a Interface with inductive proximity detector MODULTION or V - Disc (non Metalic) Figure a Tachometer circuit Metal foil V S = V S = 0 VS V S S V V S k μ V 00mW 0k V N k k V ed Grey n 0k N 0V 00n 00n V 00mW 0n 0 to m Proximity detector 0- Black Figure b alibration interface k 0k N V Figure b Interface for use with slotted opto switch From sig gen 0V peak to peak n Disc V S = V S = V S 0μ IN 0k 0k B0 Slot 0B Disc k 0k V N n Slotted opto switch 0-0 S omponents shall not be liable for any liability or loss of any nature (howsoever caused and whether or not due to S omponents negligence) which may result from the use of any information provided in S technical literature. S omponents, PO Box, orby, Northants, NN S Telephone: 0 0 n Electrocomponents ompany S omponents