High Speed, Low Noise Quad Operational Amplifier OP471

Transcription

1 a FEATURES Excellent Speed: V/ s Typ Low Noise: nv/ khz Max Unity-Gain Stable High Gain Bandwidth:. MHz Typ Low Input Offset Voltage:. mv Max Low Offset Voltage Drift: V/ C Max High Gain: V/mV Min Outstanding CMR: db Min Industry Standard Quad Pinouts GENERAL DESCRIPTION The is a monolithic quad op amp featuring low noise, nv/ Hz khz, excellent speed, V/ms typical, a gain bandwidth of. MHz, and unity-gain stability. The has an input offset voltage under. mv and an input offset voltage drift below mv/ C, guaranteed over the full military temperature range. Open-loop gain of the is over, into a kw load ensuring outstanding gain accuracy and linearity. The input bias current is under na limiting errors due to signal source resistance. The s CMR of over db and PSRR of under. mv/v significantly reduce errors caused by ground noise and power supply fluctuations. The offers excellent amplifier matching which is important for applications such as multiple gain blocks, low-noise instrumentation amplifiers, quad buffers and low-noise active filters. The conforms to the industry standard -lead DIP pinout. It is pin-compatible with the LM/LM9, HA7, RM, MC337, TL and TL7 quad op amps and can be used to upgrade systems using these devices. For applications requiring even lower voltage noise the OP7 with a voltage density of nv/ Hz khz is recommended. High Speed, Low Noise Quad Operational Amplifier OUT A IN A +IN A 3 V+ +IN B IN B OUT B 7 -Lead Hermetic Dip (Y-Suffix) PIN CONFIGURATIONS OUT D 3 IN D +IN D V +IN C 9 IN C OUT C OUT A IN A +IN A 3 V+ +IN B IN B OUT B 7 -Lead SOIC (S-Suffix) OUT A IN A +IN A V+ +IN B IN B OUT B NC OUT D IN D +IN D V +IN C IN C OUT C NC NC = NO CONNECT -Lead Plastic Dip (P-Suffix) OUT D 3 IN D +IN D V +IN C 9 IN C OUT C V+ BIAS IN +IN OUT V Figure. Simplified Schematic Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7/ Fax: 7/3-73 Analog Devices, Inc.,

2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V S = V,, unless otherwise noted.) E F G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Input Offset Voltage V OS mv Input Offset Current I OS V CM = V 7 3 na Input Bias Current I B V CM = V 7 na Input Noise Voltage e n p-p. Hz to Hz nv p p Input Noise e n f O = Hz nv/ Hz Voltage Density f O = Hz nv/ Hz f O = khz... nv/ Hz Input Noise i n f O = Hz pa Hz Current Density f O = Hz pa Hz f O = khz... pa Hz Large-Signal A VO V = ± V Voltage Gain R L = kw V/mV R L = kw V/mV Input Voltage Range 3 IVR ± ± ± ± ± ± V Output Voltage Swing V O R L kw ± ± 3 ± ± 3 ± ± 3 V Common-Mode CMR V CM = ± V 9 9 db Rejection Power Supply PSRR V S =. V to V mv/v Rejection Ratio Slew Rate SR... V/ms Supply Current I SY No Load ma (All Amplifiers) Gain Bandwidth GBW Av =... MHz Product Channel Separation CS V O = V p-p db f O = Hz Input Capacitance C IN... pf Input Resistance R IN... MW Differential-Mode Input Resistance R INCM GW Common-Mode Settling Time t S A V = To.%... ms To. % ms NOTES Guaranteed but not % tested. Sample tested. 3 Guaranteed by CMR test.

3 ELECTRICAL CHARACTERISTICS (V s = ± V, C T A C for E/F, C T A for G, unless otherwise noted.) E F G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Input Offset Voltage V OS mv Average Input TCV OS 7 mv/ C Offset Voltage Drift Input Offset Current los V CM = V na Input Bias Current I B V CM = V na Large-Signal V O = ± V Voltage Gain Avo R L = kw 37 V/mV R L = kw Input Voltage Range* IVR ± ± ± ± ± ± V Output Voltage Swing V O R L kw ± ± 3 ± ± 3 ± ± 3 V Common-Mode CMR V CM = ± V 9 9 db Rejection Power Supply PSRR V S = ±. V to ± V mv/v Rejection Ratio Supply Current (All Amplifiers) I SY No Load ma *Guaranteed by CMR test. ABSOLUTE MAXIMUM RATINGS Supply Voltage ± V Differential Input Voltage ±. V Differential Input Current ± mw Input Voltage Supply Voltage Output Short-Circuit Duration Continuous Storage Temperature Range P, Y-Package C to + C Lead Temperature Range (Soldering, sec) C Junction Temperature (T i ) C to + C Operating Temperature Range E, F C to + C G C to + C NOTES Absolute Maximum Ratings apply to packaged parts, unless otherwise noted. The s inputs are protected by back-to-back diodes. Current limiting resistors are not used in order to achieve low noise performance. If differential voltage exceeds ±. V, the input current should be limited to ± ma. Package Type JA * JC Unit -Lead Hermetic DIP(Y) 9 C/W -Lead Plastic DIP(P) 7 33 C/W -Lead SOIC (S) 3 C/W * JA is specified for worst-case mounting conditions, i.e., JA is specified for device in socket for TO, CERDIP, PDIP packages; JA is specified for device soldered to printed circuit board for SO packages. ORDERING GUIDE T A = C Package Options Operating V OS MAX Temperature (mv) -Lead CERDIP Plastic Range EY IND, FY* IND, GP XIND, GS XIND *Not for new design. Obsolete April. For military processed devices, please refer to the standard microcircuit drawing (SMD) available at 9-A - ARCMDA 9-3A - ATCMDA 9-CA - AYMDA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE 3

4 Typical Performance Characteristics VOLTAGE NOISE nv/ Hz 3 3 I/F CORNER = Hz VOLTAGE NOISE nv/ Hz AT Hz AT khz NOISE VOLTAGE nv/div 9 % mv s k TPC. Voltage Noise Density vs. Frequency SUPPLY VOLTAGE V TPC. Voltage Noise Density vs. Supply Voltage TIME Seconds TPC 3.. Hz to Hz Noise VOLTAGE NOISE nv/ Hz 3 3 I/F CORNER = Hz INPUT OFFSET VOLTAGE V 3 CHANGE IN OFFSET VOLTAGE V k 7 7 TEMPERATURE C 3 TIME Minutes TPC. Current Noise Density vs. Frequency TPC. Input Offset Voltage vs. Temperature TPC. Warm-Up Offset Voltage Drift INPUT BIAS CURRENT na V CM = V INPUT OFFSET CURRENT na V CM = V INPUT BIAS CURRENT na TEMPERATURE C TPC 7. Input Bias Current vs. Temperature 7 7 TEMPERATURE C TPC. Input Offset Current vs. Temperature COMMON-MODE VOLTAGE V TPC 9. Input Bias Current vs. Common-Mode Voltage

5 CMR db k k k M TPC. CMR vs. Frequency TOTAL SUPPLY CURRENT ma T A = + C T A = + C T A = C SUPPLY VOLTAGE V TPC. Total Supply Current vs. Supply Voltage TOTAL SUPPLY CURRENT ma TEMPERATURE C TPC. Total Supply Current vs. Temperature PSR db PSR PSR k k k M M M TPC 3. PSR vs. Frequency OPEN-LOOP GAIN db V S = V k k k M M M TPC. Open-Loop Gain vs. Frequency CLOSED-LOOP GAIN db k k k M M TPC. Closed-Loop Gain vs. Frequency OPEN-LOOP GAIN db PHASE GAIN PHASE MARGIN = 7 PHASE SHIFT Degrees OPEN-LOOP GAIN V/mV R L = k PHASE MARGIN Degrees 7 GBW GAIN-BANDWIDTH PRODUCT MHz 3 FREQUENCY MHz 7 9 SUPPLY VOLTAGE V 7 7 TEMPERATURE C TPC. Open-Loop Gain, Phase Shift vs. Frequency TPC 7. Open-Loop Gain vs. Supply Voltage TPC. Gain-Bandwidth Product, Phase Margin vs. Temperature

6 PEAK-TO-PEAK AMPLITUDE V k THD = % k k M M MAXIMUM OUTPUT V POSITIVE SWING NEGATIVE SWING k k LOAD RESISTANCE OUTPUT IMPEDANCE 3 3 A V = A V = k k k M M M TPC 9. Maximum Output Swing vs. Frequency TPC. Maximum Output Voltage vs. Load Resistance TPC. Closed-Loop Output Impedance vs. Frequency SLEW RATE V/ s 9.. SR. +SR TEMPERATURE C TPC. Slew Rate vs. Temperature CHANNEL SEPARATION db V O = V p-p TO khz k k k M M TPC 3. Channel Separation vs. Frequency TOTAL HARMONIC DISTORTION %... V O = V p-p R L = k A V = A V = k k TPC. Total Harmonic Distortion vs. Frequency 9 A V = 9 A V = % % V µs mv.µs TPC. Large-Signal Transient Response TPC. Small-Signal Transient Response

7 k k V V p-p V TOTAL NOISE nv/ Hz OP OP OP7 RESISTOR NOISE ONLY CHANNEL SEPARATION = LOG V V / Figure. Channel Separation Test Circuit +V 3 +V A +V B 7 k k k RS SOURCE RESISTANCE Figure. Total Noise vs. Source Resistance (Including Resistor Noise) at khz V 9 V C V 3 D TOTAL NOISE nv/ Hz OP OP OP7 Figure 3. Burn-In Circuit APPLICATIONS INFORMATION Voltage and Current Noise The is a very low-noise quad op amp, exhibiting a typical voltage noise of only. khz. The low noise characteristic of the is, in part, achieved by operating the input transistors at high collector currents since the voltage noise is inversely proportional to the square root of the collector current. Current noise, however, is directly proportional to the square root of the collector current. As a result, the outstanding voltage noise performance of the is gained at the expense of current noise performance which is typical for low noise amplifiers. To obtain the best noise performance in a circuit, it is vital to understand the relationship between voltage noise (e n ), current noise (i n ), and resistor noise (e t ). Total Noise and Source Resistance The total noise of an op amp can be calculated by: n n n S t E e i R e = ( ) + ( ) + ( ) where: E n = total input referred noise e n = op amp voltage noise i n = op amp current noise e t = source resistance thermal noise R S = source resistance The total noise is referred to the input and at the output would be amplified by the circuit gain. 7 RESISTOR NOISE ONLY k k k RS SOURCE RESISTANCE Figure. Total Noise vs. Source Resistance (Including Resistor Noise) at Hz Figure shows the relationship between total noise at khz and source resistance. For R S < kw the total noise is dominated by the voltage noise of the. As R S rises above kw, total noise increases and is dominated by resistor noise rather than by voltage or current noise of the. When R S exceeds kw, current noise of the becomes the major contributor to total noise. Figure also shows the relationship between total noise and source resistance, but at Hz. Total noise increases more quickly than shown in Figure because current noise is inversely proportional to the square root of frequency. In Figure, current noise of the dominates the total noise when R S > kw. From Figures and, it can be seen that to reduce total noise, source resistance must be kept to a minimum. In applications with a high source resistance, the OP, with lower current noise than the, will provide lower total noise.

8 OP For reference, typical source resistances of some signal sources are listed in Table I. PEAK-TO-PEAK NOISE nv OP OP7 RESISTOR NOISE ONLY k k k RS SOURCE RESISTANCE Figure. Peak-to-Peak Noise (. Hz to Hz) vs. Source Resistance (Includes Resistor Noise) Figure shows peak-to-peak noise versus source resistance over the. Hz to Hz range. Once again, at low values of R S, the voltage noise of the is the major contributor to peak-to-peak noise. Current noise becomes the major contributor as R S increases. The crossover point between the and the OP for peak-to-peak noise is at R S = 7 W. The OP7 is a lower noise version of the, with a typical noise voltage density of 3. nv/ khz. The OP7 offers lower offset voltage and higher gain than the, but is a slower speed device, with a slew rate of V/ms compared to a slew rate of V/ms for the. TABLE I. Source Device Impedance Comments Strain gauge < W Typically used in low-frequency applications. Magnetic <, W Low I B very important to reduce tapehead self-magnetization problems when direct coupling is used. I B can be neglected. Magnetic <, W Similar need for low I B in direct phonograph coupled applications. cartridges will not introduce any self -magnetization problem. Linear variable <, W Used in rugged servo-feedback differential applications. Bandwidth of transformer interest is Hz to khz. *For further information regarding noise calculations, see Minimization of Noise in Op Amp Applications, Application Note AN-. R3.k R R DUT R OP7E R 99 C F R k D N R k D N OPE R9 3k C.3 F R.k R.k C. F C3. F R k OPE R3.9k R.99k C F e OUT GAIN =, Figure 7. Peak-to-Peak Voltage Noise Test Circuit (. Hz to Hz)

9 Noise Measurements - Peak-to-Peak Voltage Noise The circuit of Figure 7 is a test setup for measuring peak-to-peak voltage noise. To measure the nv peak-to-peak noise specification of the in the. Hz to Hz range, the following precautions must be observed:. The device must be warmed up for at least five minutes. As shown in the warm-up drift curve, the offset voltage typically changes 3 mv due to increasing chip temperature after power-up. In the -second measurement interval, these temperature-induced effects can exceed tens-of-nanovolts.. For similar reasons, the device must be well-shielded from air currents. Shielding also minimizes thermocouple effects. 3. Sudden motion in the vicinity of the device can also feedthrough to increase the observed noise.. The test time to measure. Hz to Hz noise should not exceed seconds. As shown in the noise-tester frequency-response curve of Figure, the. Hz corner is defined by only one pole. The test time of seconds acts as an additional pole to eliminate noise contribution from the frequency band below. Hz.. A noise voltage density test is recommended when measuring noise on a large number of units. A Hz noise voltage density measurement will correlate well with a. Hz to Hz peak-to-peak noise reading, since both results are determined by the white noise and the location of the /f corner frequency.. Power should be supplied to the test circuit by well bypassed, low noise supplies, e.g, batteries. These will minimize output noise introduced through the amplifier supply pins. GAIN db.. Figure.. Hz to Hz Peak-to-Peak Voltage Noise Test Circuit Frequency Response Noise Measurement - Noise Voltage Density The circuit of Figure 9 shows a quick and reliable method of measuring the noise voltage density of quad op amps. Each individual amplifier is series connected and is in unity-gain, save the final amplifier which is in a noninverting gain of. Since the ac noise voltages of each amplifier are uncorrelated, they add in rms fashion to yield: e = Ê e + e + e + e Ë OUT na nb nc nd The is a monolithic device with four identical amplifiers. The noise voltage density of each individual amplifier will match, giving: e = Ê e ˆ = e Ë ( ) OUT n n ˆ R R k e OUT (nv Hz) = (e n ) e OUT TO SPECTRUM ANALYZER Figure 9. Noise Voltage Density Test Circuit 9

10 Noise Measurement - Current Noise Density The test circuit shown in Figure can be used to measure current noise density. The formula relating the voltage output to current noise density is: where: i n = Ê e Á Ë G nout ˆ - ( nv / Hz ) R G = gain of, R S = kw source resistance Capacative Load Driving and Power Supply Considerations The is unity-gain stable and is capable of driving large capacitive loads without oscillating. Nonetheless, good supply bypassing is highly recommended. Proper supply bypassing reduces problems caused by supply line noise and improves the capacitive load driving capability of the. R R k R3.k S adds phase shift in the feedback network and reduces stability. A simple circuit to eliminate this effect is shown in Figure. The added components, C and R3, decouple the amplifier from the load capacitance and provide additional stability. The values of C and R3 shown in Figure are for load capacitances of up to, pf when used with the. In applications where the s inverting or noninverting inputs are driven by a low source impedance (under W) or connected to ground, if V+ is applied before V, or when V is disconnected, excessive parasitic currents will flow. Most applications use dual tracking supplies and with the device supply pins properly bypassed, power-up will not present a problem. A source resistance of at least W in series with all inputs (Figure ) will limit the parasitic currents to a safe level if V is disconnected. It should be noted that any source resistance, even W, adds noise to the circuit. Where noise is required to be kept at a minimum, a germanium or Schottky diode can be used to clamp the V pin and eliminate the parasitic current flow instead of using series limiting resistors. For most applications, only one diode clamp is required per board or system. R f DUT OP7E R.k e n OUT TO SPECTRUM ANALYZER V/ s R GAIN =, Figure. Current Noise Density Test Circuit V IN R * *SEE TEXT * V+ V C F + C3. F C pf C. F C F + R R3 V OUT C L pf PLACE SUPPLY DECOUPLING CAPACITORS AT Figure. Driving Large Capacitive Loads In the standard feedback amplifier, the op amp s output resistance combines with the load capacitance to form a lowpass filter that Figure. Pulsed Operation Unity-Gain Buffer Applications When R f W and the input is driven with a fast, large signal pulse (> V), the output waveform will look as shown in Figure. During the fast feedthrough-like portion of the output, the input protection diodes effectively short the output to the input, and a current, limited only by the output short-circuit protection, will be drawn by the signal generator. With R f W, the output is capable of handling the current requirements (I L ma at V); the amplifier will stay in its active mode and a smooth transition will occur. When R f > 3 kw, a pole created by R f and the amplifier s input capacitance (. pf) creates additional phase shift and reduces phase margin. A small capacitor ( pf to pf) in parallel with R f helps eliminate this problem. APPLICATIONS Low Noise Amplifier A simple method of reducing amplifier noise by paralleling amplifiers is shown in Figure 3. Amplifier noise, depicted in Figure, is around nv/ khz (R.T.I.). Gain for each paralleled amplifier and the entire circuit is. The W resistors limit circulating currents and provide an effective output resistance of W. The amplifier is stable with a nf capacitive load and can supply up to 3 ma of output drive.

11 High-Speed Differential Line Driver The circuit of Figure is a unique line driver widely used in professional audio applications. With ± V supplies, the line driver can deliver a differential signal of 3 V p-p into a. kw load. The output of the differential line driver looks exactly like a transformer. Either output can be shorted to ground without changing the circuit gain of, so the amplifier can easily be set for inverting, noninverting, or differential operation. The line driver can drive unbalanced loads, like a true transformer. +V NOISE DENSITY.nV/ Hz/DIV REFERRED TO INPUT 9 % V IN R E V R k R3 Figure. Noise Density of Low-Noise Amplifier, G = R k R R7 E E R k R k R R9 V OUT = V IN IN R k R k R7 k R k R9 k R k R R k R3 k R k OUT R E R k R R3 k R k R +OUT Figure 3. Low-Noise Amplifier High-Output Amplifier The amplifier shown in Figure is capable of driving V p-p into a floating W load. Design of the amplifier is based on a bridge configuration. A amplifies the input signal and drives the load with the help of A. Amplifier A3 is a unity-gain inverter which drives the load with help from A. Gain of the high output amplifier with the component values shown is, but can easily be changed by varying R or R. Figure. High-Speed Differential Line Driver V IN R k C F + C3. F C. F C F + +V E A R 9k R3 E A R7 R k R R R L E A R k E A3 V Figure. High-Output Amplifier

12 Quad Programmable Gain Amplifier The combination of the quad and the DAC, a quad -bit CMOS DAC, creates a space-saving quad programmable gain amplifier. The digital code present at the DAC, which is easily set by a microprocessor, determines the ratio between the fixed DAC feedback resistor and the impedance the DAC ladder presents to the op amp feedback loop. Gain of each amplifier is: V V OUT IN = n where n equals the decimal equivalent of the -bit digital code present at the DAC. If the digital code present at the DAC consists of all zeros, the feedback loop will be open causing the op amp output to saturate. The MW resistors placed in parallel with the DAC feedback loop eliminates this problem with a very small reduction in gain accuracy. DAC-ET V DD V IN A R FB A V REF A I OUTA R M +V DAC A OP7E V OUT A I OUTA/B V IN B R FB B V REF B V DAC B I OUTB R M OP7E V OUT B V IN C R FB C V REF C I OUTC R3 M DAC C OP7E V OUT C I OUTC/D V IN D R FB D V REF D DAC D I OUTD R M DAC DATA BUS PINS 9 (LSB) (MSB) OP7E V OUT D DGND Figure 7. Quad Programmable Gain Amplifier

13 Low Phase Error Amplifier The simple amplifier depicted in Figure utilizes monolithic matched operational amplifiers and a few resistors to substantially reduce phase error compared to conventional amplifier designs. At a given gain, the frequency range for a specified phase accuracy is over a decade greater than for a standard single op amp amplifier. The low phase error amplifier performs second-order frequency compensation through the response of op amp A in the feedback loop of A. Both op amps must be extremely well matched in frequency response. At low frequencies, the A feedback loop forces V /(K + ) = V IN. The A feedback loop forces Vo/(K +) = V /(K + ) yielding an overall transfer function of V O /V IN = K +. The dc gain is determined by the resistor divider at the output, V O, and is not directly affected by the resistor divider around A. Note that similar to a conventional single op amp amplifier, the dc gain is set by resistor ratios only. Minimum gain for the low phase error amplifier is. Figure 9 compares the phase error performance of the low phase error amplifier with a conventional single op amp amplifier and a cascaded two-stage amplifier. The low phase error amplifier shows a much lower phase error, particularly for frequencies where / T <.. For example, phase error of. occurs at. / T for the single op amp amplifier, but at. / T for the low phase error amplifier. For more detailed information on the low phase error amplifier, see Application Note AN-7. PHASE SHIFT Degrees V IN 3 R K E A E A ASSUME: A AND A ARE MATCHED. A O (s) = T s R R R = R V R K V O V O = (K + ) V IN Figure. Low Phase Error Amplifier SINGLE OP AMP (CONVENTIONAL DESIGN) CASCADED (TWO STAGES) LOW-PHASE ERROR AMPLIFIER FREQUENCY RATIO /, / T Figure 9. Phase Error Comparison 3

14 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Lead PDIP Package (N-) PIN. (.33) MAX. (.). (.93).79 (.9).7 (.) 7. (.) BSC. (.). (.3).7 (.77). (.). (7.). (.). (.). (.3).3 (3.3) MIN SEATING PLANE.3 (.).3 (7.). (.3). (.).9 (.9). (.93) -Lead CERDIP Package (Q-). (.3) MIN.9 (.9) MAX PIN. (.) MAX. (.). (3.).3 (.). (.3) 7. (.) BSC.7 (9.9) MAX.7 (.7).3 (.7).3 (7.7). (.9). (.). (.3). (3.) MIN SEATING PLANE.3 (.3).9 (7.37). (.3). (.) -Lead SOIC Package (R-).33 (.).3977 (.) 9.99 (7.).9 (7.).93 (.).3937 (.) PIN. (.7) BSC.3 (.).9 (.3).9 (.7).9 (.). (.3). (.).9 (.9).3 (.3) SEATING PLANE. (.3).9 (.3). (.7).7 (.)

15 Revision History Location Data Sheet changed from REV. to. Edits to FEATURES Edits to ELECTRICAL CHARACTERISTICS Edits to ABSOLUTE MAXIMUM RATINGS Edits to ORDERING GUIDE Deleted DICE CHARACTERISTICS Deleted WAFER TEST CHARACTERISTICS Page

16 PRINTED IN U.S.A. C37 /(A)