Sara Vinco. Position and Education RECORD OF EMPLOYMENT

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1 Sara Vinco Name Sara Vinco Date of birth July 27, 1985 Citizenship Italian Address Via Sanzio Benazzi 15, 37135, Verona (VR) Web page pers.asp?matricola= Position and Education RECORD OF EMPLOYMENT January 2014 December 2014 Research associate at the Department of Control and Computer Engineering of the Politecnico di Torino. Project title: Energy efficient electronic design automation. EDA research group. Tutor: Prof. Massimo Poncino. January 2013 December 2013 Research associate at the Department of Computer Science of the University of Verona. Project title: Automatic device driver generation for HW accelerators in multi-core systems. December 2010 January 2011 Research assistant at the Computer Science Department of the University of Verona COCONUT project grant. Project title: Definition of the architecture of an EFSM generator. June July 2010 Research assistant at the Computer Science Department of the University of Verona. Project title: Application of the COCONUT flow to the reference platform for the final experimentation of the project technologies. January 2010 December 2012 Ph.D. student of the Science Engineering Medicine Graduate School of the University of Verona. Advisor: Prof. Franco Fummi. October December 2009 Research assistant at the Computer Science Department of the University of Verona. Project title: Automatic generation of device drivers for MPSoCs. September 2007 Research assistant at the Computer Science Department of the University of Verona. Project title: Integration of an abstract middleware in a co-simulation environment.

2 EDUCATION Ph.D. in Computer Science, University of Verona, May Thesis Title: Reuse and Integration of Heterogeneous Components for Efficient Embedded Software Generation Advisor: Prof. F. Fummi Reviewer: Prof. P. Mishra, Prof. D. Sciuto Thesis presented at the annual ACM/SigDa PhD Forum at ACM/IEEE Design Automation & Test in Europe Conference (DATE), 2012, and at the annual ACM/SigDa PhD Forum at ACM/IEEE Design Automation Conference (DAC), M. Sc. in Computer Science, University of Verona. July Grade: 110/110 cum laude. Thesis title: A methodology for automatic device driver generation Advisor Prof. F. Fummi B.Sc. in Computer Science, University of Verona. July Grade: 110/110 cum laude. Thesis title: An abstract-middleware based methodology for the design of networked embedded systems Advisor Prof. F. Fummi Scientific high school diploma at Liceo A. Messedaglia, Verona Grade: 100/100 cum laude. VISITING EXPERIENCES September - November 2013 Visiting scholar at the University of Southampton. Hosting professor: Prof. M. Zwolinski. Project title: Formal modeling of analog circuit descriptions with VHDL-AMS and Verilog-AMS to gain C++ code generation. Sponsored by a CooperInt grant from the University of Verona. June - December 2011 Visiting scholar at the University of Michigan. Hosting professor: Prof. V. Bertacco. Project title: Efficient simulation of SystemC systems on GPGPUs. SUMMER SCHOOLS SWING, School on Security of Wireless Networking, Mobile Computing and Communications: Towards the Next Generation of Networks, J.T. Schwartz International School for Scientific Research ARTIST Summer School in Europe, Artist European Network of Excellence on Embedded Systems SCHOLARSHIPS AND RESEARCH AWARDS CooperInt (COOPERazione INTernazionale) cooperation grant from the University of Verona to support the stay at University of Southampton Project title: Formal modeling of analog circuit descriptions with VHDL-AMS and Verilog-AMS to gain C++ code generation. Travel awards from ACM and SigDa to attend both the the annual ACM/SigDa PhD Forum at ACM/IEEE Design Automation & Test in Europe Conference (DATE), 2012, and at the annual ACM/SigDa PhD Forum at ACM/IEEE Design Automation Conference (DAC),

3 Best paper award at the IEEE Forum on Design Languages in 2011 for the paper Efficient implementation and abstraction of SystemC data types for fast simulation. Premio di Laurea AICA - Confindustria Servizi Innovativi e Tecnologici grant for the value of the master thesis in terms of applicability in the Italian industrial context E.S.U. grant from the University of Verona to attend a course of English grammar and culture at the Nottingham Trent University (Nottingham, England, UK) CONFERENCE SPEECHES On the Use of GP-GPUs for Accelerating Compute-intensive EDA Applications, IEEE/ACM Design And Test in Europe Conference (DATE), March 18, 21, 2013, Grenoble, embedded tutorial presentation. Energy Aware TLM Platform Simulation via RTL Abstraction, IEEE High Level Design Validation and Test Workshop (HLDVT), November 7-12, 2012, Huntington Beach, paper presentation. Accurate Profiling of Oracles for Self-Checking Time-Constrained Embedded Software, IEEE High Level Design Validation and Test Workshop (HLDVT), November 7-12, 2012, Huntington Beach, paper presentation. The Strange Pair: IP-XACT and UNIVERCM to Integrate Heterogeneous Embedded Systems, IEEE High Level Design Validation and Test Workshop (HLDVT), November 7-12, 2012, Huntington Beach, paper presentation. Reconciliation of Heterogeneous Embedded System Domains to Gain a Homogeneous SW Representation, ACM/SigDa PhD Forum at ACM/IEEE Design Automation Conference (DAC), June 01-10, 2012, San Francisco, poster presentation. SAGA: SystemC Acceleration on GPU Architectures, IEEE Design Automation Conference (DAC), June 01-10,2012, San Francisco, paper presentation. UNIVERCM: a Formal Computational Model for Heterogeneous Embedded Systems, ACM/SigDa PhD Forum at ACM/IEEE Design Automation & Test in Europe Conference (DATE), March 12-15, 2012, Dresden, poster presentation. MOUSSE: scaling MOdelling and verification to complex heterogeneous embedded Systems Evolution, ACM/IEEE Design Automation & Test in Europe Conference (DATE), March 12-15, 2012, Dresden, paper and poster presentation. Reusing of Properties after Discretization of Hybrid Automata, IEEE Microprocessor Test and Verification (MTV), December 5-7, 2011, Austin, paper presentation. Reusing of Properties after Discretization of Hybrid Automata, IEEE High-Level Design Validation and Test Workshop (HLDVT), November 10-11, 2011, Napa Valley, poster presentation. UNIVERCM the UNIversal VERsatile Computational Model for heterogeneous embedded system design, IEEE High-Level Design Validation and Test Workshop (HLDVT), November 10-11, 2011, Napa Valley, paper presentation. On the Mutation Analysis of SystemC TLM-2.0 Standard, IEEE Microprocessor Test and Verification (MTV), December 5-11, 2009, Austin, paper presentation. Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform, IEEE Microprocessor Test and Verification (MTV), December 5-11, 2009, Austin, paper presentation. 3

4 RTL IP Abstraction into Optimized Embedded Software, IEEE East-West Design and Test Symposium (EWDTS), September 16-21, 2010, St. Petersburg, paper presentation. Automatic Customization of Device Drivers for IP-cores Used with Assorted CPU Organizations, ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES - ISSS), October 11-16, 2009, Grenoble, paper and poster presentation. CONTRIBUTION TO EUROPEAN AND NATIONAL PROJECTS The research of Sara Vinco has always been inserted in the context of European projects. In detail, Sara Vinco contributed to the following European projects: FP IST VERTIGO; FP IST ANGEL; FP IST COCONUT; FP7-ICT SMAC; FP7-ICT TOUCHMORE. This allowed to test all methodologies on complex case studies and in real life scenarios, provided by the industrial partners. Sara contributed to dissemination both by publishing papers on the novel contributions and by participating to booths and dissemination activities at conferences (IEEE/ACM Design And Test in Europe Conference 2010 and 2011). She also contributed to the preparation of formal documentation, ranging from project proposals to deliverable composition. Sara Vinco also contributed to the preparation of proposals and internal documentation for FIRB (Futuro In Ricerca) and PRIN (Programmi di ricerca di rilevante interesse nazionale) national projects. Teaching activity Basic Information Technology, adjunct professor, bachelor degree in Communication Studies, University of Verona. Design of Embedded Systems, teaching assistant managing the laboratory activities and projects, master degree in Engineering and Computer Science, University of Verona. Computer Architecture, teaching assistant tutoring students, bachelor degree in Computer Science, University of Verona. Design of Embedded Systems, teaching assistant managing the laboratory activities and projects, master degree in Engineering and Computer Science, University of Verona. Computer Architecture, teaching assistant tutoring students, bachelor degree in Computer Science, University of Verona. Design of Embedded Systems, teaching assistant managing the laboratory activities and projects, master degree in Engineering and Computer Science, University of Verona. 4

5 Computer Architecture, teaching assistant tutoring students, bachelor degree in Computer Science, University of Verona. Computer Architecture, teaching assistant tutoring students, bachelor degree in Computer Science, University of Verona. Introduction to Computer Architecture, teaching assistant tutoring students, bachelor degree in Bioinformatics, University of Verona. STUDENTS SUPERVISION Master/Bachelor Students Supervision Davide Costanzi, Generazione automatica di modelli IP-XACT, Bachelor Degree in Computer Science, Advisor Prof. G. Pravadelli. AA. 2012/2013. Michele Pizzini, Automatic Generation of APU Oriented Software Applications from RTL IPs, Master Degree in Engineering and Computer Science. Advisor Prof. F. Fummi. AA. 2012/2013 (thesis writing in process). Diego Braga, The IP-XACT formalism for modeling heterogeneous embedded systems, Master Degree in Engineering and Computer Science, AA. 2010/2011. Massimo Benedetti, Generazione automatica di SW embedded a partire da descrizioni TLM, Master Degree in Computer Science. Advisor Prof. F. Fummi. AA. 2009/2010. Diego Forrini, Astrazione di IP RTL in software dedicato e ottimizzazione mediante astrazione dei tipi di dato HDL, Master Degree in Computer Science. Advisor Prof. Franco Fummi. AA. 2009/2010. Matteo Laurenzi, Astrazione di IP RTL in software dedicato e ottimizzazione mediante astrazione del protocollo di comunicazione, Master Degree in Computer Science. Advisor Dr. N. Bombieri. AA. 2009/2010. Professional Activities Co-chair for the track entitled Hardware/Software Co-design and Design Automation of the IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), Program committee member of the IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC), Delegate of the Computer Science Ph.D. students in the Computer Science Department Council, University of Verona ( ). Reviewer (or secondary reviewer) for IEEE/ACM conferences, including IEEE/ACM CODES+ISSS, IEEE/ACM DATE, IEEE/ACM DAC, IEEE DSD, ECSI/IEEE FDL, ACM/IEEE MEMOCODE, IEEE SIES, IEEE VLSI, IFIP/IEEE VLSI-SOC, IEEE HLDVT, IEEE/IFIP EUC. 5

6 Research interests The main interest of Sara Vinco s research is the integration and simulation of heterogeneous embedded systems. In particular, the activity carried out in the latest years spans over the following research lines: integration of heterogeneous components via interface generation, homogeneous formal modeling of heterogeneous components to achieve homogeneous simulation, and software generation. INTEGRATION OF HETEROGENEOUS COMPONENTS VIA INTERFACE GENERATION Modern embedded systems are highly heterogeneous, as they are composed of a mix of analog and digital HW, as well as embedded SW. Furthermore, the tight bound with the physical environment implies to take into account physical evolution during the design and verification phases. In this context, reuse is a very difficult task, as the components to integrate are highly heterogeneous. On the other hand, reuse is a winning approach to save design cost and time. Indeed, top-down approaches allow to optimize and configure each step of design, but any time that a component must be added or changed, the whole design flow must be undergone again. Given these motivations, the main goal of this research is to develop a methodology that allows to automate the integration process. Sara Vinco proposed an innovative methodology for determining the necessary interfaces. The IP-XACT description of the heterogeneous components is analyzed to gather information about their domain and interface. The IP-XACT design description is then exploited to determine the desired connections between components. A taxonomy allows then to determine the necessary connecting components to be generated [IC.14],[IC.9], [JS.1]. This step must then be followed by generation of the interfaces. This is a very error prone and time consuming process, as interface designers rarely have a deep expertise of the involved components. As a result, automatic interface generation is preferable. Sara Vinco extended the state of the art by focusing on the generation of two types of interfaces: soft drivers and device drivers. Soft drivers are interfaces allowing communication between software components. When existing software has to be reused, it may indeed be necessary to map the services invoked to the correct signature exported by an existing component, or to protect shared data. These tasks are the goal of soft drivers. Their implementation is usually associated with software engineering, rather than with embedded design. However, their generation is critical when integrating a heterogeneous system. Sara Vinco proposed a flow for automatic generation of soft drivers, taking into account the desired type of communication [IC.7]. Device drivers constitute the interface between the hardware and the software domain. Their implementation is very complex, as the device driver must comply both with the device communication protocol and with the requirements and constraints of the underlying CPU architecture. Current state of the art exploits formal specification of the device protocol, that are very difficult to extract when the hardware component is third party. Sara Vinco contributed by proposing a methodology that extracts the device communication protocol from the testbench of the device itself. Furthermore, the generated device driver can be customized with respect to the target architecture characteristics, by providing user specifications [JR.3], [IC.2], [IC.3], [IC.7], [IC.15]. The device driver generation methodology is also provided with a co-simulation platform, that connects the QEmu software emulator and SystemC to validate the generated code and hardware-software communication [IC.5]. HOMOGENEOUS FORMAL REPRESENTATION OF HETEROGENEOUS COMPONENTS Generating the necessary interfaces allows communication but preserves the degree of heterogeneity of the system. Co-simulation would allow to validate the system behavior, but it is unreliable as it implies to connect not only different simulators but also different models of computation and levels of abstraction. Furthermore, 6

7 building a co-simulation framework for managing all the typical domains of embedded systems would be a very critical and time consuming operation. Exploiting top-down flows for designing the entire system is the complementary approach. Approaches such as Ptolemy and Metropolis allow to provide a system specification and to refine it through a number of steps, by choosing the appropriate model of computation and communication style of all components. On the other hand, top-down flows do not allow reuse of existing components. In this scenario, Sara Vinco proposed UNIVERCM, an automata based model of computation that covers all the typical domains of embedded systems. The starting heterogeneous components are automatically converted to the computational model, with transformations that preserve the starting behavior and that are implemented in automatic conversion tools, thus supporting a fully bottom-up flow [JR.1], [IC.8], [IC.12], [JS.1]. The homogeneous description is then used as a starting point for automatic generation of code for simulation and validation of the integrated system, or for efficient execution [IC.17],[IC.12] [IC.21]. HARDWARE TO SOFTWARE MIGRATION For long time, hardware implementation of a functionality has been considered more advisable than the corresponding software implementation for gaining better performance and efficiency. Indeed, hardware designs are customized to the needs and constraints of the surrounding system. A major drawback of this choice is the cost in terms of money and time: indeed, any change requires to go through a redesign process and to realize a new custom circuit, thus making integration and reuse extremely challenging. Furthermore, costs of silicon realization tend to be high for highly optimized and customized circuits. The development of highly and massively parallel processors, such as multiprocessors and GP-GPUs (General Purpose Graphics Processing Units), has improved by far the effectiveness and the performance of SW. The availability of multiple processing units and of light synchronization mechanisms on one side, and the easiness of reuse and adaptation of software compared to hardware, make software a viable alternative. In this context, Sara Vinco proposes a range of methodologies that, from a common starting point, gain C++ code generation with different approaches. The starting point is a set of heterogeneous existing components, reconciliated to a single formalism through the UNIVERCM-based approach. The first approach proposed is the generation of C++ code implementing the starting functionality. The generated code can be used both as an efficient implementation of the starting system, or rather as a software version of its functionality. The generated components are converted to one or more C++ functions, managed by a single scheduling routine. The implementation of the scheduling routine differs whether the support of continuous time behaviors is preserved [IC.17] or not [IC.18],[JS.2]. The generated code can also be parallelized by creating local schedulers, associated with different execution cores and managing a subset of the C++ functions. A centralized scheduler is in charge of synchronizing local schedulers [IC.10],[JS.1]. GP-GPUs offer a massive level of parallelism that can be exploited to speed up computation. In detail, discrete GP-GPUs can be used to run code that simulates the starting system, while integrated GP-GPUs (or APUs) can be exploited as hardware accelerators for running software code. Sara Vinco proposed two flows, targeting each of such scenarios. SAGA proposed a flow to simulate RTL HDL code on GP-GPUs. RTL processes are partitioned in dataflows according to inter-process dependencies, and such dataflows are then associated with different cores. Multiple copies of the same dataflow can be run in parallel to increase throughput and to run more instancies at one time [IC.11], [IC.16], [IC.13],[JS.1]. Generating code for APUs allows to modify the internal structure of the code, in order to get more performing code. To this extent, [IC.19] proposed an approach to exploit both inter-process dependencies and pipeline structure of the starting designs to achieve massively parallel execution in software on APUs. The code generation flows have been accompanied by the implementation of an efficient data type library, reproducing hardware data types (e.g., multi-value logic) in a very efficient and performing way. This allows to preserve compatibility with respect to the starting code, without slowing down the execution or adding the overhead of hardware libraries (e.g., SystemC) [JR.2], [IC.6]. 7

8 SOFTWARE GENERATION FOR NETWORKED EMBEDDED SYSTEMS Middleware consists of a set of services that allow multiple processes running on one or more machines to interact and that supports the development of complex distributed applications by hiding networking and task distribution complexity. Thus, using middleware-centric flows for the design of Networked Embedded Systems (NES) is a key solution. Many middlewares exist in literature, but there is no comprehensive methodology supporting their use during each design step. In this context, Sara Vinco proposed techniques to enhance and automate the design of NES and to gain automatic middleware-based software generation. The main programming paradigms followed by middlewares are four: database, tuplespace, messageoriented and object-oriented. During application development the choice of the programming paradigm is driven by the expertise of the designer and by the need to re-use application components from other projects. At deployment time, the chosen programming paradigm might be not satisfactory. Sara proposed a translation flow to automatically modify the application code to use a different programming paradigm without changing the functional behavior and with no manual effort. This allows also the designer to explore other alternatives to compare performance of the same application written with different paradigms, e.g., in terms of execution time, network usage or code size [IC.1], [JS.3]. Mapping a middleware-based application to the actual middleware and software stack of the final board is a very complex operation. Indeed, not only the designer must meet tight hardware constraints, such as very limited resources, but he also has to comply with network transmission standards (e.g., ZigBee) and to deal with a bare operating system support. Sara Vinco targeted the automation of this flow by presenting a methodology for automatic refinement of object oriented applications to the ZigBee protocol and the ZStack software stack. Object oriented communication mechanisms are substituted with network messages and a centralized repository for node addresses. Node applications are modified to comply with the ZStack requirements and to avoid busy-waiting (that would stall execution). ZigBee profiles are supported [IC.4], [JS.3]. 8

9 Complete publication list H-index: 4 Citations: 59 Source: Google Scholar ( Last accessed: January 13, In all publications, except [IC.11], authors are listed in alphabetical order. Refereed international journals JR (3) Refereed international conferences IC (21) Submitted to international journals JS (3) REFEREED INTERNATIONAL JOURNALS JR.3. JR.2. JR.1. A. Acquaviva, N. Bombieri, F. Fummi, S. Vinco, Semi-Automatic Generation of Device Drivers for Rapid Embedded Platform Development, in IEEE Transactions on Computer Aided Design, vol. 32, n. 9, pp , [doi: N. Bombieri, F. Fummi, V. Guarnieri, F. Stefanni, S. Vinco, HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels, in International Journal on Design Automation for Embedded Systems, vol. 16, n. 2, pp , [doi: L. Di Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinco, UNIVERCM: the UNIversal VERsatile Computational Model for Heterogeneous System Integration, in IEEE Transactions on Computers, 2012, vol. 62, n. 2, pp , [doi: REFEREED INTERNATIONAL CONFERENCES IC.21. IC.20. IC.19. IC.18. IC.17. IC.16. IC.15. F. Fummi, M. Lora, D. Trachanis, J. Vanhese, S. Vinco, Moving from Co-Simulation to Simulation for Effective Smart Systems Design, in Proceedings of IEEE/ACM Design And Test in Europe Conference (DATE), [doi: (not available yet)] V. Guarnieri, M. Petricca, A. Sassone, S. Vinco, N. Bombieri, F. Fummi, E. Macii, M. Poncino, A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors, in Proceedings of IEEE/ACM Design And Test in Europe Conference (DATE), [doi: (not available yet)] N. Bombieri, F. Fummi, S. Vinco, On the Automatic Generation of GPUoriented Software Applications from RTL IPs, in Proceedings of ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 1-10, [doi: N. Bombieri, D. Forrini, F. Fummi, M. Laurenzi, S. Vinco, RTL IP Abstraction into Optimized Embedded Software, in Proceedigns of IEEE East-West Design and Test Symposium (EWDTS), pp. 1-5, [doi: ( /EWDTS )] F. Fummi, M. Lora, F. Stefanni, S. Vinco, Code Generation Alternatives to Reduce Heterogeneous Embedded Systems to Homogeneity, Proceedings of ECSI/IEEE/CEDA Forum on specification & Design Languages, pages 1-4, [doi: (not available yet)] F. Fummi, D. Chatterjee, V. Bertacco, N. Bombieri, S. Vinco, H.D. Patel, On the use of GP-GPUs for accelerating computing intensive EDA applications, Embedded tutorial in Proceedings of IEEE/ACM Design And Test in Europe Conference (DATE), pp , [doi: N. Bombieri, F. Fummi, V. Guarnieri, G. Pravadelli, S. Vinco, Redesign and Verification of RTL IPs through RTL-to- TLM Abstraction and TLM Synthesis, in Proceedigns of IEEE International Workshop on Microprocessor Test and Verification (MTV), pp , [doi: 9

10 IC.14. IC.13. IC.12. IC.11. IC.10. IC.9. IC.8. IC.7. IC.6. IC.5. IC.4. IC.3. IC.2. IC.1. D. Braga, F. Fummi, G. Pravadelli, S. Vinco, The Strange Pair: IP-XACT and UNIVERCM to Integrate Heterogeneous Embedded Systems, in Proceedings of IEEE High Level Design Validation and Test Workshop (HLDVT), pp , [doi: N. Bombieri, S. Vinco, V. Bertacco, D. Chatterjee, SystemC Simulation on GP-GPUs: CUDA vs. OpenCL, in Proceedings of IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS, ESWEEK conference), pp , [doi: L. Di Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinco, A Formal Support for Homogeneous Simulation of Heterogeneous Embedded Systems, in Proceedings of IEEE International Symposium on Industrial Embedded Systems (SIES 12), pp. 1-8, [doi: S. Vinco, D. Chatterjiee, V. Bertacco, F. Fummi, SAGA: SystemC Acceleration on GPU Architectures, in Proceedings of IEEE Design Automation Conference (DAC), pp , [doi: A. Acquaviva, N. Bombieri, F. Fummi, S. Vinco, On the automatic synthesis of parallel SW from RTL models of hardware IPs, in Proceedings of IEEE ACM Great lakes symposium on VLSI (GLSVLSI), pp , [doi: M. Becker, G. Bertrand, F. Fummi, W. Mueller, G. Pravadelli, S. Vinco, MOUSSE: scaling MOdelling and verification to complex heterogeneous embedded Systems Evolution, in Proceedings of ACM/IEEE Design Automation & Test in Europe Conference (DATE), pp , [doi: L. Di Guglielmo, F. Fummi, G. Pravadelli, F. Stefanni, S. Vinco, UNIVERCM: the UNIversal VERsatile Computational Model for heterogeneous embedded system design, in Proceedings of IEEE High-Level Design Validation and Test Workshop (HLDVT), pp , [doi: N. Bombieri, F. Fummi, D. Quaglia, S. Vinco, Automatic Interface Generation for Component Reuse in HW-SW partitioning, in Proceedings of EUROMICRO Conference on Digital System Design (DSD), pp , [doi: N. Bombieri, F. Fummi, V. Guarnieri, F. Stefanni, S. Vinco, Efficient implementation and abstraction of SystemC data types for fast simulation, in Proceedings of IEEE Forum on Design Languages best paper award, pp. 1-7, [ISSN: ] F. Fummi, G. Perbellini, D. Quaglia, S. Saggin, S. Vinco, Mixing Simulated and Actual Hardware Devices to Validate device Drivers in a Complex Embedded Platform, in Proceedings of IEEE Microprocessor Test and Verification (MTV), pp.63-68, [doi: F. Fummi, G. Perbellini, D. Quaglia, S. Vinco, A SystemC-centric Approach for Simulation and Generation of WSN Applications Targeted to ZigBee, in Proceedings of IEEE International Conference on Mobile and Ubiquitous Systems: Computing, Networking and Services (MobiQuitous), pp , [doi: A. Acquaviva, N. Bombieri, F. Fummi, S. Vinco, Automatic Customization of Device Drivers for IP-cores Used with Assorted CPU Organizations, in Proceedings of ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES - ISSS), pp , [doi: N. Bombieri, F. Fummi, G. Pravadelli, S. Vinco, Correct-by-Construction Generation of Device Drivers Based on RTL Testbenches, in Proceedings of IEEE Design and Test in Europe Conference (DATE), pp , [doi: F. Fummi, G. Perbellini, D. Quaglia, S. Vinco, AME: an Abstract Middleware Environment for validating Networked Embedded Systems Applications, in Proceedings of IEEE High-Level Design Validation and Test Workshop (HLDVT), pp , [doi: 10

11 SUBMITTED TO INTERNATIONAL JOURNALS JS.3. JS.2. JS.1. F. Fummi, G. Perbellini, F. Stefanni, D. Quaglia, S. Vinco, AME: A Middleware-centric Design Flow for Networked Embedded Systems, submitted to IEEE Transactions on Computer Aided Design. F. Fummi, N. Bombieri, S. Vinco, On the Automatic Synthesis of RTL IPs into Embedded SW, submitted to IEEE Transactions on Computers. F. Fummi, S. Vinco, Reuse and Integration of Heterogeneous Components for Efficient Embedded Software Generation, submitted to IEEE Transactions on Computers. Verona, January 13, 2014 Signature Sara Vinco 11