pss Comparison of AlGaN/GaN MISHEMT powerbar designs solidi status physica

Transcription

1 Phys. Status Solidi C 11, No. 3 4, (2014) / DOI /pss Comparison of AlGaN/GaN MISHEMT powerbar designs physia pss urrent topis in solid state physis Steve Stoffels *, Nioló Ronhi, Rafael Venegas, Brie De Jaeger, Denis Maron, and Stefaan Deoutere Ime Leuven, Kapeldreef 75, 3001 Leuven, Belgium Reeived 23 August 2013, revised 7 Otober 2013, aepted 12 Deember 2013 Published online 11 February 2014 Keywords AlGaN/GaN powerbar, MISHEMT, design, modelling * Corresponding author: steve.stoffels@ime.be, Phone: , Fax: This works presents a omparison of several different AlGaN/GaN powerbar designs, with a total gate width of 9mm, with the goal to minimize the total gate resistane. Analytial models were developed for the interonnet parasitis to aid in the design phase. The different power transistor topologies were fabriated in a GaN-on-Si MISHEMT tehnology. Measurements on the fabriated transistors showed a good agreement between the analytial models and the measurements. Furthermore, the modelling framework allowed us to design power transistors that reahed the goal of reduing the gate resistane while having minimal impat on other harateristis. 1 Introdution AlGaN/GaN high eletron mobility transistors (HEMT s) have properties whih make them very desirable for use as power swithes [1]. Cost redutions through e.g. heteroepitaxial growth on silion [2] have made it possible for AlGaN/GaN HEMT s to start ompeting with established silion power tehnologies. The tehnology is now mature enough that system level integration of demonstrators are starting to be realized. It is essential that, during the design phase there are tools available, whih an predit how the omponent will funtion. Furthermore, the trade-offs between different designs need to be understood, suh that a seletion an be made between devie topologies. For this work we have designed, fabriated and evaluated three different AlGaN/GaN powerbar arhitetures. During the design phase we have developed analytial models to alulate the interonnet parameters suh as gate resistane, aess resistane and parasiti apaitanes. The models were used to analyze three different designs, with very different gate and interonnet topologies and with the goal to redue the overall gate resistane. The designs were fabriated in an 8 inh GaN- On-Si MISHEMT tehnology. 2 Topologies For this work we have investigated three different topologies for power transistors. The most ommon design presented in the literature for AlGaN/GaN powerhemt s is a fishbone type of design with long interdigitated fingers [3-6]. This design is referred to in this paper as the long gate finger (LGF) design. The design is easy to implement and relatively ompat. The drawbaks are that the long gate fingers lead to an exessive gate resistane and thus limit the hoie of the stak for gate metallization. And seondly, due to the swithing delay, the ative region at the end of suh a finger will need a longer time to swith, ausing it to draw a large amount of urrent during swithing and potentially leading to reliability issues. A split gate version (W-gate) was also designed, for whih eah gate finger is split in two along the width of the finger, and eah setion was onneted from two sides. Therefore it is expeted that R g,lgw = R g,lgf /4. a) b) ) Figure 1 Shemati drawing of the a) LGF, b) SGF, ) 3DI designs.

2 Contributed Artile Phys. Status Solidi C 11, No. 3 4 (2014) 907 To avoid the issues related to the long gate fingers, we have investigated two alternative designs, with more, but shorter gate fingers in parallel. To aommodate the many fingers, the ative region was split up in several islands whih were horizontally and vertially repeated. This introdued the need for a more omplex soure and drain bus arhiteture. For one design the interonnets were designed to run in between the ative islands, we will refer to this design as the short gate finger (SGF) design. An overview of the SGF design is shown in Fig. 1b. A disadvantage of this approah is the inrease in area whih is needed for the interonnet bus. For the third design the interonnets for soure and drain were designed in a ross bar arhiteture, and staked in a 3D interonneted manner on top of the ative island (Fig. 1), referred to as 3D interonneted design (3DI). The diretion of eah subsequent interonnet level is perpendiular to the interonnets on the previous level. The gate bus runs on the lowest interonnet level in between the ative islands. This design is more ompat, as the interonnets are on top of ative, however, due to the ross bar arhiteture, high potential and low potential lines ross, whih neessitates the need to optimize the inter-metal dieletri (IMD) thikness for sustaining the high voltage applied between soure and drain in the off-state. The power bars were designed with a gate drain spaing of 10 µm, gate soure spaing of 0.75 µm and gate length of 1.5 µm. The LGF design had an ative width of w a =1 mm, while the SGF and 3DI design had a w a =150 µm. All designs had a total gate width of 9 mm. 3 Design methodology To study the impat of the topology on the funtioning of the transistor, it is essential that models are developed whih an predit the eletrial performane of the omponent. The main differene between the different topologies is related to how the interonnets are routed between the ative islands. Therefore, we have foused on modelling the parasiti resistane and apaitane due to the interonnets. The goal is to have a lumped representation for the parasitis at eah of the ports of the transistor, as is shown in the network in Fig. 2. Figure 2 Lumped equivalent iruit representation of the interonnet parasitis of an AlGaN/GaN PowerHEMT. 3.1 Resistane model The goal was to find a single lumped resistor representation for the interonnets at eah of the ports (Soure/Gate/Drain) and an approximate value for the resistanes. This was done by reating a distributed lumped omponent representation of the interonnet network. It was assumed that the distributed network onsisted of purely resistive omponents, and seondly it was assumed that for eah port all the onnetions of the interonnet elements to the ative region were equipotential, whih were then referened to ground. An example of a ut out of a lumped iruit for a portion of the SGF design is shown in Fig. 3. Figure 3 Distributed resistane network for a portion of the gatebus for the SGF design. The geometry of eah of the designs was analysed and partitioned in setions through whih the urrent ould only flow in one diretion. The resistane (R) of eah partition ould be alulated, using the value for the sheet resistane (R sh ): R = R sh W/L, (1) where W is the width of the partition and L is the length of the partition. Combining all the elements allowed us to onstrut the distributed equivalent network. Using the Kirhhoff rules allows to redue the network to a single lumped omponent. 3.2 Capaitane model For the apaitanes we have onsidered the parasiti apaitanes due to the interonnets, ourring at different geometrial loations. An overview of the different ontributions is given in the diagram, shown in Fig. 4. There are three type of apaitors onsidered, the first is an idealized parallel plate apaitor with a single dieletri in between the metal plates, indiated by C pp. The seond apaitor that was modelled was a parallel plate apaitor with multiple dieletris (C pp,m ), whih an be approximated as a series onnetion of apaitors, with the plate separation and dieletri onstant defined by eah subsequent dieletri layer in the stak. The final apaitor that was onsidered was due to the fringing fields (C ff ) between the side and top of metal interonnets and the top of a nearby eletrode. A onformal mapping tehnique was used for alulating C ff [7]. The analytial formula s for the different apaitane values are thus given by: C pp = ε 0 ε r A/d, (2) C pp,m = ε 0 A/(d 1 /ε d n /ε n ), (3) C ff = ε 0 ε r /2π ln[(t ( d t ) + )/d], (4) where ε 0 is vauum permittivity, ε r is the relative permittivity of the dieletri, d n is the thikness of the dieletri,

3 physia p s s 908 St. Stoffels et al.: Comparison of AlGaN/GaN MISHEMT powerbar designs A is the area of the eletrode and t is the thikness of the metal interonnet. Apart from these parasiti apaitanes lose to the aess regions, we also onsidered overlap apaitanes between different metal lines. Our designs also inluded a soure field plate (SFP) [8], whih is not shown in Fig. 4. The effets of the soure field plate were taken into aount by assuming a parasiti parallel plate apaitane between the SFP and the 2DEG in the drain aess region and also between the SFP and the metallization at the gate. For the on-state, the apaitane between the gate and 2DEG was also onsidered. have performed gate resistane and apaitane measurements, with an impedane analyzer and LCR meter. The R g was measured by biasing the devie in the on-state. It is assumed that the gate-soure branh ats as a series resistane (R s ), dominated by (R g ), and series apaitane (C s ), the values an be determined from the measured impedane data. The extration is done internally in the LCR meter. It an be seen from Fig. 5 that there is a good agreement between the analytial alulations and the measured gate resistane. Furthermore, it an be seen that the 3DI and LGF design have R g values whih are about 10x lower than the original LGF design, reahing our design goal. This demonstrates the apabilities of the modelling methodology presented in this work. Figure 4 Physial loation of the apaitors in the ative region of the omponent. Table 1 Capaitane values for a LGF design. The fringing apaitane inludes the lateral C pp and the lateral C ff. Bulk is the ontribution of the bulk parallel plate apaitanes between two ports. Overlap is the apaitanes due to interonnet rossing. Fringing Bulk Overlap gate-soure gate-drain soure-drain Calulating the different values for the apaitanes revealed that the parasiti impedanes are mainly aused by the vertial interonnet overlap apaitanes and the interonnet to substrate apaitanes (Table 1). Also the soure field plate plays an important role in the ontribution to the parasiti apaitane. For the power transistor designs the lateral separation is large enough that fringing field apaitanes and horizontal overlap apaitane only has a negligible influene. 4 Design of GaN powerbars The design goal was to redue the gate resistane of the LGF design with a fator of 5, while having limited impat on the key figures of merit of the power transistor. The power transistors were fabriated and subsequently haraterized, whih allowed us to evaluate both the performane of the transistors and also at as a validation for the modelling framework. The power-transistors were fabriated in an AlGaN/GaN metal insulator semiondutor HEMT (MISHEMT) devie tehnology [9], with a bilayer dieletri stak to isolate the gate eletrode from the hannel [10]. To verify the models we Figure 5 R g for different devie designs. The models for the parasiti apaitanes were verified on a single design, namely the LGF design. For the design we have varied the pith between the different gate fingers (l gg ) from 30 µm to 80 µm. The parasiti apaitanes due to the interonnets were alulated and ompared with measured values, shown in Fig. 6. It an be seen that the values for the parasiti apaitanes between the different ports are in lose agreement. The parasiti apaitanes were measured by biasing the transistor in off-state with a high V ds. This ondition assures that the intrinsi apaitanes are minimized and the parasiti apaitanes beome dominant. It was assumed that under this ondition the soure-gate branh ould be represented by a parallel resistor and apaitor, and the model for the LCR meter was set to a parallel ondutane (G p ) and apaitane (C p ). Figure 6 Variation of the off-state apaitane with the gate to gate pith (l gg ).

4 Contributed Artile Phys. Status Solidi C 11, No. 3 4 (2014) 909 Figure 7 On-state apaitane (C gs,on ) for different designs. The on-state apaitanes were measured with an LCR meter, with the transistor biased in the on-state. The extration of the apaitane value was ahieved by using a series R s -C s model. As an be seen in Fig. 7, an auray between measurement and simulation of better than 20% was ahieved. Furthermore, the SGF design has a value for the on-state apaitane, whih is very similar to the LGF design. For the designs where there is muh overlap between the interonnets (as is the ase for the 3DI and LGF-W design), the apaitane is slightly higher. 5 Figures of merit As was demonstrated in previous setion, the modelling framework allowed us to design power transistors with a lowered gate resistane, with a minimal impat on the apaitane. In this setion several key figure of merits will be ompared. Figure 8 Normalized on resistane for different designs. The first FOM is the on-resistane, normalized by the total gate width. It an be seen from Fig. 8 that it is equal for all topologies, indiating that there are no adverse effets on the resistane. This also followed from our models, as the alulated parasiti soure and drain resistanes were negligible ompared to the resistane of the ative hannel. The seond FOM is the breakdown squared divided by the speifi on-resistane (normalized by the area of the ative region) and shows for a ertain tehnology the trade-off between these two parameters (see Fig. 9). There are several topologies whih have a lower figure of merit, whih is aused by a vertial breakdown when high and low potential lines ross on different levels of the interonnets. This behaviour was not unexpeted as the inter-metal dieletris were not optimized for reahing high breakdown voltages. This optimization will be performed in future work. The last figure of merit was the on-resistane times the on-state gate-soure apaitane, whih is related to the often used figure of merit of on-resistane times gate harge. It an be seen in Fig. 10 that all designs perform at a similar level. The 3DI has slightly higher value for this FOM due to the inreased overlap apaitanes. Our models predited this behaviour, as an be seen from Fig. 7 and the FOM an be improved by inreasing the IMD thikness. Figure 10 R on,sp C gs,on for different designs. 6 Conlusions For this work we have shown a modelling framework whih an, from simple analytial models, give a good desription of the interonnet parasitis. For eah of the analysed topologies a good agreement was ahieved between simulated values and measurements. The SGF/3DI power bar designs reahed the design goal of reduing the gate resistane with a fator of 4 to 8 with respet to the long gate finger designs, while having limited impat on the FOM s R on,sp, R on C g,son and V 2 BD/R on,sp. The 3DI did exhibited a redued value for the FOM V 2 BD/R on,sp due to vertial breakdown at the interonnet rossings. However, this was expeted as no optimization was performed on the inter-metal dieletris (IMD) and will be addressed in future proess iterations. Referenes [1] D. Ueda et al., AlGaN/GaN devies for future power swithing systems, Teh. Digests of IEDM, De. 2005, pp [2] S. Deoutere et al., GaN-on-Si:A salable material system to realize ost effetive next-generation solid state lighting and power devies, Symposium on VLSI Tehnology, 2010, pp [3] T. Imada et al., Enhanement-mode GaN MIS-HEMTs for power supplies, in: IPEC, 2010 IEEE, Jun. 2010, pp Figure 9 V bd 2 /R on,sp for different designs.

5 physia p s s 910 St. Stoffels et al.: Comparison of AlGaN/GaN MISHEMT powerbar designs [4] M. Ishida, Y. Uemoto, T. Ueda, T. Tanaka, and D. Ueda, GaN power swithing devies, in: IPEC, 2010 IEEE, Jun. 2010, pp [5] N. Ikeda, S. Kaya, J. Li, Y. Sato, S. Kato, and S. Yoshida, High power AlGaN/GaN HFET with a high breakdown voltage of over 1.8 kv on 4 inh Si substrates and the suppression of urrent ollapse, ISPSD '08, IEEE, May 2008, pp [6] R. Lossy et al., High power, high AlGaN/GaN-HEMTs with novel powerbar design, IEDM Teh. Digest, De. 2005, pp [7] A. Bansal, B. C. Paul, and K. Roy, IEEE Trans. 25(12), 2765 (2006). [8] Y. F. Wu et al., IEEE Eletron Devie Lett. 25(3), 117 (2004). [9] B. D. Jaeger et al., Au-free CMOS-ompatible AlGaN/GaN HEMT proessing on 200 mm Si substrates, ISPSD 2012, pp [10] M. Van Hove et al., IEEE Eletron Devie Lett. 33(5), 667 (2012).