SBCCI'10. Symposium on Integrated Circuits and Systems Design. Proceedings of the Twenty-Third. USP, UNICAMP, and Centro Universitario da FEt

Transcription

1 September 6-9, 2010 Sao Paulo, Brazil Association for Computing Machinery Advancing Computing as a Science & Profession SBCCI'10 Proceedings of the Twenty-Third Symposium on Integrated Circuits and Systems Design Sponsored by: Brazilia ACM SIGDA, and IEEE CAS Technical Co-Sponsor: TIB/UB Hannover Organized by: USP, UNICAMP, and Centro Universitario da FEt

2 A Table of Contents SBCCI 2010 Organization «SBCCI 2010 Sponsors & Supporters xii Session 1: Low Power Design Session Chair: Ricardo Reis (UFRGS, Brazil) Computing at the Ultimate Low-Energy Limits 1 Vojin Oklobdzija (University of Texas at Dallas) Performance Analysis of Dynamic Threshold MOS (DTMOS) Based 4-lnput Multiplexer Switch for Low Power and High Speed FPGA Design 2 Deepak Kumar, Paiikaj Kumar, Manisha Pattanaik (AB V- Indian Institute ofinformation Technology and Management) Reducing and Smoothing Power Consumption of ROM-Based Controller Implementations 8 Bertrand Le Gal, Aurelien Ribon, Lilian Bossuet, Dominique Dallet (University ofbordeaux) Session 2: Analog and RF Circuits Session Chair: Wilhelmus Noije (USP, Brazil) A 5.4 GHZ Fully-Integrated Low-Noise Mixer 14 Stanley S. K. Ho, Carlos E. Saavedra (Queen's University, Canada) Wideband Ring VCO for Cognitive Radio Five-Port Receiver 18 Francisco de Assis Brito Filho (LSI-TEC IC Design House), Fernando Rangel de Sousa (Federal University ofsanta Catarina) A High Speed, Highly Linear CMOS Fully Differential Track and Hold Circuit 23 Shaahin Haddadi Nejad, Ziaaddin Daie Kouzekanani, Jafar Sobhi, Iman Salami Fard, Kuresh Ghanbari (Tabriz University) A Precision Autozero Amplifier for EEG Signals 28 Guillermo Costa, Alfredo Arnaud, Marias Miguez (Universidad Catolica del Uruguay) Session 3: Analog and Mixed-Signal Design Session Chair: Fernando Rangel (UFSC, Brazil) A -60db Thd/100mhz True Unity-Gain Voltage Buffer CMOS Circuit 33 Andre Luis Fortunato, Carlos Alberto dos Reis Filho (UNICAMP) Systematic Analysis & Optimization of Analog/Mixed-Signal Circuits Balancing Accuracy and Design Time 37 Antonio Colaci, Gianluigi Boarin, Andrea Roggero, Lorenzo Civardi (STMicroelectronics), Carlo Roma, Andreas Ripp, Michael Pronath (MunEDA GmbH), Gunter Strube (Blu Business Development) Design Methodology Using Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage Reference 43 Dalton M. Colombo, Gilson I. Wirth (UFRGS, Brazil), Christian Fayomi (UQAM, Canada) SwitchCraft Framework for Transistor Network Design 49 Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock (UFRGS, Brazil), Leomar S. da Rosa Jr (UFPel, Brazil), Renato P. Ribas, Andre I. Reis (UFRGS, Brazil) Session 4: Testing Session Chair: Alex Orailoglu (University ofcalifornia, San Diego) Design for Reality: Knowledge Discovery in Design and Test Data 54 Magdy Abadir (Freescale Semiconductor, USA) v

3 Low-Power Test in Compression-Based Reconfigurable Scan Architectures 55 Sobeeh Almukhaizim, Mohammad Mohammad (Kuwait University), Mohammad Khajah (Kuwait Institute for Scientific Research) Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors 61 Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sanchez, Matteo Sonza Reorda (Politecnico di Torino) Session 5: Multiprocessor SoCs Session Chair: Edna Barros (UFPE, Brazil) Adaptive Multi-Threading for Dynamic Workloads in Embedded Multiprocessors 67 Chenjie Yu, Peter Petrov (University ofmaryland) Evaluating the Impact of Task Migration in Multi-Processor Systems-on-Chip 73 Gabriel Marchesan Almeida, Sameer Varyani, Remi Busseuil, Gilles Sassatelli, Pascal Benoit, Lionel Torres (Laboratory ofinformatics, Robotics and Microelectronics of Montpellier), Everton Alceu Carara, Fernando GehmMoraes (Pontifical Catholic University ofrio Grande do Sul) Exploring Memory Organization in Virtual MP-SoC Platforms 79 Bruno C. Oliveira, Marcio E. Kreutz, Edgard de F. CorrSa (Universidade Federal do Rio Grande do Norte), Ivan S. Silva (Universidade Federal do Piaui) Session 6: NoC Design and Evaluation Session Chair: Altamiro Susin (UFRGS, Brazil) Evaluation of a Hardware Transactional Memory Model in an NoC-Based Embedded MPSoC 85 Leonardo Kunz, Gustavo Girao, Flavio R. Wagner (Federal University of Rio Grande do Sul) Implementation and Evaluation of a Congestion Aware Routing Algorithm for Networks-on-Chip 91 Leonel P. Tedesco, Thiago Rosa (FACIN-PUCRS, Brasil), Fabien Clermidy (CEA-LETI-MINATEC), Ney Calazans, Fernando G. Moraes (FACIN-PUCRS, Brasil) The LRD Traffic Impact on the NoC-Based SoCs 97 Johanna Sepiilveda, Marius Strum, Wang Jiang Chau (University of Sao Paulo), Ricardo Pires (Federal Institute ofeducation, Science and Technology ofsao Paulo (IFSP) Session 7: Digital Design Session Chair: Flavio Wagner (UFRGS, Brazil) Zero Logic Overhead Integration of Partially Reconfigurable Modules 103 Dirk Koch, Christian Beckhoff, Jim Torresen (University ofoslo) On Evaluating the Signal Reliability of Self-Checking Arithmetic Circuits 109 Denis T. Franco (Federal University of Rio Grande), Mai C. Vasconcelos, Linda A. de B. Naviner, Jean-Francois Naviner (Telecom ParisTech) A GALS Pipeline DES Architecture to Increase Robustness Against DPA and DEMA Attacks 115 Rafael I. Soares, Ney L. V. Calazans (Pontificia Universidade Catolica do Rio Grande do Sul), Victor Lomne, Amine Dehbaoui, Philippe Manrine, Lionel Torres (Universite Montpellier2) An Efficient Implementation of Montgomery Powering Ladder in Reconfigurable Hardware 121 Daniel G. Mesquila (Universidade Federal de Uberldndia), Guilherme Perin (Universidade Federal de Santa Maria), Fernando Luis Herrmann (Santa Maria Design House), Joao Baptista Martins (Universidade Federal de Santa Maria) vi

4 Session 8: Design Reliability Issues Session Chair: Guido Araujo (UNICAMP, Brazil) Designing Working Systems with Imperfect Chips 127 Fadi J. Kurdahi (University ofcalifornia, Irvine) Modeling the Impact of RTS on the Reliability of Ring Oscillators 128 Mauricio Banaszeski da Silva, Gilson Wirth (Universidade Federal do Rio Grande do Sul) Evaluating the Effectiveness of a Mixed-Signal TMR Scheme Based on Design Diversity 134 Gabriel de M. Borges, Luiz F. Goncalves, Tiago R. Balen, Marcelo S. Lubaszewski (Universidade Federal do Rio Grande do Sul) A Methodology to Improve Yield in Analog Circuits by Using Geometric Programming 140 Jorge Joharmy Saenz (University of Sao Paulo), Elkim Roa (Purdue University & Universidad Industrial de Santander), Armando Ayala Pabon (Integrated Systems Laboratory oftechnology, Sao Paulo), Wilhelmus Van Noije (University of Sao Paulo) Session 9: Compressed Video Architectures Session Chair: Elmar Melcher (UFCG, Brazil) An MPEG-2 Transport Stream Demultiplexer IP Core Compliant with SBTVD 146 Leonardo Medeiros, Antonio Carlos Cavalcanti (Universidade Federal da Paraiba) A High Performance Hardware Architecture for the H.264/AVC Haif-Pixel Motion Estimation Refinement 151 Marcel M. Correa, Mateus T. Schoenknecht, Luciano V. Agostini (Federal University ofpelotas) Performance Enhancement of H.264/AVC Intra Frame Prediction Hardware Using Efficient 4-2 and 5-2 Adder-Compressors 157 Claudio M. Diniz (Universidade Federal do Rio Grande do Sul), Joao Altermann, Eduardo Costa (Universidade Catdlica de Pelotas), Sergio Bampi (Universidade Federal do Rio Grande do Sul) A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension 163 Thaisa Silva, Luis A. Cruz (University of Coimbra), Luciano V. Agostini (Federal University ofpelotas) Session 10: Image, Video and Signal Processing Session Chair: Antonio Cavalcanti (UFPB, Brazil) A 720p H.264/AVC Decoder ASIC Implementation for Digital Television Set-top Boxes 168 Alexsandro C. Bonatto, Andre B. Soares, Adriano Renner, Altamiro A. Susin, Leandro Max Silva, Sergio Bampi (Federal University of Rio Grande do Sul) A Low Complexity Image Compression Solution for Onboard Space Applications 174 Antonio Lopes F. (National Institute for Space Research), Roberto d'amore (Instituto Tecnologico de Aerondutica) Ordering and Partitioning of Coefficients Based on Heuristic Algorithms for Low Power FIR Filter Realization 180 Angelo G. da Luz, Eduardo A.C da Costa (Catholic University ofpelotas), Marilton S. de Aguiar (Federal University ofpelotas) Variable Block Size Motion Estimation Architecture with a Fast Bottom-Up Decision Mode and an Integrated Motion Compensation Targeting the H.264/AVC Video Coding Standard 186 Robson S. S. Dornelles, Felipe M. Sampaio, Luciano V. Agostini (Federal University ofpelotas) vii

5 Session 11: Algorithmic Advances in CAD Session Chair: Wang Jiang Chau (USP, Brazil) fmprovements on the Detection of False Paths by Using Unateness and Satisfiability 192 Felipe S. Marques, Osvaldo Martinello Jr., Renato P. Ribas, Andre I. Reis (Institute de Informdtica - UFRGS) A Modular CNF-Based SAT Solver 198 Bernardo C. Vieira (Universidade Federal de Minas Gerais), Fabricio V. Andrade (Centro Federal de Educagao Tecnologica de Minas Gerais), Antonio O. Fernandes (Universidade Federal de Minas Gerais) CentroidM: A Centroid-Based Localization Algorithm for Mobile Sensor Networks 204 Leonardo L. de Oliveira, Joao Baptista Martins (UFSMPPGG/PPGI), Gustavo Dessbesell (Santa Maria Design House, Brazil), Jose Monteiro (IST/INESC-ID, Portugal) Implementation Comparisons of the QR Decomposition for MIMO Detection 210 Gabriel L. Nazar (Universidade Federal do Rio Grande do Sul and Technische Universitdt Kaiserslautern), Christina Gimmler, Norbert Wehn (Technische Universitdt Kaiserslautern) Author Index 215 viii