MAX1781 Advanced Smart Battery-Pack Controller Features. General Description. Applications

Transcription

1 General Description The MAX1781 smart battery-pack controller integrates a user-programmable microcontroller core, a Coulombcounting fuel gauge, a multi-channel data-acquisition unit, and an SMBus v1.1 compliant master/slave SMBus interface. The 8-bit, RISC microcontroller core has an integrated 12k bytes of user programmable EEPROM, which provides battery-pack designers with complete flexibility in developing fuel gauging and control algorithms. The MAX1781 is equipped with full ICE (in-circuit emulator) capability for efficient firmware development and debugging. The 16-bit data-acquisition unit measures individual cell voltages, cell stack voltage, chip internal/external temperature, and two general purpose analog inputs. Individual cell voltage measurements with 0.5% accuracy and over-current protection allow the MAX1781 to eliminate a separate 1st level protection IC. Adjustable over-current thresholds and delay timers provide a flexible solution. The integrating fuel gauge module provides a typical input offset of less than 1uV, and gain accuracy of better than 1% with no trimming required during pack manufacture. The MAX1781 has a wide 4V to 28V operating voltage range. The IC is available in a 7mm x 7mm 48-TQFN package with a maximum thickness of 0.8mm. Applications Notebook Battery Packs Proprietary Battery Packs Data-Acquisition Systems Remote Data Logging Ordering Information PART TEMP RANGE PIN-PACKAGE MAX1781ETM -40 C to +85 C 48 TQFN Features Accurate Fuel Gauge Uses V to F Method <1µV Input Offset Voltage <1% Gain Accuracy No Calibration Required 8-bit RISC Microcontroller Core 12k Bytes of Program/Data EEPROM 64 Bytes of Byte Writeable EEPROM 264 Bytes of RAM Watchdog Timer ICE for Firmware Debugging Integrated Development Environment (IDE) C Compiler Inline Assembler Eliminates Separate Primary-Protection IC Individual Cell Voltage Measurements with 0.5% accuracy Built-In Protection MOSFET Gate Drivers 8% Accurate Overcurrent Protection Programmable Over-Current Delay Timers SMBus v1.1-compliant, with Master Capability Typical Operating Current <120µA Typical Shutdown Current <10nA Integrated 32kHz Oscillator: No Crystal Fully Integrated LDO (V IN = 4V to 28V) Pin Configuration HV0 1 HV1 2 HV2 3 HV3 4 HV4 5 SCL 48 SDA 47 GND 46 VDD 45 PA7 44 PA6 43 PA5 42 PA4 41 PA3 40 PA2 39 PA1 38 PA NC7 35 NC6 34 NC5 33 NC4 32 NC3 HV NC2 HV6 7 HV7 8 MAX NC1 VPP0 CHG 9 28 ICLK PCKP MCLR AGND 11 *EXPOSED PADDLE 26 AIN1 VAA AIN0 DIS 13 BATT 14 B4P 15 B3P 16 B2P 17 B1P 18 BN 19 CSP 20 CSN 21 ODI 22 SCI 23 THRM 24 Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 Typical Operating Circuit + M1 M2 VAA PCKP CHG HV5 DIS BATT B4P V B ATT SCI ODI CELL #4 ICLK B3P C BN SCL CELL #3 D SDA B2P V BA TT MAX1781 CELL #2 VAA LED1 LED2 LED3 LED4 LED5 HV0 HV1 HV2 HV3 HV4 B1P CELL #1 PA5 BN S1 DISPLAY CAPACITY THRM CSP AIN0 t AIN1 PA0 PA1 PA2 PA3 PA4 PA6 PA7 HV6 HV7 GND VDD CSN MCLR VAA AGND VAA - Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 2 of 96

3 TABLE OF CONTENTS Absolute Maximum Ratings... 8 ELECTRICAL CHARACTERISTICS... 8 Pin Description Architectural Overview Harvard Architecture MAX1781 Digital Core Instruction Execution Instruction Pipeline Core Register Descriptions Program Counter (PCH and PCL) Program Stack and Interrupt PC Shadow Working Register (W) File Selection Register (FSR) Arithmetic Logic Unit (ALU) Status Register (STATUS) TBLSTRT and Accessing Data Tables in Program Memory Core Registers Program Memory Map Data Memory Map Interrupts Instruction Set Normal Modes of Operation Shutdown Entering Shutdown Recovering From Shutdown Sleep Entering Sleep Mode Wake-Up from Sleep Mode Master Clear Program Execution Factory Calibration Initialization EEPROM Memory General Description EEPROM Memory Commands Clear All Program EEPROM and Unlock Clear All Data EEPROM Clear Program EEPROM Page Clear Program EEPROM Sector Clear Data EEPROM Byte Write Program EEPROM Sector Write Data EEPROM Byte Read Program EEPROM Word Read Data EEPROM Byte Program Memory Protection Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 3 of 96

4 EEPROM Memory Registers Analog Peripherals MHz Instruction Oscillator kHz Oscillator Linear Regulators for System Power and Startup Precision Bandgap Reference Power-Supply Sequencing Mixed Signal Peripherals Fuel-Gauge Unit General Description Features Automatic Cancellation of Input Offset Voltage Coulomb Counting Charge and Discharge Counters Fuel-Gauge Gain Fuel-Gauge Current Fuel-Gauge Resolution Current Direction-Change Detection Function Counter Latching Source and Arbiter Direct CPU Control ADC Conversion Start and Stop RTCC (TEI) Interrupt Arbitration Logic FG Interrupts Fuel-Gauge Registers Data-Acquisition Unit General Description Features Analog Front-End/Multiplexer (AFE) Input Bias Cancellation AFE Register Analog-To-Digital Converter (ADC) Operation Digital Counter/Adder ADCCFG Register Description ADC/AFE Interrupts FREEZE ADC Operation with PFW Understanding ADC Error Sources ADC Registers AIN and THRM Pins BN to CSN Current-Sense Resistor Measurement Temperature Sensor Overcurrent Protection and Protection MOSFET Drivers Description Using Software to Control the Protection MOSFETs Clearing Overcurrent Interrupts ODSC FREEZE Operation CHG and DIS Output Driver Description ODSC Registers High-Voltage Output Port Description Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 4 of 96

5 HV Register Digital Peripherals Port A Port A interrupts Port A Registers RTCC Timer and Watchdog Watchdog Timer Register SMBus Interface Introduction Features Description Transmit and Receive Buffers Slave Sequence Control Master Sequence Control Packet Error Code (PEC) Timeouts and Clock Stretching Glitch Filter BAUD Rate Setting SMBus Registers Access and Security Locking/Unlocking the MAX Service/Normal Mode Manufacturer Access Commands Parallel Programming Mode Access and Security Registers Design and Applications Information ESD and Short Protection on the Battery Pins Setting Over-Discharge Current and Short-Circuit Current Thresholds Improving Fuel Gauge Measurement Accuracy Startup with Under-Voltage Cells Chip Information Package Information Table Of Figures Figure 1. SMBus Timing Diagram Figure 2. Max1781 Typical Application Circuit Figure 3. MAX1781 Harvard Architecture Figure 4. MAX1781 System Block Diagram Figure 5. MAX1781 Instruction Pipeline Figure 6. Program Memory Map Figure 7. MAX1781 Interrupt Tree Figure 8. Dual Linear Regulators Figure 9. Supply Voltage Sequencing Figure 10. Fuel-Gauge Block Diagram Figure 11. Data-Acquisition Unit Block Diagram Figure 12. ADCSTCONV and ADCI Timing Figure 13. MAX1781 Thermistor Circuit Figure 14. Overcurrent Comparator Functional Diagram Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 5 of 96

6 Figure 15. CHG and DIS pin Driver Simplified Schematic Figure 16. High-Voltage Output Port Figure 17. Port A Block Diagram Figure 18. SMBus Peripheral Block Diagram Figure 19. Putting the MAX1781 in Service Mode Figure 20. Parallel Programming Read Data Memory Byte Timing Diagram Figure 21. Parallel Programming Write Data Memory Byte Timing Diagram Figure 22. ESD and Battery Pin Short Protection Figure 23. Overcharge And Short Circuit Configuration Figure 24. Layout Recommendation for Current Sense Inputs Figure 25. Trickle Charge Circuit Table Of Registers W Working Register STATUS Status Register PCL Program Counter Low Byte PCH Program Counter High Byte FSR File Select Register TBLSTRT Table Starting Page Register for TBLRDW Instruction IE1 Interrupt Enable 1 Register IE2 Interrupt Enable 2 Register IS1 Interrupt Status 1 Register IS2 Interrupt Status 2 Register MADRL EEPROM Address Pointer Register MADRH EEPROM Address Pointer Register MDATL EEPROM Read/Write Data Register MDATH EEPROM Read/Write Data Register MCFG1 EEPROM Configuration Register FGCFG Fuel-Gauge Configuration Register FGINT Fuel-Gauge Interrupt Configuration and Status FGDISL Fuel-Gauge Discharge Count Low Byte FGDISH Fuel-Gauge Discharge Count High Byte FGCHGL Fuel-Gauge Charge Count Low Byte FGCHGH Fuel-Gauge Charge Count High Byte AFECFG AFE Configuration Register ADCCFG ADC Configuration Register ADCL ADC Result Low Byte ADCH ADC Result High Byte ODSC ODSC Configuration Register ODSCDLY Over-discharge and Short-Circuit Delay PHV High-Voltage Output Port Register PAEN Port A Output Enable Register Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 6 of 96

7 PA Port A Output Register PAIN Port A Input Register PACFG Port A Configuration Register PAINTST Port A Interrupt Status Register WDT Timer Register SMBRDR SMBus Received Data Register SMBXDR SMBus Transmit Data Register SMBCFG1 SMBus Configuration Register SMBCFG2 SMBus Configuration Register SMBST1 SMBus Status Register SMBST2 SMBus Status Register SMBEI SMBus Interrupt Enable Register SMBPSADR SMBus Primary Slave Address SMBSSADR SMBus Secondary Slave Address SMBPDR SMBus PEC SMBMACR SMBus Manufacturer Access Command TMCFGSTA Parallel Programming Register ISPDBGAC In System Programming Debug Access Register ISPDBGCFG In System Programming Debug Configuration Register Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 7 of 96

8 Absolute Maximum Ratings (VDD = VAA, AGND = GND, unless otherwise noted.) BATT, PCKP, SCL, SDA, HV[7:0] to GND V to +30V B3P, B2P, B1P, DIS to GND V to V BATT +0.3V B4P to BATT V to +0.3V CHG to GND V to V PCKP +0.3V PA[7:0] to GND V to V DD +0.3V AIN0, AIN1, ODI, SCI (Note 1), THRM, ICLK to GND V to V AA +0.3V V AA, V DD, MCLR to GND V to 6V BN, CSP to GND... -2V to 6V CSN to GND... -1V to 1V AGND to GND V to 0.3V SCI source current mA to +10mA Continuous Power Dissipation (T A =+70 C) TQFN (derating 26.3mW/ºC) mW Storage Temperature C to +150 C Lead Temperature (soldering, 10s) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications in not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VBATT = VPCKP = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = 0 C to +85 C, unless otherwise noted. Typical values are at TA = +25ºC.) PARAMETER CONDITIONS MIN TYP MAX UNITS BATT LINEAR REGULATOR (V AA ) Input Voltage Range Includes dropout operation V Output Voltage 4V < V BATT < 28V, 0 < I LOAD < 10mA V V AA to BATT Leakage Current V BATT = 0V, V AA = 3.4V, BATTON = μa V BATT = 0V, V AA = 3.4V, BATTON = µa Short-Circuit Current V DD = 2.8V, 4V < V BATT < 28V ma PCKP LINEAR REGULATOR (V AA ) Input Voltage Range Includes dropout operation V Output Voltage 4V < V PCKP < 28V, 0 < I LOAD < 10mA V V AA to PCKP Leakage Current V PCKP = 0V, V AA = 3.4V, BATTON = μa V PCKP = 0V, V AA = 3.4V, BATTON = µa PCKP Supply Current BATTON = 1 V PCKP = 20V 5 15 µa V PCKP = 28V 5 50 µa Short-Circuit Current V AA = 0V, 4V< V PCKP < 28V ma Falling V AA Power-Fail Warning Trip Level V Rising V AA 3.2 (PFW) Hysteresis on rising V AA 24 mv Power-On Reset Trip Level Falling V AA V Rising V AA 2.9 ( MCLR ) Hysteresis on rising V AA 24 MV SUPPLY CURRENT (BATT) BATTON = 1 SHUTDOWN (Everything Off) BATTON = µa SLEEP: Linear Regulator, 32kHz Clock µa Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 8 of 96

9 (VBATT = VPCKP = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = 0 C to +85 C, unless otherwise noted. Typical values are at TA = +25ºC.) PARAMETER CONDITIONS MIN TYP MAX UNITS SLEEP + FG + ODSC: Linear Regulator, 32kHz Clock, Fuel Gauge, Precision Reference, ODSC Comparators, MOSFET Drivers in DC State µa CPU RUN + FG + ODSC: Linear Regulator, 32kHz Clock, Fuel Gauge, Precision Reference, ODSC Comparators, MOSFET Drivers in DC state, Instructions Executing SLEEP + AFE/ADC + FG + ODSC: Linear Regulator, 32kHz Clock, Fuel Gauge, Precision Reference, ODSC Comparators, MOSFET Drivers in DC state, ADC Running µa µa PME2 CPURUN + FG + ODSC + DME2 Cancellation Circuit Supply Current from BATT (Only present during ADC Conversions with Cancellation Enabled, Not Included in Currents Above). Programming Program Memory EEPROM Linear Regulator, 32kHz Clock, Fuel Gauge, Precision Reference, ODSC Comparators, MOSFET Drivers in DC state, Instructions Executing, Programming Data Memory EEPROM One cancellation circuit on. 15V applied to cancellation pin; Two cancellation circuits on. 15V applied to cancellation pins µa µa FUEL GAUGE Input Voltage Offset 1 µv Input Resistance Between CSP and CSN kw Charge Coulomb-Counter Accumulation Rate Discharge Coulomb-Counter Accumulation Rate Gain Variation Current Measurement Accuracy (When Using Internal 32kHz Oscillator as a Time Base) ADC Conversion Time V CSP - V CSN = 125mV V CSP - V CSN = -125mV -125mV < V CSP - V CSN < 125mV, T A = +25 C mV < V CSP - V CSN < 125mV 0.5 V CSP - V CSN = 125mV, Excluding Offset Error 9-Bit Bit Bit Bit Bit Bit 23.6 µa 49,250 50,000 50,750 Counts/s 49,250 50,000 50,750 Counts/s % % ms Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 9 of 96

10 (VBATT = VPCKP = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = 0 C to +85 C, unless otherwise noted. Typical values are at TA = +25ºC.) PARAMETER CONDITIONS MIN TYP MAX UNITS 15-Bit Bit 93.9 High voltage, full scale = 20.48V 500 LSB Bit Weight Low voltage, full scale = 5.12V 125 µv BN to CSN, full scale = V 10 Quantization Error LSB V AA, THRM, AIN0, AIN1, V DD = V AA = V BATT = 3.4V Gain Accuracy at Full Scale % V BN -V CSN = V B1P, B2P, B3P, B4P referenced to BN BN-CSN Gain Matching between BN-CSN, V BN -V CSN =+/-0.4V % Positive and Negative Inputs Integral Nonlinearity (INL) 0.01 % Input Offset Voltage V BN -V CSN (12-bit resolution) μv B1P, B2P, B3P, B4P referenced to BN V BN for measurements of B1P, B2P, B3P, B4P Input Voltage Range V THRM, AIN0, AIN1-0.2 AA + V 0.2 Input Resistance to AGND with ADC (ON) Input Bias Current with ADC and Input Bias Current Cancellation On (B3P, B2P, B1P) Input Bias Current with ADC Off Input Bias Current with ADC Off V BN V CSN High-voltage range: BN, B1P, B2P, B3P, B4P; 4 No input bias current cancellation MW Low Voltage range: AIN0, AIN1, THRM 1 BN, CSN 80 kw V B4P = 20V, V B3P = V B2P = V B1P = 15V 80 na V B4P = V B3P = V B2P = V B1P = 20.48V 0 1 μa V BN = V AIN0 = V AIN1 = 3.4V 0 1 µa ADC CELL DIFFERENTIAL VOLTAGE MEASUREMENT ACCURACY (14-BIT RESOLUTION): B4P to B3P V B3P = 12.75V, V B4P = 17V mv B3P to B2P V B2P = 8.5V, V B3P = 12.75V mv B2P to B1P V B1P = 4.25V, V B2P = 8.5V mv B1P to BN V BN = 0V, V B1P = 4.25V mv TEMPERATURE SENSOR THRM Pull High Impedance V AA = V DD = V PCKP = V BATT = 3.4V, 2mA source current W THRM High-Impedance Leakage 1 µa SHORT-CIRCUIT AND OVER-DISCHARGE COMPARATORS ODI, SCI Input Offset Voltage mv Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 10 of 96

11 (VBATT = VPCKP = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = 0 C to +85 C, unless otherwise noted. Typical values are at TA = +25ºC.) PARAMETER CONDITIONS MIN TYP MAX UNITS ODI, SCI Input Bias Current 2 na ODI, SCI Comparator Propagation Delay in Fault-Trip Direction 20mV input overdrive 2 µs ODI Delay ODSCDLY=0x ms SCI Delay ODSCDLY=0x μs SCI Service-Mode Entry Current -3-2 ma CHARGE AND DISCHARGE FET DRIVERS DIS Source Current V BATT = 20V, V BATT - V DIS = 3V ma CHG Source Current V PCKP = 20V, V PCKP - V CHG = 3V ma CHG, DIS Output Sink Current V PCKP = V BATT = 20V, V DIS = V BATT - V CLAMP + 2V, ma V CHG = V PCKP - V CLAMP + 2V, CHG, DIS Pull-Up Resistance V BATT = 20V, V BATT - V DIS = 0.5V, V PCKP = 20V, V PCKP - V CHG = 0.5V 4 MW DIS Output Voltage High V BATT - V DIS V CHG Output Voltage High V PCKP - V CHG V DIS Clamp Voltage (V CLAMP ) V BATT - V DIS V BATT = 20V, no load V CHG Clamp Voltage (V CLAMP ) V PCKP - V CHG V PCKP = 20V, no load V DIS, CHG Voltage Output Low No load, V BATT = V PCKP = 4V 1.2 V INSTRUCTION OSCILLATOR Frequency 2.7V < V DD < 3.6V MHz INTERNAL TIMER OSCILLATOR kHz Oscillator Accuracy 12-cycle average % PORT A LOGIC INPUTS/OUTPUTS PA[7:0] Input Voltage Low 2.7V < V DD < 3.6V 0.8 V Input Voltage High 2.7V < V DD < 3.6V 2.4 V High-Impedance Leakage Current I/O pins programmed to Hi-Z µa Output Voltage Low I SINK = 2mA 0.25 V Output Voltage High I SOURCE = 2mA V DD V MCLR RESET PIN MCLR Output Voltage Low I SINK = 1mA, and V BATT = V DD = 2.5V 0.2 V V MCLR Output Voltage High I SOURCE = 0, V BATT = V DD = 3.4V DD - V 0.2 MCLR Pullup Resistance Internally connected from MCLR to V AA kw MCLR Input High Voltage 2.4 V MCLR Input Low Voltage 1 V MCLR Input Hysteresis 300 mv HIGH-VOLTAGE OPEN-DRAIN OUTPUTS (HV0 HV7) Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 11 of 96

12 (VBATT = VPCKP = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = 0 C to +85 C, unless otherwise noted. Typical values are at TA = +25ºC.) PARAMETER CONDITIONS MIN TYP MAX UNITS Output Voltage Low I SOURCE = 10mA V Leakage Current V HV[7:0] = 28V 1 µa HIGH-VOLTAGE PINS IN PARALLEL ACCESS MODE (HV0 HV3) Input High Voltage V DD - V 0.6 Input Low Voltage 0.6 V Input Leakage Current 1 µa SMBus PINS, SCL and SDA Input Low Voltage Clock/Data input low voltage 0.8 V Input High Voltage Clock/Data input high voltage 2.1 V Output Low Voltage I SINK = 2mA 0.4 V Leakage Current V SCL = V SDA = 28V 1 µa Short-Circuit Current V SCL = V SDA = 3.4V 6 50 ma t LOW t R t F SCL V IH V IL t HD:STA t HD:DAT t HIGH tsu:dat t SU:STA t SU:STO SDA V IH V IL t BUF P S S P Figure 1. SMBus Timing Diagram SMBus SLAVE MODE AC CHARACTERISTICS (V BATT = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, Glitch Filter Enabled, T A = 0 C to +85 C. Typical values are at +25ºC.) SYMBOL PARAMETER/CONDITIONS MIN TYP MAX UNITS t TIMEOUT Timeout for maximum clock low time ms t LOW:SEXT Timeout for cumulative slave clock stretch time ms t BUF Bus free time between a stop and start condition 4.7 ms t HD:STA Hold time after a start or repeated start condition 4.0 ms t SU:STA Repeated start setup time 600 ns t SU:STO Stop condition setup time 600 ns t HD:DAT Data Hold time. Transmit ns Receive -30 ns Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 12 of 96

13 (V BATT = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, Glitch Filter Enabled, T A = 0 C to +85 C. Typical values are at +25ºC.) SYMBOL PARAMETER/CONDITIONS MIN TYP MAX UNITS t SU:DAT Data Setup Time Transmit 250 ns Receive 200 t LOW SCL low period 4.7 ms t HIGH SCL high period 4.0 ms t GREJ Glitch pulse width rejected, 1000 ns SMBus MASTER MODE AC CHARACTERISTICS (V BATT = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, Instruction Oscillator is On, Glitch Filter Enabled, T A = 0 C to +85 C. Typical values are at +25ºC.) SYMBOL PARAMETER/CONDITIONS MIN TYP MAX UNITS t BUF Bus free time between a stop and start condition 8.1 µs t LOW:MEXT Timeout for cumulative master clock stretch time ms t HD:STA Hold time after a (repeated) start condition 7.3 µs t SU:STA Repeated start setup time 5.7 µs t SU:STO Stop condition setup time 5.7 µs Transmit 300 ns t HD:DAT Data Hold Time Receive -30 ns Acknowledge 300 ns Transmit 250 ns t SU:DAT Data Setup Time Receive 250 ns f SCL SCL clock frequency (50% typical duty cycle) Acknowledge 250 ns MBAUD= khz MBAUD=011 (default) 50.8 khz MBAUD= khz MBAUD= khz MBAUD= khz MBAUD= khz Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 13 of 96

14 ELECTRICAL CHARACTERISTICS (VBATT = VPCKP = 12V, GND=AGND=CSN=0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = -40 C to +85 C, unless otherwise noted. Note 2.) PARAMETER CONDITIONS MIN TYP MAX UNITS BATT LINEAR REGULATOR (V AA ) Input Voltage Range Includes dropout operation V Output Voltage 4V < V BATT < 28V, 0 < I LOAD < 10mA V Short-Circuit Current V DD = 2.8V, 4V < V BATT < 28V ma PCKP LINEAR REGULATOR (V AA ) Input Voltage Range Includes dropout operation V Output Voltage 4V < V PCKP < 28V, 0 < I LOAD < 10mA V Short-Circuit Current V AA = 0V, 4V< V PCKP < 28V ma Power-Fail Warning Trip Level (PFW) Falling V AA Rising V AA V Power-On Reset Trip Level Falling V AA ( MCLR ) Rising V AA 2.9 V SUPPLY CURRENT (BATT) BATTON = 1 SLEEP + FG + ODSC: Linear Regulator, 32kHz Clock, Fuel Gauge, Precision Reference, ODSC Comparators, MOSFET Drivers in DC State 200 µa CPU RUN + FG + ODSC: Linear Regulator, 32kHz Clock, Fuel Gauge, Precision Reference, ODSC Comparators, MOSFET Drivers in DC state, Instructions Executing SLEEP + AFE/ADC + FG + ODSC: Linear Regulator, 32kHz Clock, Fuel Gauge, Precision Reference, ODSC Comparators, MOSFET Drivers in DC state, ADC Running 4000 µa 1400 µa FUEL GAUGE Charge Coulomb-Counter Accumulation Rate Discharge Coulomb-Counter Accumulation Rate Current Measurement Accuracy (When Using Internal 32kHz Oscillator as a Time Base) ADC Gain Accuracy at Full Scale Input Voltage Range V CSP - V CSN = 125mV 49,000 51,000 Counts/s V CSP - V CSN = -125mV 49,000 51,000 Counts/s V CSP - V CSN = 125mV, Excluding Offset Error % V AA, THRM, AIN0, AIN1, V DD = V AA = V BATT = 3.4V V BN V CSN = V B_P referenced to BN B1P, B2P, B3P, B4P referenced to BN V BN for measurements of B1P, B2P, B3P, B4P % V Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 14 of 96

15 (VBATT = VPCKP = 12V, GND=AGND=CSN=0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = -40 C to +85 C, unless otherwise noted. Note 2.) PARAMETER CONDITIONS MIN TYP MAX UNITS THRM, AIN0, AIN1-0.2 V AA V BN V CSN ADC CELL DIFFERENTIAL VOLTAGE MEASUREMENT ACCURACY (14-BIT RESOLUTION): B4P to B3P V B3P = 12.75V, V B4P = 17V mv B3P to B2P V B2P = 8.5V, V B3P = 12.75V mv B2P to B1P V B1P = 4.25V, V B2P = 8.5V mv B1P to BN V BN = 0V, V B1P = 4.25V mv TEMPERATURE SENSOR THRM Pull High Impedance V AA = V DD = V PCKP = V BATT = 3.4V, 2mA source current 75 W SHORT-CIRCUIT AND OVER-DISCHARGE COMPARATORS ODI, SCI Input Offset Voltage mv ODI Delay ODSCDLY=0x ms SCI Delay ODSCDLY=0x μs CHARGE AND DISCHARGE FET DRIVERS DIS Source Current V BATT = 20V, V BATT - V DIS = 3V 1.6 ma CHG Source Current V PCKP = 20V, V PCKP - V CHG = 3V 1.6 ma CHG, DIS Output Sink Current V PCKP = V BATT = 20V, V DIS = V BATT - V CLAMP + 2V, 0.3 ma V CHG = V PCKP - V CLAMP + 2V, DIS Output Voltage High V BATT - V DIS 0.2 V CHG Output Voltage High V PCKP - V CHG 0.2 V DIS Clamp Voltage (V CLAMP ) V BATT - V DIS V BATT = 20V, no load 5 11 V CHG Clamp Voltage (V CLAMP ) V PCKP - V CHG V PCKP = 20V, no load 5 11 V DIS, CHG Voltage Output Low No load, V BATT = V PCKP = 4V 1.2 V INSTRUCTION OSCILLATOR Frequency 2.7V < V DD < 3.6V MHz INTERNAL TIMER OSCILLATOR kHz Oscillator Accuracy 12-cycle average -2 2 % PORT A LOGIC INPUTS/OUTPUTS PA[7:0] Input Voltage Low 2.7V < V DD < 3.6V 0.8 V Input Voltage High 2.7V < V DD < 3.6V 2.4 V Output Voltage Low I SINK = 2mA 0.25 V Output Voltage High I SOURCE = 2mA HIGH-VOLTAGE OPEN-DRAIN OUTPUTS (HV0 HV7) Output Voltage Low I SOURCE = 10mA 1.4 V SMBus PINS, SCL and SDA Input Low Voltage Clock/Data input low voltage 0.8 V Input High Voltage Clock/Data input high voltage 2.1 V V DD V Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 15 of 96

16 (VBATT = VPCKP = 12V, GND=AGND=CSN=0, VDD = VAA, C VAA = 1µF, instruction oscillator is off, T A = -40 C to +85 C, unless otherwise noted. Note 2.) PARAMETER CONDITIONS MIN TYP MAX UNITS Output Low Voltage I SINK = 2mA 0.4 V Short-Circuit Current V SCL = V SDA = 3.4V 6 50 ma SMBus SLAVE MODE AC CHARACTERISTICS (V BATT = 12V, GND = AGND = CSN = 0, VDD = VAA, CVAA = 1µF, Glitch Filter Enabled, T A = -40 C to +85 C. Note 2.) SYMBOL PARAMETER/CONDITIONS MIN TYP MAX UNITS t TIMEOUT Timeout for maximum clock low time ms t LOW:SEXT Timeout for cumulative slave clock stretch time ms t BUF Bus free time between a stop and start condition 4.7 ms t HD:STA Hold time after a start or repeated start condition 4.0 ms t SU:STA Repeated start setup time 600 ns t SU:STO Stop condition setup time 600 ns t HD:DAT Data Hold time. Transmit ns Receive -30 ns t SU:DAT Data Setup Time Transmit 250 Receive 200 ns t LOW SCL low period 4.7 ms t HIGH SCL high period 4.0 ms SMBus MASTER MODE AC CHARACTERISTICS (V BATT = 12V, GND = AGND = CSN = 0, VDD = VAA, C VAA = 1µF, Instruction Oscillator is On, Glitch Filter Enabled, T A = -40 C to +85 C. Note 2) SYMBOL PARAMETER/CONDITIONS MIN TYP MAX UNITS t BUF Bus free time between a stop and start condition 8.1 µs t LOW:MEXT Timeout for cumulative master clock stretch time ms t HD:STA Hold time after a (repeated) start condition 7.3 µs t SU:STA Repeated start setup time 5.7 µs t SU:STO Stop condition setup time 5.7 µs Transmit 300 ns t HD:DAT Data Hold Time Receive -30 ns Acknowledge 300 ns Transmit 250 ns t SU:DAT Data Setup Time Receive 250 ns Acknowledge 250 ns Note 1: The SCI pin is allowed to go to more negative voltages if the current is limited as shown in the Absolute Maximum Ratings. Note 2: Operation to -40ºC is guaranteed by design, not production tested. Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 16 of 96

17 Typical Operating Characteristics TYPICAL ADC VOLTAGE MEASUREMENT ERROR MAX AVG MIN FUEL GAUGE FREQUENCY vs. INPUT VOLTAGE FULL-SCALE DISCHARGE CHARGE COUNT INCREMENTED DISCHARGE COUNT INCREMENTED FULL-SCALE CHARGE FUEL GAUGE FREQUENCY vs. INPUT VOLTAGE } INPUT VOLTAGE OFFSET }OUTPUT FREQUENCY OFFSET T EM PER A T U R E ( º C ) INPU T V OLTA GE ( mv ) -2 IN PU T V OLT A GE ( m V ) GAIN ERROR vs. FUEL GAUGE INPUT VOLTAGE T A =-40ºC T A =25ºC T A =85ºC IN PU T V OLT A GE ( mv ) Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 17 of 96

18 Pin Description PIN NAME FUNCTION 1 HV0 2 HV1 3 HV2 4 HV3 5 HV4 6 HV5 7 HV6 8 HV7 9 CHG 10 PCKP High-Voltage Outputs. Each open-drain output can be pulled up as high as 28V using a pullup resistor and can be used for driving LEDs. See the High-Voltage Output Port section for more information. Charge-Protection MOSFET Driver. CHG drives an external P-channel MOSFET that allows/prevents the battery from receiving current. CHG is driven to PCKP when off and typically provides 8V gate drive when on. See the CHG and DIS Output Driver Description section for more information. Pack+ Connection. The system load and battery charger connect to the battery pack at PCKP. PCKP provides power to the IC and V AA linear regulator when BATTON = 0 (see the Linear Regulators for System Power and Startup section). 11 AGND Analog Ground Connection. Connect AGND to GND at a single point to form a star ground. 12 V AA 3.4V Linear Regulator Output. Bypass V AA to AGND with a 0.47μF capacitor close to the IC. Connect V AA to V DD. 13 DIS Discharge Protection MOSFET Driver. DIS drives an external P-channel MOSFET that allows/prevents the battery from delivering current. DIS is driven to BATT when off and typically provides 8V gate drive when on. See the CHG and DIS Output Driver Description section for more information. 14 BATT Battery Connection. Connect BATT to the battery. BATT should not be exposed to the outside of the battery pack. BATT provides power to the IC and V AA linear regulator during normal operation when BATTON = 1 (see the Linear Regulators for System Power and Startup section). 15 B4P Positive Terminal of Top Cell. B4P senses the voltage at the top of the battery stack. 16 B3P Positive Terminal of Third Cell. B3P senses the voltage at the positive terminal of the third cell. Connect B1P, B2P, and B3P for 2 cell packs. Connect B2P and B3P for 3 cell packs. 17 B2P Positive Terminal of Second Cell. B2P senses the voltage at the positive terminal of the second cell. 18 B1P Positive Terminal of First Cell. B1P senses the voltage at the positive terminal of the first cell. 19 BN Negative Terminal of Battery. BN senses the voltage at the negative terminal of the battery. 20 CSP Battery Current-Sense Positive Input. Battery current for fuel gauging is sensed from CSP to CSN. 21 CSN Battery Current-Sense Negative Input. Battery current for fuel gauging is sensed from CSP to CSN. Connect CSN to AGND. 22 ODI Over-Discharge Current Sense. Connect a resistive voltage divider from a reference to the Current Sense Resistor, with ODI as the center-tap. Over-discharge is detected when V ODI is below CSN for a set time. See the Overcurrent Protection and Protection MOSFET Drivers section for more information. 23 SCI 24 THRM 25 AIN0 26 AIN1 27 MCLR Short-Circuit Current Sense. Connect a resistor-divider from a reference to the Current Sense Resistor, with SCI as the center-tap. A short circuit is detected when V SCI is below CSN for a set time. See the Overcurrent Protection and Protection MOSFET Drivers section for more information. Drive this pin 3mA below ground during reset to place the part into Service Mode. Thermistor Connection and General-Purpose ADC Channel. THRM can be configured to connect to V AA using an internal 100W switch or left floating for general-purpose ADC measurements. See the AIN and THRM Pins section for more information. General-Purpose ADC Channels. See the AIN and THRM Pins section for more information. Manual Clear/Reset Input. Pull MCLR low to reset the MAX1781. MCLR is pulled low internally during power failure or watchdog timeout. See the Linear Regulators for System Power Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 18 of 96

19 and Startup section for more information. 28 ICLK Instruction Oscillator Input. Connect ICLK to GND. Not used in normal operation. 29 V PP0 Charge-Pump Output. Do not connect this pin NC1 NC7 No Connection. Not internally connected. 37 PA0 38 PA1 39 PA2 40 PA3 41 PA4 42 PA5 43 PA6 44 PA7 Port A Input/Output. Each pin PA0 PA7 can be independently configured as either a logic-level input or output. PA3 and PA4 can also be configured as edge-triggered interrupts. PA6 and PA7 can be configured to output the status of the CHG and DIS MOSFETs. See the Port A section for more information. 45 V DD Digital Power Supply. Connect V DD to V AA. Bypass V DD with a 0.47μF capacitor to GND. 46 GND Digital Ground. Connect GND to AGND. 47 SDA SMBus Open-Drain Data Input/Output. See the SMBus Interface section for more information. 48 SCL SMBus Open-Drain Clock Input/Output. In master mode SCL is an output. In slave mode it is an input. See the SMBus Interface section for more information. Paddle AGND Connect the exposed paddle to AGND. Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 19 of 96

20 R38 510W R3 1MW M1 + V AA C1 0.1mF M2 M3 C6 0.1mF C R7 R8 BN R5 R6 C5 0.1mF R17 100W CHG HV5 PCKP SCI ODI ICLK SCL DIS BATT B4P HV7 B3P HV6 R26 100W C7 0.1mF R27 100W C8 0.1m F R30 M10 R34 R31 M11 P P CELL #4 CELL #3 D R16 1MW BATT R15 1MW R21 1kW R19 100W SDA MAX1781 B2P PA3 R28 100W C9 0.1m F N M8 R35 R32 M12 P CELL #2 VAA R14 LED1 LED2 LED3 LED4 LED5 HV0 HV1 HV2 HV3 HV4 B1P PA2 R29 100W C10 0.1m F R36 R33 M13 P N M9 R37 CELL #1 S1 DISPLAY CAPACITY R9 PA5 THRM AIN0 BN CSP RS1 0.01W C11 0.1mF t AIN1 CSN MCLR C4 0.01mF Pins Not Shown: PA0-4, PA6, PA7, HV6,HV7 VAA AGND VDD GND C2 0.47mF C3 0.47mF VAA - Figure 2. Max1781 Typical Application Circuit Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Page 20 of 96