Chapter 12: Multiprocessor Architectures. Lesson 04: Interconnect Networks
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1 Chapter 12: Multiprocessor Architectures Lesson 04: Interconnect Networks
2 Objective To understand different interconnect networks To learn crossbar switch, hypercube, multistage and combining networks 2
3 Crossbar Switches (Matrix Switch) for dynamic interconnections 3
4 Crossbar switch 4
5 Crossbar switches for dynamic interconnections Each processor has switch to memory bus horizontally and processor-to-switch links vertically A switch S having four I/O paths (0, 1, 2, 3) provides the following twelve paths (assume even paths horizontal, odd paths vertical): 0-2, 0-1, 0-3, 1-0, , 2-0, 2-1, 2-3, 3-0, 3-1, 3-2 5
6 Hypercube Networks 6
7 Hypercube (3-cube) networks 7
8 Hypercube (n-cube) networks 8
9 Multistage Networks 9
10 Multistage (Butterfly) network m stage n switches multistage 10
11 Butterfly connection The 0 th output of stage j switch k connects to 1 st input of stage j +1 switch k 1 and 1 st t output of stage j switch k 1 connects to 0 th input of stage j + 1 switch k 11
12 Multistage (Butterfly) connection at 0 th stage 12
13 Butterfly and Shuffle connections in Banyan-Delta Networks 13
14 Multistage Network Banyan network m stage n switches multistage network example with butterfly and shuffle connections 14
15 Butterfly and Shuffle connections in Banyan-Delta Networks Butterfly help in one switch up or down, when the route path changes from stage j to j + 1 One switch up or down, when the route path changes from stage j to j
16 Butterfly and Shuffle connections in Banyan-Delta Networks Shuffle helps the 1 st output of stage j switch k connects to 0 th input of stage j +1 switch k + i and 0 th output of stage j switch k + i 1 connects to 1 st input of stage j + 1 switch k 16
17 Multistage (Butterfly) and Shuffle connections at the stages 17
18 Banyan Network Connections table for 4 14 stages 18
19 Combining in Networks 19
20 Combining network bus requests 20
21 Summary 21
22 We Learnt Crossbar switch interconnects for multiprocessor networks Hypercube interconnects Multistage interconnects Combining the interconnect network memory requests 22
23 End of Lesson 04 on Interconnect Networks 23
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