Technical Writing - Indexing and Falling Edge in Microsoft Windows

Transcription

1 R2 Unbuffered SOIMM 2pin Unbuffered SOIMM based on 2Gb A-die 64-bit Non- 83SP with Lead-Free and Halogen-Free (RoHS compliant) INFORMAION IN HIS OUMN IS PROVI IN RLAION O SAMSUNG PROUS, AN IS SUBJ O HANG WIHOU NOI. NOHING IN HIS OUMN SHALL B ONSRU AS GRANING ANY LINS, XPRSS OR IMPLI, BY SOPPL OR OHR- WIS, O ANY INLLUAL PROPRY RIGHS IN SAMSUNG PROUS OR HNOL- OGY. ALL INFORMAION IN HIS OUMN IS PROVI ON AS "AS IS" BASIS WIHOU GUARAN OR WARRANY OF ANY IN.. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung lectronics reserves the right to change products or specification without notice. of 7

2 able of ontents. R2 Unbuffered IMM Ordering Information Features Address onfiguration Pin onfigurations (Front side/back side) Pin escription Input/Output Function escription Functional Block iagram : 4GB, 52Mx64 Module - M475267AZ(H) Absolute Maximum Ratings A & Operating onditions Recommended Operating onditions (SSL -.8) Operating emperature ondition Input Logic Level Input A Logic Level A Input est onditions I Specification Parameters efinition.... Operating urrent able : M475267AZ(H)3: 52Mx64 4GB Module Input/Output apacitance lectrical haracteristics & A iming for R2-8/667/ Refresh Parameters by evice ensity Speed Bins and L, tr, trp, tr and tras for orresponding Bin iming parameters by speed grade (R2-8 and R2-667) iming parameters by speed grade (R2-533) Physical imensions : st.52mbx8 based 52Mx64 Module (2 Ranks) of 7

3 Revision History Revision Month Year History. ecember 27 - Initial Release. ecember 27 - ypo orrection. July 28 - Applied J update(js79-2) on A timing table.2 September 28 - rased the product of 8Mbps L5 speed 3 of 7

4 . R2 Unbuffered IMM Ordering Information Part Number ensity Organization omponent omposition Note :. Z of Part number(th digit) stands for Lead-Free products. 2. H of Part number(2th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products of Part number(2th digit) stands for ummy Pad PB products. Number of Rank M475267AZ(H)3-(L)F7/6/5 4GB 52Mx64 st.52mx8 (44G274QA-(L)F7/6/5)*8 2 3mm Height 2. Features Performance range F7 (R2-8) 6 (R2-667) 5 (R2-533) Unit Speed@L3-4 4 Mbps Speed@L Mbps Speed@L Mbps Speed@L Mbps L-tR-tRP J standard V =.8V ±.V Power Supply V Q =.8V ±.V 267MHz f for 533Mb/sec/pin, 333MHz f for 667Mb/sec/pin, 4MHz f for 8Mb/sec/pin 8 Banks Posted AS Programmable AS Latency: 3, 4, 5, 6 Programmable Additive Latency:,, 2, 3, 4, 5 Write Latency(WL) = Read Latency(RL) - Burst Length: 4, 8(Interleave/Nibble sequential) Programmable Sequential / Interleave Burst Mode Bi-directional ifferential ata-strobe (Single-ended data-strobe is an optional feature) Off-hip river(o) Impedance Adjustment On ie ermination with selectable values(5/75/5 ohms or disable) Average Refresh Period 7.8us at lower than a AS 85, 3.9us at 85 < AS < 95 - Support High emperature Self-Refresh rate enable feature Package: 83ball SP - st.52mx8 All of base components are Lead-Free, Halogen-Free, and RoHS compliant Note : For detailed operation, please refer to Samsung s evice operation & iming diagram. 3. Address onfiguration Organization Row Address olumn Address Bank Address Auto Precharge 256Mx8(2Gb) based Module A-A4 A-A9 BA-BA2 A 4 of 7

5 4. Pin onfigurations (Front side/back side) Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back V RF 2 V SS M2 A 2 A 5 Q42 52 Q46 3 V SS 4 Q4 53 V SS 54 V SS 3 V 4 V 53 Q43 54 Q47 5 Q 6 Q5 55 Q8 56 Q22 5 A/AP 6 BA 55 V SS 56 V SS 7 Q 8 V SS 57 Q9 58 Q23 7 BA 8 RAS 57 Q48 58 Q52 9 V SS M 59 V SS 6 V SS 9 W S 59 Q49 6 Q53 2 V SS 6 Q24 62 Q28 V 2 V 6 V SS 62 V SS 3 4 Q6 63 Q25 64 Q29 3 AS 4 O 63 N, S 64 5 V SS 6 Q7 65 V SS 66 V SS 5 N/S 6 A3 65 V SS 66 7 Q2 8 V SS 67 M V 8 V V SS 9 Q3 2 Q2 69 N N/O 2 N M6 2 V SS 22 Q3 7 V SS 72 V SS 2 V SS 22 V SS 7 V SS 72 V SS 23 Q8 24 V SS 73 Q26 74 Q3 23 Q32 24 Q36 73 Q5 74 Q54 25 Q9 26 M 75 Q27 76 Q3 25 Q33 26 Q37 75 Q5 76 Q55 27 V SS 28 V SS 77 V SS 78 V SS 27 V SS 28 V SS 77 V SS 78 V SS N/ M4 79 Q56 8 Q V 82 V V SS 8 Q57 82 Q6 33 V SS 34 V SS 83 N 84 N 33 V SS 34 Q38 83 V SS 84 V SS 35 Q 36 Q4 85 BA2 86 A4 35 Q34 36 Q39 85 M Q 38 Q5 87 V 88 V 37 Q35 38 V SS 87 V SS V SS 4 V SS 89 A2 9 A 39 V SS 4 Q44 89 Q58 9 V SS 4 V SS 42 V SS 9 A9 92 A7 4 Q4 42 Q45 9 Q59 92 Q62 43 Q6 44 Q2 93 A8 94 A6 43 Q4 44 V SS 93 V SS 94 Q63 45 Q7 46 Q2 95 V 96 V 45 V SS SA 96 V SS 47 V SS 48 V SS 97 A5 98 A4 47 M SL 98 SA N 99 A3 A2 49 V SS 5 V SS 99 V SP 2 SA Note : N = No onnect; N, S(pin 63)is for bus analysis tool and is not connected on normal memory modules. 5. Pin escription Pin Name escription Pin Name escription, lock Inputs, positive line SA SP ata Input/Output, lock Inputs, negative line SA,SA SP address, lock nables Q~Q63 ata Input/Output RAS Row Address Strobe M~M7 ata Masks AS olumn Address Strobe ~7 ata strobes W Write nable ~7 ata strobes complement S,S hip Selects S Logic Analyzer specific test pin (No connect on So-IMM) A~A9, A~A4 Address Inputs V ore and I/O Power A/AP Address Input/Autoprecharge V SS Ground BA~BA2 SRAM Bank Address V RF Input/Output Reference O,O On-die termination control V SP SP Power SL Serial Presence etect(sp) lock Input N Spare pins, No connect, lock Inputs, positive line SA SP ata Input/Output *he V and V Q pins are tied to the single power-plane on PB. 5 of 7

6 6. Input/Output Function escription ype escription S-S RAS, AS, W Input Input Input Input he system clock inputs. All address and command lines are sampled on the cross point of the rising edge of and falling edge of. A elay Locked Loop (LL) circuit is driven from the clock input and output timing for read operations is synchronized to the input clock. Activates the signal when high and deactivates the signal when low, By deactivating the clocks, low initiates the Power own mode or the Self Refesh mode. nables the associated command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank is selected by S, Rank is selected by S. Ranks are also called Physical banks. When sampled at the cross point of the rising edge of and falling edge of, AS, RAS, and W define the operation to be executed by the SRAM. BA~BA2 Input Selects which internal bank is activated. O~O A~A9, A/AP, A~A4 Input Input Asserts on-die termination for Q, M,, and signals if enabled via the xtended Mode Register Set (MRS). uring a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of and falling edge of. uring a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of and falling edge of. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. uring a Precharge command cycle, AP is used in conjunction with BA-BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA- BAn inputs. If AP is low, then BA-BAn are used to define which bank to precharge. Q~Q63 In/Out ata Input/Output pins. M~M7 ~7 ~7 Input In/Out he data write masks, associated with one data byte. In Write mode, M operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, M lines have no effect. he data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the s and is sent at the leading edge of the data window. signals are complements, and timing is relative to the crosspoint of respective and If the module is to be operated in single ended strobe mode, all signals must be tied on the system board to V SS and R2 SRAM mode registers programmed appropriately. V,V SP,V SS Supply Power supplies for core, I/O, Serial Presence etect, and ground for the module. SA SL In/Out Input his is a bidirectional pin used to transfer data into or out of the SP PROM. A resistor must be connected to V to act as a pull up. his signal is used to clock data into and out of the SP PROM. A resistor may be connected from SL to V to act as a pull up. SA~SA Input Address pins used to select the Serial Presence etect base address. S In/Out he S pin is reserved for bus analysis tools and is not connected on normal memory modules(so- IMMs). 6 of 7

7 7. Functional Block iagram : 4GB, 52Mx64 Module - M475267AZ(H)3 (Populated as 2 ranks of x8 s) 3Ω + 5% O S O S M Q Q Q2 Q3 Q4 Q5 Q6 Q7 M I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S O M I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S O S O M4 M M Q32 I/O I/O Q33 Q34 Q35 Q36 Q37 Q38 Q39 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 4 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S O 2 M Q8 Q9 Q Q Q2 Q3 Q4 Q5 M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S O M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S O M5 Q4 Q4 Q42 Q43 Q44 Q45 Q46 Q47 M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S O 5 M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S O M2 Q6 Q7 Q8 Q9 Q2 Q2 Q22 Q23 M I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S 2 O M I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S O 6 6 M6 Q48 Q49 Q5 Q5 Q52 Q53 Q54 Q55 M I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S O 6 M I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S O M3 Q24 Q25 Q26 Q27 Q28 Q29 Q3 Q3 M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S 3 O M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S O 7 7 M7 Q56 Q57 Q58 Q59 Q6 Q6 Q62 Q63 M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S O 7 M I/O 8 I/O 9 I/O I/O I/O 2 I/O 3 I/O 4 I/O 5 S O 5 BA - BA2 A - A4 RAS AS W Ω + 5% s - 5 s - 5 s - 5 s - 5 s - 5 SL SA SA SL A A A2 SP WP SA * lock Wiring lock Input s */ */ 8 s 8 s * Wire per lock Loading able/wiring iagrams V SP V RF V Serial P s - 5 s - 5, V and V Q Note :. Q,M, / resistors : 22 Ohms ± 5%. 2. BAx, Ax, RAS, AS, W resistors :. Ohms ± 5%. V SS s - 5, SP 7 of 7

8 8. Absolute Maximum Ratings Parameter Rating Notes V Voltage on V pin relative to V SS -. V ~ 2.3 V V V Q Voltage on V Q pin relative to V SS -.5 V ~ 2.3 V V V L Voltage on V L pin relative to V SS -.5 V ~ 2.3 V V V IN, V OU Voltage on any pin relative to V SS -.5 V ~ 2.3 V V SG Storage emperature -55 to +, 2 Note :. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. his is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. xposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage emperature is the case surface temperature on the center/top side of the RAM. For the measurement conditions, please refer to JS5-2 standard. 9. A & Operating onditions 9. Recommended Operating onditions (SSL -.8) Parameter Min. Rating yp. Max. V Supply Voltage V Notes V L Supply Voltage for LL V 4 V Q Supply Voltage for Output V 4 V RF Input Reference Voltage.49*V Q.5*V Q.5*V Q mv,2 V ermination Voltage V RF -.4 V RF V RF +.4 V 3 Rating Parameter Min. Max. Notes V SP ore Supply Voltage V 5 Note : here is no specific device V supply voltage requirement for SSL-.8 compliance. However under all conditions V Q must be less than or equal to V.. he value of V RF may be selected by the user to provide optimum noise margin in the system. ypically the value of V RF is expected to be about.5 x V Q of the transmitting device and V RF is expected to track variations in V Q. 2. Peak to peak A noise on V RF may not exceed +/-2% V RF (). 3. V of transmitting device must track V RF of receiving device. 4. A parameters are measured with V, V Q and V L tied together. 5. SOIMMs that include an optional temperature sensor may require a restricted V SP operating voltage range for proper operation of the temperature sensor. Refer to the thermal sensor specification for details regarding the supported voltage range. All other functions of the SOIMM SP are supported across the full V SP range. 8 of 7

9 9.2 Operating emperature ondition Parameter Rating Notes OPR Operating emperature to 95, 2 Note :. Operating emperature is the case surface temperature on the center/top side of the RAM. For the measurement conditions, please refer to JS5.2 standard. 2. At operation temperature range, doubling refresh commands in frequency to a 32ms period ( trfi=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an MRS command is required to change internal refresh rate. 9.3 Input Logic Level Parameter Min. Max. Notes V IH () input logic high V RF +.25 V Q +.3 V V IL () input logic low -.3 V RF -.25 V 9.4 Input A Logic Level R2-533 R2-667, R2-8 Parameter Min. Max. Min. Max. V IH (A) A input logic high V RF V RF +.2 V V IL (A) A input logic low - V RF -.25 V RF -.2 V 9.5 A Input est onditions ondition Value Notes V RF Input reference voltage.5 * V Q V V SWING(MAX) Input signal maximum peak to peak swing. V SLW Input signal minimum slew rate. V/ns 2, 3 Note :. Input waveform timing is referenced to the input signal crossing through the V IH/IL (A) level applied to the device under test. 2. he input signal minimum slew rate is to be maintained over the range from V RF to V IH (A) min for rising edges and the range from V RF to V IL (A) max for falling edges as shown in the below figure. 3. A timings are referenced with input waveforms switching from V IL (A) to V IH (A) on the positive transitions and V IH (A) to V IL (A) on the negative transitions. V SWING(MAX) delta F delta R V Q V IH (A) min V IH () min V RF V IL () max V IL (A) max V SS Falling Slew = V RF - V IL (A) max Rising Slew = V IH (A) min - V RF delta F delta R < A Input est Signal Waveform > 9 of 7

10 . I Specification Parameters efinition (I values are for full operating range of Voltage and emperature) Proposed onditions Note I I I2P I2Q I2N I3P I3N I4W I4R I5B I6 I7 Operating one bank active-precharge current; t = t(i), tr = tr(i), tras = trasmin(i); is HIGH, S is HIGH between valid commands; Address bus inputs are SWIHING; ata bus inputs are SWIHING Operating one bank active-read-precharge current; IOU = ; BL = 4, L = L(I), AL = ; t = t(i), tr = tr (I), tras = trasmin(i), tr = tr(i); is HIGH, S is HIGH between valid commands; Address bus inputs are SWIHING; ata pattern is same as I4W Precharge power-down current; All banks idle; t = t(i); is LOW; Other control and address bus inputs are SABL; ata bus inputs are FLOAING Precharge quiet standby current; All banks idle; t = t(i); is HIGH, S is HIGH; Other control and address bus inputs are SABL; ata bus inputs are FLOAING Precharge standby current; All banks idle; t = t(i); is HIGH, S is HIGH; Other control and address bus inputs are SWIHING; ata bus inputs are SWIHING Active power-down current; All banks open; t = t(i); is LOW; Other control and address bus inputs are SABL; ata bus inputs are FLOAING Fast PN xit MRS(2) = Slow PN xit MRS(2) = Active standby current; All banks open; t = t(i), tras = trasmax(i), trp = trp(i); is HIGH, S is HIGH between valid commands; Other control and address bus inputs are SWIHING; ata bus inputs are SWIHING Operating burst write current; All banks open, ontinuous burst writes; BL = 4, L = L(I), AL = ; t = t(i), tras = trasmax(i), trp = trp(i); is HIGH, S is HIGH between valid commands; Address bus inputs are SWIHING; ata bus inputs are SWIHING Operating burst read current; All banks open, ontinuous burst reads, IOU = ; BL = 4, L = L(I), AL = ; t = t(i), tras = trasmax(i), trp = trp(i); is HIGH, S is HIGH between valid commands; Address bus inputs are SWIH- ING; ata pattern is same as I4W Burst auto refresh current; t = t(i); Refresh command at every trf(i) interval; is HIGH, S is HIGH between valid commands; Other control and address bus inputs are SWIHING; ata bus inputs are SWIHING Self refresh current; and at V;.2V; Other control and address bus inputs are FLOAING; ata bus inputs are FLOAING Normal Low Power Operating bank interleave read current; All bank interleaving reads, IOU = ; BL = 4, L = L(I), AL = tr(i)-*t(i); t = t(i), tr = tr(i), trr = trr(i), tfaw = tfaw(i), tr = *t(i); is HIGH, S is HIGH between valid commands; Address bus inputs are SABL during SLs; ata pattern is same as I4R; Refer to the following page for detailed timing conditions of 7

11 . Operating urrent able : M475267AZ(H)3: 52Mx64 4GB Module (A= o, V =.9V) 8@L=6 667@L=5 533@L=4 F7 LF7 6 L6 5 L5 Notes I,24,6,8 I,44,32,24 I2P I2Q I2N I3P-F I3P-S I3N,2, 92 I4W,84,64,44 I4R 2,8,8,6 I5 2,72 2,52 2,4 I I7 3,28 3, 2,72 * Module I was calculated on the basis of component I and can be differently measured according to Q loading cap. of 7

12 2. Input/Output apacitance (V =.8V, V Q =.8V, A =25 o ) Parameter Min Max Non- M475267AZ(H)3 Input capacitance, and - 48 Input capacitance,, S, Addr, RAS, AS, W I - 42 Input/output capacitance, Q, M,, IO(533) - IO(667/8) - 9 * M is internally loaded to match Q and identically. pf 3. lectrical haracteristics & A iming for R2-8/667/533 ( < OPR < 95 ; V Q =.8V +.V; V =.8V +.V) 3. Refresh Parameters by evice ensity Parameter 256Mb 52Mb Gb 2Gb 4Gb Refresh to active/refresh command time trf ns AS µs Average periodic refresh interval trfi 85 < AS µs 3.2 Speed Bins and L, tr, trp, tr and tras for orresponding Bin Speed R2-8(F7) R2-667(6) R2-533(5) Bin(L - tr - trp) Parameter min max min max min max t, L= ns t, L= ns t, L= ns t, L= tr ns trp ns tr ns tras ns 2 of 7

13 3.3 iming parameters by speed grade (R2-8 and R2-667) (Refer to notes for informations related to this table at the component datasheet) Parameter R2-8 R2-667 min max min max Q output access time from / ta ps 4 output access time from / t ps 4 Average clock HIGH pulse width th(avg) t(avg) 35,36 Average clock LOW pulse width tl(avg) t(avg) 35,36 half pulse period thp Min(tL(abs), th(abs)) x Min(tL(abs), th(abs)) Notes x ps 37 Average clock period t(avg) ps 35,36 Q and M input hold time th(base) 25 x 75 x ps 6,7,8,2,28,3 Q and M input setup time ts(base) 5 x x ps 6,7,8,2,28,3 ontrol & Address input pulse width for each input tipw.6 x.6 x t(avg) Q and M input pulse width for each input tipw.35 x.35 x t(avg) ata-out high-impedance time from / thz x ta(max) x ta(max) ps 8,4 / low-impedance time from / tlz() ta(min) ta(max) ta(min) ta(max) ps 8,4 Q low-impedance time from / tlz(q) 2* ta(min) ta(max) 2* ta(min) ta(max) ps 8,4 -Q skew for and associated Q signals tq x 2 x 24 ps 3 Q hold skew factor tqhs x 3 x 34 ps 38 Q/ output hold time from tqh thp - tqhs x thp - tqhs x ps 39 latching rising transitions to associated clock edges ts t(avg) 3 input HIGH pulse width th.35 x.35 x t(avg) input LOW pulse width tl.35 x.35 x t(avg) falling edge to setup time tss.2 x.2 x t(avg) 3 falling edge hold time from tsh.2 x.2 x t(avg) 3 Mode register set command cycle time tmr 2 x 2 x n MRS command to O update delay tmo 2 2 ns 32 Write postamble twps t(avg) Write preamble twpr.35 x.35 x t(avg) Address and control input hold time tih(base) 25 x 275 x ps 5,7,9,23,29 Address and control input setup time tis(base) 75 x 2 x ps 5,7,9,22,29 Read preamble trpr t(avg) 9,4 Read postamble trps t(avg) 9,42 Activate to activate command period for B page size products trr 7.5 x 7.5 x ns 4,32 Activate to activate command period for 2B page size products trr x x ns 4,32 3 of 7

14 Parameter R2-8 R2-667 min max min max Four Activate Window for B page size products tfaw 35 x 37.5 x ns 32 Four Activate Window for 2B page size products tfaw 45 x 5 x ns 32 AS to AS command delay t 2 x 2 x n Write recovery time twr 5 x 5 x ns 32 Auto precharge write recovery + precharge time tal WR + tnrp x WR + tnrp x n 33 Internal write to read command delay twr 7.5 x 7.5 x ns 24,32 Internal read to precharge command delay trp 7.5 x 7.5 x ns 3,32 xit self refresh to a non-read command txsnr trf + x trf + x ns 32 xit self refresh to a read command txsr 2 x 2 x n xit precharge power down to any command txp 2 x 2 x n xit active power down to read command txar 2 x 2 x n xit active power down to read command (slow exit, lower power) txars 8 - AL x 7 - AL x n,2 minimum pulse width (HIGH and LOW pulse width) t 3 x 3 x n 27 O turn-on delay taon n 6 O turn-on taon ta(min) ta(max)+.7 ta(min) ta(max)+.7 ns 6,6,4 O turn-on (Power-own mode) taonp ta(min)+2 2*t(avg) +ta(max)+ ta(min)+2 2*t(avg) +ta(max)+ O turn-off delay taof n 7,45 O turn-off taof ta(min) ta(max)+.6 ta(min) ta(max)+.6 ns 7,43,45 O turn-off (Power-own mode) taofp ta(min)+2 2.5*t(avg)+ ta(max)+ ta(min)+2 2.5*t(avg)+ ta(max)+ O to power down entry latency tanp 3 x 3 x n O power down exit latency taxp 8 x 8 x n O drive mode output delay toi 2 2 ns 32 Minimum time clocks remains ON after asynchronously drops LOW telay tis+t(avg) +tih x tis+t(avg) +tih ns ns Notes x ns 5 4 of 7

15 3.4 iming parameters by speed grade (R2-533) (Refer to notes for informations related to this table at the component datasheet) R2-533 Parameter Notes min max Q output access time from / ta -5 5 ps output access time from / t ps HIGH pulse width th t LOW pulse width tl t half pulse period thp Min(tL, th) x ps,2 lock cycle time, L=x t ps 5 Q and M input hold time (differential strobe) th(base) 225 x ps 6,7,8,2,28 Q and M input setup time (differential strobe) ts(base) x ps 6,7,8,2,28 Q and M input hold time (single-ended strobe) th(base) -25 x ps 6,7,8,26 Q and M input setup time (single-ended strobe) ts(base) -25 x ps 6,7,8,25 ontrol & Address input pulse width for each input tipw.6 x t Q and M input pulse width for each input tipw.35 x t ata-out high-impedance time from / thz x ta(max) ps 8 (/) low-impedance time from / tlz() ta(min) ta(max) ps 8 Q low-impedance time from / tlz(q) 2* ta(min) ta(max) ps 8 -Q skew for and associated Q signals tq x 3 ps 3 Q hold skew factor tqhs x 4 ps 2 Q/ output hold time from tqh thp - tqhs x ps latching rising transitions to associated clock edges ts t input HIGH pulse width th.35 x t input LOW pulse width tl.35 x t falling edge to setup time tss.2 x t falling edge hold time from tsh.2 x t Mode register set command cycle time tmr 2 x t MRS command to O update delay tmo 2 ns Write postamble twps.4.6 t Write preamble twpr.35 x t Address and control input hold time tih(base) 375 x ps 5,7,9,23 Address and control input setup time tis(base) 25 x ps 5,7,9,22 Read preamble trpr.9. t 9 Read postamble trps.4.6 t 9 Active to active command period for B page size products trr 7.5 x ns 4 Active to active command period for 2B page size products trr x ns 4 5 of 7

16 Parameter min R2-533 Four Activate Window for B page size products tfaw 37.5 x ns Four Activate Window for 2B page size products tfaw 5 x ns AS to AS command delay t 2 x t Write recovery time twr 5 x ns Auto precharge write recovery + precharge time tal WR+tRP x t 4 Internal write to read command delay twr 7.5 x ns 24 Internal read to precharge command delay trp 7.5 x ns 3 xit self refresh to a non-read command txsnr trf + x ns xit self refresh to a read command txsr 2 x t xit precharge power down to any non-read command txp 2 x t xit active power down to read command txar 2 x t xit active power down to read command (slow exit, lower power) txars 6 - AL x t,2 minimum pulse width (HIGH and LOW pulse width) t 3 x t 27 O turn-on delay taon 2 2 t 6 O turn-on taon ta(min) ta(max)+ ns 6 O turn-on (Power-own mode) taonp ta(min)+2 2t+ ta(max)+ ns O turn-off delay taof t 7,44 O turn-off taof ta(min) max ta(max) +.6 Notes ns 7,44 O turn-off (Power-own mode) taofp ta(min)+2 2.5t+ ta(max)+ ns O to power down entry latency tanp 3 x t O power down exit latency taxp 8 x t O drive mode output delay toi 2 ns 32 Minimum time clocks remains ON after asynchronously drops LOW telay tis+t+tih x ns 5 6 of 7

17 4. Physical imensions : st.52mbx8 based 52Mx64 Module (2 Ranks) - M475267AZ(H)3 : Millimeters 67.6 mm 3.8 mm max SP ± a 47.4 b mm max 2 a mm AIL a AIL b FRON SI ±..5 ±. 4. ±. BA SI. ±.5.2 ± ±.. ±.5.8 ± ± ±.3 he used device is st.52m x8, FBGA. Part NO : 44G274QA 7 of 7