Octal bus transceiver with direction pin; 3-state

Similar documents
INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook Jun 30

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

INTEGRATED CIRCUITS DATA SHEET. SAA digit LED-driver with I 2 C-Bus interface. Product specification File under Integrated Circuits, IC01

4-bit binary full adder with fast carry CIN + (A1 + B1) + 2(A2 + B2) + 4(A3 + B3) + 8(A4 + B4) = = S1 + 2S2 + 4S3 + 8S4 + 16COUT

74HC138; 74HCT to-8 line decoder/demultiplexer; inverting

8-bit binary counter with output register; 3-state

74ALVC bit dual supply translating transceiver; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

74HC02; 74HCT General description. 2. Features and benefits. Ordering information. Quad 2-input NOR gate

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74HC238; 74HCT to-8 line decoder/demultiplexer

74HC154; 74HCT to-16 line decoder/demultiplexer

Triple single-pole double-throw analog switch

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

Hex buffer with open-drain outputs

74HC573; 74HCT General description. 2. Features and benefits. Octal D-type transparent latch; 3-state

74HCU General description. 2. Features and benefits. 3. Ordering information. Hex unbuffered inverter

HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate

74HC4067; 74HCT channel analog multiplexer/demultiplexer

8-channel analog multiplexer/demultiplexer

MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop

74HC107; 74HCT107. Dual JK flip-flop with reset; negative-edge trigger

74HC595; 74HCT General description. 2. Features and benefits. 3. Applications

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

74HC377; 74HCT General description. 2. Features and benefits. 3. Ordering information

3-to-8 line decoder, demultiplexer with address latches

74HC165; 74HCT bit parallel-in/serial out shift register

High-Speed, Low r ON, SPST Analog Switch (1-Bit Bus Switch)

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC4040; 74HCT stage binary ripple counter

The 74LVC1G11 provides a single 3-input AND gate.

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register

Low-power configurable multiple function gate

74HC4066; 74HCT4066. Quad single-pole single-throw analog switch

74HC175; 74HCT175. Quad D-type flip-flop with reset; positive-edge trigger

DG2302. High-Speed, Low r ON, SPST Analog Switch. Vishay Siliconix. (1-Bit Bus Switch with Level-Shifter) RoHS* COMPLIANT DESCRIPTION FEATURES

74HC595; 74HCT General description. 2. Features and benefits. 3. Applications

74VHC574 Octal D-Type Flip-Flop with 3-STATE Outputs

3-input EXCLUSIVE-OR gate. The 74LVC1G386 provides a 3-input EXCLUSIVE-OR function.

DATA SHEET. HEF40374B MSI Octal D-type flip-flop with 3-state outputs. For a complete data sheet, please also download: INTEGRATED CIRCUITS

1-of-4 decoder/demultiplexer

Quad 2-input NAND Schmitt trigger

How To Control A Power Supply On A Powerline With A.F.F Amplifier

MM74HC273 Octal D-Type Flip-Flops with Clear

DATA SHEET. TDA1518BQ 24 W BTL or 2 x 12 watt stereo car radio power amplifier INTEGRATED CIRCUITS

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

Bus buffer/line driver; 3-state

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

74HC4051; 74HCT channel analog multiplexer/demultiplexer

MM74HC174 Hex D-Type Flip-Flops with Clear

74HC74; 74HCT General description. 2. Features and benefits. 3. Ordering information

Low-power D-type flip-flop; positive-edge trigger; 3-state

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input NOR gate

The 74LVC1G04 provides one inverting buffer.

MM74HC14 Hex Inverting Schmitt Trigger

DATA SHEET. TDA1510AQ 24 W BTL or 2 x 12 W stereo car radio power amplifier INTEGRATED CIRCUITS

INTEGRATED CIRCUITS DATA SHEET. TDA W BTL mono audio amplifier. Product specification File under Integrated Circuits, IC01

74AUP1G General description. 2. Features and benefits. Low-power D-type flip-flop with set and reset; positive-edge trigger

14-stage ripple-carry binary counter/divider and oscillator

INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook

DATA SHEET. TDA8560Q 2 40 W/2 Ω stereo BTL car radio power amplifier with diagnostic facility INTEGRATED CIRCUITS Jan 08

74HC32; 74HCT General description. 2. Features and benefits. Quad 2-input OR gate

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

8-bit synchronous binary down counter

INTEGRATED CIRCUITS DATA SHEET. TDA7000 FM radio circuit. Product specification File under Integrated Circuits, IC01

CD4043BC CD4044BC Quad 3-STATE NOR R/S Latches Quad 3-STATE NAND R/S Latches

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer

NTB General description. 2. Features and benefits. Dual supply translating transceiver; auto direction sensing; 3-state

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

Buffer with open-drain output. The 74LVC1G07 provides the non-inverting buffer.

DATA SHEET. HEF4508B MSI Dual 4-bit latch. For a complete data sheet, please also download: INTEGRATED CIRCUITS

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

INTEGRATED CIRCUITS. NE558 Quad timer. Product data Supersedes data of 2001 Aug Feb 14

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate Quad 2-Input NAND Buffered B Series Gate

HCC/HCF4032B HCC/HCF4038B

MADR TR. Single Driver for GaAs FET or PIN Diode Switches and Attenuators Rev. V1. Functional Schematic. Features.

CD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop

HCF4081B QUAD 2 INPUT AND GATE

DISCRETE SEMICONDUCTORS DATA SHEET. BFQ34 NPN 4 GHz wideband transistor. Product specification File under Discrete Semiconductors, SC14

Kit 27. 1W TDA7052 POWER AMPLIFIER

74AC139 74ACT139 Dual 1-of-4 Decoder/Demultiplexer

High-speed switching diodes. Type number Package Configuration Package NXP JEITA JEDEC

.LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M74HC154 4 TO 16 LINE DECODER/DEMULTIPLEXER. HIGH SPEED tpd = 15 ns (TYP.) at VCC =5V

DATA SHEET. TDA1543 Dual 16-bit DAC (economy version) (I 2 S input format) INTEGRATED CIRCUITS

MM74HC4538 Dual Retriggerable Monostable Multivibrator

74LVC1G General description. 2. Features and benefits. Single D-type flip-flop with set and reset; positive edge trigger

HCF4070B QUAD EXCLUSIVE OR GATE

MADR TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators Rev. 4. Functional Schematic. Features.

40 V, 200 ma NPN switching transistor

HCF4010B HEX BUFFER/CONVERTER (NON INVERTING)

MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer

N-channel enhancement mode TrenchMOS transistor

BAS16 series. 1. Product profile. High-speed switching diodes. 1.1 General description. 1.2 Features and benefits. 1.

IP4234CZ6. 1. Product profile. Single USB 2.0 ESD protection to IEC level General description. 1.2 Features. 1.

CD4013BC Dual D-Type Flip-Flop

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

MADR TR. Quad Driver for GaAs FET or PIN Diode Switches and Attenuators. Functional Schematic. Features. Description. Pin Configuration 2

MM74C74 Dual D-Type Flip-Flop

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Transcription:

FEATURES Wide supply voltage range of to 3.6 In accordance with the JEDEC standard no. 8-1A. Inputs accept voltages upto 5.5 Direct interface with TTL levels CMOS low power consumption Output drive capability 50 Ω transmission lines @ 85 C DESCRIPTION The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The 245 features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. The 245 is identical to the 640 but has true (non-inverting) outputs. FUNCTION TABLE INPUTS INPUTS/OUTPUT OE DIR A n B n L L A = B inputs L H inputs B = A H X Z Z H = HIGH voltage level L = LOW voltage level X = don t care Z = high impedance OFF-state QUICK REFERENCE DATA = 0 ; T amb = 25 C; t r = t f 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT t PHL /t PLH propagation delay C L = 50 pf A n to B n ; B n to A n = 3.3 4.1 ns C I input capacitance 5.0 pf C I/O input/output capacitance 10 pf C PD power dissipation capacitance per buffer notes 1 and 2 40 pf Notes to the quick reference data 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D = C PD x 2 x f i + Σ (C L x 2 x f o ) where: f i = input frequency in MHz; C L = output load capacity in pf; f o = output frequency in MHz; = supply voltage in ; Σ (C L x 2 x f o ) = sum of outputs. 2. The condition is = to. ORDERING INFORMATION TYPE NUMBER PACKAGES PINS PACKAGE MATERIAL CODE D 20 SO plastic SO20/SOT163A DB 20 SSOP plastic SSOP20/SOT339 PW 20 TSSOP plastic SSOP20/SOT360 PINNING PIN SYMBOL NAME AND FUNCTION 1 DIR direction control 2, 3, 4, 5, 6, 7, 8, 9 A 0 to A 7 data inputs/outputs 10 ground (0 ) 18, 17, 16, 15, 14, 13, 12, 11 B 0 to B 7 data inputs/outputs 19 OE output enable input (active LOW) 20 positive supply voltage April 1994 1

DIR 1 A 0 2 A 1 3 A 2 4 A 3 5 A 4 6 A 5 7 A 6 8 A 7 9 245 20 19 OE 18 B 0 17 B 1 16 B 2 15 B 3 14 B 4 13 B 5 12 B 6 10 11 B 7 DIR 1 A 0 2 3 A 1 4 A 2 5 A 3 6 A 4 7 A 5 8 A 6 9 A 7 OE 19 B 0 18 B 1 17 B 2 16 B 3 15 B 4 14 B 5 13 B 6 12 B 7 11 Fig.1 Pin configuration. Fig.2 Logic symbol. 19 1 G3 3EN1 3EN2 2 1 2 18 3 17 4 16 5 15 6 14 7 13 8 12 9 11 Fig.3 IEC logic symbol. April 1994 2

FAMILY DESCRIPTION The LC family comprises very fast low-power logic ICs fabricated in a sub-micron CMOS process. LC ICs with 3.3 ±0.3 supply operate at the same speed as FAST bipolar logic and consumes only a fraction of the power. The LC family functions with supply voltages down to 2.7. The reduction from the conventional 5.0 to 3.3 reduces the output swing leading to a much lower dynamic power dissipation. Pin and function compatibility with FAST ensures an easy transfer of existing systems into new 3.3 systems. RECOMMENDED OPERATING CONDITIONS FOR THE LC FAMILY SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS DC supply voltage (for max. speed performance) DC supply voltage (for low-voltage applications) 2.7 3.6 3.6 DC input voltage range 0 5.5 /O DC input voltage range for I/Os 0 O DC output voltage range 0 T amb t r, t f operating ambient temperature range in free air input rise and fall times LIMITING ALUES FOR THE LC FAMILY (Note 1) In accordance with the Absolute Maximum Rating System (IEC 134) oltages are referenced to (ground = 0 ) 40 +85 C SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS DC supply voltage 0.5 +4.6 I IK DC input diode current 50 ma < 0 DC input voltage 0.5 +5.5 note 2 /O DC input voltage range for I/Os 0.5 + 0.5 0 0 20 10 ns/ K DC output diode current ±50 ma O > or O < 0 O DC output voltage 0.5 + 0.5 note 2 DC output source or sink current ±50 ma O = 0 to I, I CC DC or current ±100 ma T stg storage temperature range 60 +150 C P tot power dissipation per package - plastic mini-pack (SO) - plastic shrink mini-pack (SSOP and TSSOP) 500 500 mw mw see DC and AC characteristics per device = to 2.7 = 2.7 to 3.6 above + 70 C derate linearly with 8 mw/k above + 60 C derate linearly with 5.5 mw/k Notes to the limiting values 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. April 1994 3

DC CHARACTERISTICS FOR THE LC FAMILY Over recommended operating conditions oltages are referenced to (ground = 0 ) SYMBOL H L OH OL I l I IHZ /I ILZ Z I CC I CC PARAMETER HIGH level input voltage LOW level input voltage HIGH level output voltage LOW level output voltage input leakage current input current for common I/O pins 3-state output OFF-state current quiescent supply current additional quiescent supply current given per input pin T amb ( C) 40 to +85 MIN. TYP. MAX. 2.0 0.5 0.2 0.6 1.0 0.8 0.40 0.20 0.55 UNIT () 2.7 to 3.6 2.7 to 3.6 2.7 2.7 TEST CONDITIONS H or L H or L OTHER = 12 ma = 100 µa = 12 ma = 24 ma = 12 ma = 100 µa = 24 ma ±0.1 ±5 µa 3.6 5.5 or not for I/O pins ±0.1 ±15 µa 3.6 or 0.1 ±10 µa 3.6 H or L O = or 0.1 20 µa 3.6 or = 0 5 500 µa 2.7 to 3.6 0.6 O = 0 Note: All typical values are measured at = 3.3 and T amb = 25 C. April 1994 4

DC CHARACTERISTICS FOR For the DC characteristics see chapter "LC family characteristics", section "Family specifications". I CC category: MSI AC CHARACTERISTICS FOR = 0 ; t r = t f 2.5 ns; C L = 50 pf SYMBOL t PHL /t PLH t PZH /t PZL t PHZ /t PLZ PARAMETER propagation delay A n to B n ; B n to A n 3-state output enable time OE to A n ; OE to B n 3-state output disable time OE to A n ; OE to B n MIN. T amb ( C) -40 to +85 UNIT TYP. MAX. 21 4.6 4.1* 25 5.3 4.5* 8.0 4.3 4.0* 8.0 7.0 10.0 9.0 9.0 8.0 ns ns ns () TEST CONDITIONS 2.7 Figs 4, 6 to 3.6 2.7 Figs 5, 6 to 3.6 2.7 Figs 5, 6 to 3.6 WAEFORMS Notes: All typical values are measured at T amb = 25 C. * Typical values are measured at = 3.3. April 1994 5

AC WAEFORMS INPUTS M (1) OE INPUT M (1) t PHL (4) OH OUTPUTS (1) M (4) OL t PLH OUTPUT LOW-to-OFF OFF-to-LOW (4) OL t PLZ X (2) t PZL M (1) t PHZ t PZH (4) OH OUTPUT HIGH-to-OFF OFF-to-HIGH outputs enabled Y (3) outputs disabled M (1) outputs enabled Fig. 4 Waveforms showing the input (A n, B n ) to output (B n, A n ) propagation delays Fig.5 Waveforms showing the 3-state enable and disable times. PULSE GENERATOR < 2.7 2.7-3.6 2.7 R T D.U.T. O C L 50 pf 500 Ω Test t PLH /t PHL t PLZ /t PZL t PHZ /t PZH S 1 2 Open 500 Ω S 1 Open 2 Notes: (1) M = 0.5 at < 2.7 M = at 2.7 (2) X = OL + 0.3 at 2.7 X = OL + 0.1 at < 2.7 (3) Y = OH 0.3 at 2.7 Y = OH 0.1 at < 2.7 (4) OL and OH are the typical output voltage drop that occur with the output load. Fig.6 Load circuitry for switching times. April 1994 6

1 12.6 7.6 7.4 A S 0.9 0.4 (4x) 0.1 S 10.65 10.00 20 11 2.45 2.25 0.3 0.1 1.1 1.0 0.32 0.23 2.65 2.35 pin 1 index detail A 1.1 0.5 0 to 8 o MBC234 1 10 7 0.49 0.36 0.25 M (20x) Fig.7 20-lead mini-pack; plastic (SO20; SOT163A). 7.4 7.0 5.4 5.2 A S 0.1 S 7.9 7.6 0.9 20 11 1.80 1.65 0.20 0.05 0.9 0.7 0.22 0.13 2.0 1.7 pin 1 index 1 10 0.50 0 to 8 o detail A MSA322 0.65 0.38 0.25 0.13 M Fig.8 20-lead plastic medium-shrink SO (SSOP II 20; SOT339) April 1994 7

SOLDERING Plastic mini-packs BY WAE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING OR PULSE-HEATED SOLDER TOOL) Fix the component by first soldering two diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification Limiting values This data sheet contains final product specifications Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operating of the device at these or any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1994 8