HT1632C 32 8 &24 16 LED Driver

Similar documents
HT1632C 32 8 &24 16 LED Driver

HT6P20X Series 2 24 OTP Encoder

HT12A/HT12E 2 12 Series of Encoders

Information Board User s Guide

HT12D/HT12F 2 12 Series of Decoders

HT7660. CMOS Switched-Capacitor Voltage Converter. Features. Applications. General Description. Block Diagram

HT6221/HT6222 Multi-Purpose Encoders

HT6P OTP Encoder

Radiowe zdalne sterowanie

0832 Dot Matrix Green Display Information Board User s Guide

LMB162ABC LCD Module User Manual

LCM NHD-12032BZ-FSW-GBW. User s Guide. (Liquid Crystal Display Graphic Module) RoHS Compliant. For product support, contact

Using the HT1632 for Dot Matrix LED Displays

How To Power A Power Supply On A Microprocessor (Mii) Or Microprocessor Power Supply (Miio) (Power Supply) (Microprocessor) (Miniio) Or Power Supply Power Control (Power) (Mio) Power Control

7 OUT1 8 OUT2 9 OUT3 10 OUT4 11 OUT5 12 OUT6 13 OUT7 14 OUT8 15 OUT9 16 OUT10 17 OUT11 18 OUT12 19 OUT13 20 OUT14 21 OUT15 22 OUT16 OUT17 23 OUT18

DS1621 Digital Thermometer and Thermostat

PACKAGE OUTLINE DALLAS DS2434 DS2434 GND. PR 35 PACKAGE See Mech. Drawings Section

LC898300XA. Functions Automatic adjustment to the individual resonance frequency Automatic brake function Initial drive frequency adjustment function

FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM. PT2272 Remote Control Decoder

NJU6061. Full Color LED Controller Driver with PWM Control GENERAL DESCRIPTION PACKAGE OUTLINE FEATURES

INTEGRATED CIRCUITS. 74F74 Dual D-type flip-flop. Product specification Supercedes data of 1990 Oct 23 IC15 Data Handbook.

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DS1621 Digital Thermometer and Thermostat

FEATURES DESCRIPTION. PT6321 Fluorescent Display Tube Controller Driver

DS1307ZN. 64 x 8 Serial Real-Time Clock

Description. Table 1. Device summary. Order code Temperature range Package Packaging Marking

74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DESCRIPTION FEATURES BLOCK DIAGRAM. PT2260 Remote Control Encoder

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

HEF4021B. 1. General description. 2. Features and benefits. 3. Ordering information. 8-bit static shift register

HT9170 DTMF Receiver. Features. General Description. Selection Table

5495A DM Bit Parallel Access Shift Registers

Features. Instruction. Decoder Control Logic, And Clock Generators. Address Compare amd Write Enable. Protect Register V PP.

NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter

KS0108B 64CH SEGMENT DRIVER FOR DOT MATRIX LCD INTRODUCTION 100 QFP

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

14-stage ripple-carry binary counter/divider and oscillator

CD4027BM CD4027BC Dual J-K Master Slave Flip-Flop with Set and Reset

CD4013BC Dual D-Type Flip-Flop

CAT28C64B F R E E. 64K-Bit CMOS PARALLEL EEPROM L E A D FEATURES DESCRIPTION BLOCK DIAGRAM

HD61202U. (Dot Matrix Liquid Crystal GraphicDisplay Column Driver)

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

DS Wire Digital Thermometer and Thermostat

RAM Mapping 16*8 LED Controller Driver with keyscan HT16K33

CD4027BC Dual J-K Master/Slave Flip-Flop with Set and Reset

54191 DM54191 DM74191 Synchronous Up Down 4-Bit Binary Counter with Mode Control

CD4511BM CD4511BC BCD-to-7 Segment Latch Decoder Driver

MGL x64 Graphic LCD Module User Manual

DM54161 DM74161 DM74163 Synchronous 4-Bit Counters

54LS193 DM54LS193 DM74LS193 Synchronous 4-Bit Up Down Binary Counters with Dual Clock

HEF4011B. 1. General description. 2. Features and benefits. 3. Ordering information. 4. Functional diagram. Quad 2-input NAND gate

Features INSTRUCTION DECODER CONTROL LOGIC AND CLOCK GENERATORS COMPARATOR AND WRITE ENABLE EEPROM ARRAY READ/WRITE AMPS 16

8 by 8 dot matrix LED displays with Cascadable Serial driver B32CDM8 B48CDM8 B64CDM8 General Description

INTEGRATED CIRCUITS. 74LVC08A Quad 2-input AND gate. Product specification IC24 Data Handbook Jun 30

INTEGRATED CIRCUITS. 74F153 Dual 4-line to 1-line multiplexer. Product specification 1996 Jan 05 IC15 Data Handbook

VITESSE SEMICONDUCTOR CORPORATION. 16:1 Multiplexer. Timing Generator. CMU x16

DM Segment Decoder/Driver/Latch with Constant Current Source Outputs

HCC/HCF4032B HCC/HCF4038B

54LS169 DM54LS169A DM74LS169A Synchronous 4-Bit Up Down Binary Counter

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

1.5A ASYNCHRONOUS DC-DC BUCK CONV

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features

HEF4013B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Dual D-type flip-flop

HCF4056B BCD TO 7 SEGMENT DECODER /DRIVER WITH STROBED LATCH FUNCTION

Quad 2-input NAND Schmitt trigger

1-of-4 decoder/demultiplexer

FEATURES DESCRIPTION APPLICATIONS BLOCK DIAGRAM. PT2248 Infrared Remote Control Transmitter

HCC/HCF4027B DUAL-J-K MASTER-SLAVE FLIP-FLOP

MicroMag3 3-Axis Magnetic Sensor Module

Features. Modulation Frequency (khz) VDD. PLL Clock Synthesizer with Spread Spectrum Circuitry GND

IS31FL3731 AUDIO MODULATED MATRIX LED DRIVER. May 2013

LCD MODULE DEM SYH-LY

DS1220Y 16k Nonvolatile SRAM

DS1225Y 64k Nonvolatile SRAM

HD61203U. (Dot Matrix Liquid Crystal Graphic Display 64-Channel Common Driver)

DS1220Y 16k Nonvolatile SRAM

WHITE LED STEP-UP CONVERTER. Features

Push-Pull FET Driver with Integrated Oscillator and Clock Output

8741A UNIVERSAL PERIPHERAL INTERFACE 8-BIT MICROCOMPUTER

HCC4541B HCF4541B PROGRAMMABLE TIMER

8-Bit Flash Microcontroller for Smart Cards. AT89SCXXXXA Summary. Features. Description. Complete datasheet available under NDA

TS555. Low-power single CMOS timer. Description. Features. The TS555 is a single CMOS timer with very low consumption:

NT7606. STN LCDController/Driver. RAM-Map STN LCD Controller/Driver. Preliminary

256K (32K x 8) Static RAM

INTEGRATED CIRCUITS. NE558 Quad timer. Product data Supersedes data of 2001 Aug Feb 14

74F257A Quad 2-line to 1-line selector/multiplexer, non-inverting (3-State)

ICS379. Quad PLL with VCXO Quick Turn Clock. Description. Features. Block Diagram

BATRON. Specification for BTHQ 21605V-FSTF-I2C-COG

. MEDIUM SPEED OPERATION - 8MHz . MULTI-PACKAGE PARALLEL CLOCKING FOR HCC4029B HCF4029B PRESETTABLE UP/DOWN COUNTER BINARY OR BCD DECADE

8-bit binary counter with output register; 3-state

JTAG-HS2 Programming Cable for Xilinx FPGAs. Overview. Revised January 22, 2015 This manual applies to the HTAG-HS2 rev. A


ICS514 LOCO PLL CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

MC14008B. 4-Bit Full Adder

Spread-Spectrum Crystal Multiplier DS1080L. Features

1 TO 4 CLOCK BUFFER ICS551. Description. Features. Block Diagram DATASHEET

1-Mbit (128K x 8) Static RAM

HCMS-29xx Series High Performance CMOS 5 x 7 Alphanumeric Displays

WS2811. Signal line 256 Gray level 3 channal Constant current LED drive IC. Feature. Applications. General description

SPECIFICATION NO. : DS D A T E O F I S S U E : July 16, R E V I S I O N : September 1, 2010 (00) : : :

Transcription:

328 &216 LED Driver Features Operating voltage: 2.V~5.5V Multiple LED display 32 /8 COM and 2 & 16 COM Integrated display RAM select 32 & 8 COM for 6 display RAM, or select 2 & 16 COM for 96 display RAM 16-level PWM brightness control Integrated 256kHz RC oscillator Serial MCU interface CS, RD,WR, DATA Data mode & command mode instruction Cascading function for extended applications Selectable NMOS open drain output driver and PMOS open drain output driver for commons 52-pin QFP package Applications Industrial control indicator Digital clock, thermometer, counter, voltmeter Instrumentation readouts Other consumer application LED Displays General Description The HT1632C is a memory mapping LED display controller/driver, which can select a number of and commons. These are 32 & 8 commons and 2 & 16 commons. The device supports 16-gradation LEDs for each out line using PWM control with software instructions. A serial interface is conveniently provided for the command mode and data mode. Only three or four lines are required for the interface between the host controller and the HT1632C. The display can be extended by cascading the HT1632C for wider applications. Block Diagram 8,, 8 5 5, E I F = O ) -, 8,,, J H = @ 6 E E C + E H? K E J -,, H E L A H % 9 9! 9 " # 9! & -, 8 5 5 5 ; + 6 E E C / A A H = J H 2 9 J H Rev. 1.20 1 June 28, 2011

Pin Assignment 9 9 9 ' 9 & 9 % 9 $ -, 8,, 9 # 9 " 9! 9 9 9! " # $ % & '! 9 " # 9! 9 9 9 9 ' 9 & 9 % 9 $ 9 # 9 " 9! 9 # # # " '" & " %" $ " # 0 6 $! + # 3. 2 ) " ""!" " "! '! &! %! $! #! "!!!!! ' & % " # $ % & '! " # $ 9 # " -, 8,, 9 $! -, 8 5 5 9 % 9 & 9 ' 9! ' 9! & % $ # "! -, 8 5 8,, 5 ; +, 8 5 5 Pin Description Pad Name I/O Description 0~23 O Line drivers. These pins drive the LEDs. 2/COM15~ 31/COM8 O Drive LED outputs or common outputs. Each COM pin is double bonded. COM0~COM7 O Common outputs. Each COM pin is double bonded. SYNC OSC I/O I/O If the RC Master Mode or EXT CLK Master Mode command is programmed, the synchronous signal is output to SYN pin. If the Slave Mode command is programmed, the synchronous signal is input from SYN pin. If the RC Master Mode command is programmed, the system clock source is from on-chip RC oscillator and system clock is output to OSC pin. If the Slave Mode or EXT CLK Master Mode command is programmed, the system clock source is input from external clock via the OSC pin. DATA I/O Serial data input or output with pull-high resistor WR RD CS I I I WRITE clock input with pull-high resistor Data on the DATA lines are latched into the HT1632C on the rising edge of the WR signal. READ clock input with pull-high resistor. The HT1632C RAM data is clocked out on the falling edge of the RD signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data. Chip select input with pull-high resistor When the CS line is high, the data and command read from or written to the HT1632C is disabled, and the serial interface circuit is also reset. If CS is low, the data and command transmission between the host controller and the HT1632C are all enabled. LED_VDD Positive power supply for driver circuit. Each LED_VDD pin is double bonded. LED_VSS Negative power supply for driver circuit, ground. Each LED_VSS pin is double bonded. VSS Negative power supply for logic circuit, ground. VDD Positive power supply for logic circuit. Rev. 1.20 2 June 28, 2011

Absolute Maximum Ratings Supply Voltage...V SS 0.3V to V SS +6.0V Input Voltage...V SS 0.3V to V DD +0.3V Storage Temperature...50C to125c Operating Temperature...0C to85c Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics V DD =2.V~5.5V, Ta=25C (Unless otherwise specified) Symbol Parameter V DD Test Conditions Conditions Min. Typ. Max. Unit V DD Operating Voltage 2. 5.0 5.5 V I DD Operating Current 5V No load, LED, on-chip RC oscillator 0.3 0.6 ma I STB Standby Current 5V No load, power down mode 1.5 3.0 A V IL Input Low Voltage 5V DATA, WR, CS,RD 0 0.3V DD V V IH Input High Voltage 5V DATA, WR, CS,RD 0.7V DD 5 V I OL1 OSC, SYNC, DATA 5V V OL =0.5V 18 25 ma I OH1 OSC, SYNC, DATA 5V V OH =.5V -10-13 ma I OL2 Sink Current 5V V OL =0.5V 12 16 ma I OH2 Source Current 5V V OH =.5V -50-70 ma I OL3 COM Sink Current 5V V OL =0.5V 250 350 ma I OH3 COM Source Current 5V V OH =.5V -5-60 ma R PH Pull-high Resistor 5V DATA, WR, CS,RD 18 27 0 k Rev. 1.20 3 June 28, 2011

A.C. Characteristics V DD =2.V~5.5V, Ta=25C (Unless otherwise specified) Symbol Parameter V DD Test Conditions Conditions Min. Typ. Max. Unit f SYS System Clock 5V On-chip RC oscillator 230 256 282 khz f LED LED Duty Cycle & Frame Frequency 5V 1/8 duty f SYS /262 Hz 5V 1/16 duty f SYS /262 Hz f CLK1 Serial Data Clock (WR pin) 5V Duty cycle 50% 1 MHz f CLK2 Serial Data Clock (RD pin) 5V Duty cycle 50% 500 khz t CS Serial Interface Reset Pulse Width CS 250 ns t CLK WR, RDInput Pulse Width 5V t r,t f t su t h t su1 t h1 t od Rise/Fall Time Serial Data Clock Width (Figure 1) Setup Time for DATA to WR, RD Clock Width (Figure 2) Hold Time for DATA to WR,RD, Clock Width (Figure 2) Setup Time for CS to WR, RD, Clock Width (Figure 3) Hold Time for CS to WR, RD, Clock Width (Figure 3) Data Output Delay Time (Figure ) Write mode 0.5 Read mode 1.0 50 100 ns 50 100 ns 100 200 ns 200 300 ns 100 200 ns 100 200 ns s,? JB JH 8,, ' # /, J J 8 = E @, = J = # JI K JD 8,, /, Figure 1? # 8,, /, Figure 2,? J # JI K JD #. E H I J? = I J? 8,, /, 8,, /,, J @ # Figure 8,, /, 8,, /, Figure 3 Rev. 1.20 June 28, 2011

Functional Description Display Memory RAM The static display memory (RAM) is organized into 6 bits or 96 bits and is used to store the display data. If 32 & 8 COM is selected, the RAM size is 6 bits. If 2 & 16 COM is selected, the RAM size is 96 bits. The contents of the RAM are directly mapped to the contents of the LED driver. If the data in RAM is set to 1, the corresponding LED will be lighted. Data in the RAM can be accessed by the READ, WRITE, and READ-MODIFY-WRITE commands. The contents of the RAM can be read or written from bit 0 of the specific address. The following is a mapping from the RAM to the LED pattern: COM7 COM6 COM5 COM COM3 COM2 COM1 COM0 0 01H 00H 1 03H 02H 2 05H 0H 3 07H 06H 09H 08H 5 0BH 0AH 6 0DH 0CH 7 0FH 0EH 8 11H 10H 9 13H 12H 10 15H 1H 11 17H 16H 12 19H 18H 13 1BH 1AH 1 1DH 1CH 15 1FH 1EH 16 21H 20H 17 23H 22H 18 25H 2H 19 27H 26H 20 29H 28H 21 2BH 2AH 22 2DH 2CH 23 2FH 2EH 2 31H 30H 25 33H 32H 26 35H 3H 27 37H 36H 28 39H 38H 29 3BH 3AH 30 3DH 3CH 31 3FH 3EH D3 D2 D1 D0 Addr. Data D3 D2 D1 D0 Addr. Data 32 & 8 COM for 6 Display RAM Rev. 1.20 5 June 28, 2011

COM15 COM1 COM13 COM12... COM3 COM2 COM1 COM0 0 03H 00H 1 07H 0H 2 0BH 08H 3 0FH 0CH 13H 10H 5 17H 1H 6 1BH 18H 7 1FH 1CH 8 23H 20H 9 27H 2H 10 2BH 28H 11 2FH... 2CH 12 33H 30H 13 37H 3H 1 3BH 38H 15 3FH 3CH 16 3H 0H 17 7H H 18 BH 8H 1FH CH 20 53H 50H 21 57H 5H 22 5BH 58H 23 5FH... 5CH D3 D2 D1 D0 Data Addr. D3 D2 D1 D0 Data Addr. 2 & 16 COM for 96 Display RAM Rev. 1.20 6 June 28, 2011

System Oscillator The HT1632C system clock is used to generate the time base clock frequency, LED-driving clock. The clock may be sourced from an on-chip RC oscillator (256kHz), or an external clock using the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command is executed, the system clock will stop and the LED duty cycle generator will turn off. This command is, however, available only for the on-chip RC oscillator. Once the system clock stops, the LED display will become blank, and the time base will also lose its function. The LED command is used to turn the LED duty cycle generator off. After the LED duty cycle generator switches off by issuing the LED command, using the SYS DIS command reduces power consumption, serving as a system power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command can neither turn the oscillator off nor execute the power down mode. The crystal oscillator option can be applied to connect an external frequency source to the OSC pin. In this case, the system fails to enter the power down mode, similar to the case in the external clock source operation. At the initial system power on, the HT1632C is in the SYS DIS state. - N J A H =? 5 K H? A? D E F + I? E = J H # $ 0 System Oscillator Configuration 5 O I J A? LED Driver The HT1632C has a 256 (328) and 38 (216) pattern LED driver. It can be configured in a 328 or216 pattern and common pad N-MOS open drain output or P-MOS open drain output LED driver using the S/W configuration. This feature makes the HT1632C suitable for multiple LED applications. The LED-driving clock is derived from the system clock. The driving clock frequency is always 256kHz, an on-chip RC oscillator frequency, or an external frequency. The LED corresponding commands are summarized in the table. The bold form of 1 0 0, namely100,indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The LED command turns the LED display off by disabling the LED duty cycle generator. The LED command, on the other hand, turns the LED display on by enabling the LED duty cycle generator. Name Command Code Function LED 10000000010X Turn off LED outputs LED 10000000011X Turn on LED outputs Commons Option 1000010abXXX ab=00: N-MOS open drain output and 8 common option ab=01: N-MOS open drain output and 16 common option ab=10: P-MOS open drain output and 8 common option ab=11: P-MOS open drain output and 16 common option Cascade Operation For the cascade operation, the first IC is set to master mode and its SYNC and OSC pins are set to output pins. The second IC is set to slave mode and its SYNC and OSC pins are set to input pins which are connected to the the master IC. Please refer to the Cascade control flow chart for detail settings. Blinker The HT1632C has display blinking capabilities. The blink function generates all LED blinking. The blink rates is 0.25s LED on and 0.25s LED off for one blinking period. This blinking function can be effectively performed by setting the BLINK or BLINK command. Command Format The S/W setting can configure the HT1632C. There are two mode commands to configure the HT1632C resources and to transfer the LED display data. The configuration mode of the HT1632C is knows as the command mode,with a command mode ID of 100.Thecommand mode consists of a system configuration command, a system frequency selection command, a LED configuration command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and READ-MODIFY-WRITE operations. -, 6 K H 6 K H B B # I # I * E * E B B Example of Waveform for Blinker Rev. 1.20 7 June 28, 2011

LED Driver Mode output Waveform N-MOS open drain of 32x8 driver mode 0 ~31 COM0 COM1 320*tCLK 32 *tclk * tclk 8*tCLK ~ COM2 ~ COM5 COM6 COM7 1/2*tCLK SYNC 1Frame=8*328*tCLK Note: t CLK =1/f SYS P-MOS open drain of 2x16 driver mode: (COM pin with Transistor Buffer) 0 ~23 COM0 COM1 160*tCLK 16 2*tCLK 2* tclk *tclk ~ COM2 ~ 26/COM13 25/COM1 2/COM15 1/2*tCLK SYNC 1 Frame = 16*16* tclk Note: t CLK =1/f SYS Rev. 1.20 8 June 28, 2011

Digital Dimming The Display Dimming capabilities of the HT1632 are very versatile. The whole display can be dimmed using pulse width modulation techniques for the driver with the Dimming command. The relationship between and COM digital dimming duty time are shown as below: Note: COM 1/16 Duty 2/16 Duty 3/16 Duty /16 Duty 5/16 Duty 6/16 Duty 7/16 Duty 8/16 Duty 9/16 Duty 10/16 Duty 11/16 Duty 12/16 Duty 13/16 Duty 1/16 Duty 15/16 Duty 16/16 Duty 1*T 2*T 3*T *T 5*T 6*T 7*T 8*T 9*T 10*T (1) T=20 x t CLK (32x8 driver mode) (2) T=10 x t CLK (2x16 driver mode) 11*T 12*T 13*T 1*T 15*T 16*T (3) t CLK =1/f SYS Rev. 1.20 9 June 28, 2011

The following are the data mode ID and the command mode ID: Operation Mode ID Read Data 1 1 0 Write Data 1 0 1 Read-Modify-Write Data 1 0 1 Command Command 1 0 0 The mode command should be issued before the data or command is transferred. If successive commands have been issued, the command mode ID, namely 1 0 0, can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. Once the CS pin returns to 0, a new operation mode ID should be issued first. Interfacing Only four lines are required to interface to the HT1632C. The CS line is used to initialise the serial interface circuit and to terminate the communication between the host controller and the HT1632C. If the CS pin is set to 1, the data and command issued between the host controller and the HT1632C are first disabled and then initialised. Before issuing a mode command or mode switching, a high level pulse is required to initialise the serial interface of the HT1632C. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be passed through the DATA line. The RD line is the READ clock input. Data in the RAM is clocked out on the falling edge of the RD signal, and the clocked out data will then appear on the DATA line. It is recommended that the host controller reads in the correct data during the interval between the rising edge and the next falling edge of the RD signal. The WR line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the HT1632 on the rising edge of the WR signal. Timing Diagrams READ Mode Command Code =110, ) $ ) # ) " )! ) ) ),,,,! ) $ ) # ) " )! ) ), ),,,! A H O ) @ @ H A I I, = J = ) ) A H O ) @ @ H A I I, = J = ) ) READ Mode Successive Address Reading, ) $ ) # ) " )! ) ), ),,,!,,,!,,,!,,,! A H O ) @ @ H A I I, = J ) = ), = J = ), = J = ), = J = Rev. 1.20 10 June 28, 2011

WRITE Mode Command Code =101 ) $ ) # ) " )! ) ) ),,,,! ) $ ) # ) " )! ) ) ),,, A H O ) @ @ H A I I ), = J = ) A H O ) @ @ H A I I, = J = ) ) WRITE Mode Successive Address Writing ) $ ) # ) " )! ) ) ),,,,,,!,,!,,,!,,,! A H O ) @ @ H A I I ), =, J = = J = ) ), = J = ), = J = READ-MODIFY-WRITE Mode Command Code =101, ) $ ) # ) " )! ) ) ),,,,,,!,,! ) $ ) # ) " )! ) ),,,, A H O ) @ @ H A I I ),, = J = = J = ) ) A H O ) @ @ H A I I ), READ-MODIFY-WRITE Mode Successive Address Accessing, ) $ ) # ) " )! ) ) ),,,,,,!,,!,,,!,,,!,,,,! A H O ) @ @ H A I I ), =, J = = J = ) ), = J = ), =, J = J = ) ) Rev. 1.20 11 June 28, 2011

Command Mode Command Code =100 + & + % + $ + # + " +! + + + & + % + $ + # + " +! + + + = @ = @ = @ E = @ H, = J = @ A Mode Data and Command Mode = @ = @ = @ H ) @ @ H A I I = @, = J = H ) @ @ H A I I = @, = J = H ) @ @ H A I I = @, = J = @ A, = J = @ A, = J = @ A Rev. 1.20 12 June 28, 2011

Application Circuits Low Power LED Application (Direct Drive) 32 8 COM example,, + 7 9 9 9! 0 6 $! + ' 9! 9! % -, = J H E N Note: Values of the R resistors are selected depending on the power consumption of the LEDs. 2 16 COM example, + 7, 9 9! 0 6 $! + 9 9! # -, = J H E N Note: Values of the R resistors are selected depending on the power consumption of the LEDs. Rev. 1.20 13 June 28, 2011

Middle Power LED Application (COM with Transistor Buffer) 32 8 COM example,, 9 9 + 7 9 9 9! 9 ' 0 6 $! + 9! 9! % $ -, = J H E N % Note: Values of the R resistors are selected depending on the power consumption of the LEDs. 2 16 COM example,, 9 9 + 7 9 9 9! 9 0 6 $! + 9 9! # " -, = J H E N # Note: Values of the R resistors are selected depending on the power consumption of the LEDs. Rev. 1.20 1 June 28, 2011

High Power LED Application ( & COM with Transistor Buffer) 32 8 COM example 8,,,, + 7! % " # 0 6 $! + $ % 9 9 9! 9! -, = J H E N 9! Note: Values of the R resistors are selected depending on the power consumption of the LEDs. 2 16 COM example 8,,,, + 7 #! 0 6 $! + " # 9 9 9 9! 9 -, = J H E N 9! Note: Values of the R resistors are selected depending on the power consumption of the LEDs. Rev. 1.20 15 June 28, 2011

Cascade Function 32 8 COM example (direct drive)!, + 7 9 9!, 0 6 $! + = I J A H 5 ; + %! 9 & 9 9! % -, = J H E N 9 9!, 0 6 $! + 5 = L A 5 ; + %! 9 & 9 9! % -, = J H E N 9 9!, 0 6 $! + 5 = L A 5 ; + %! 9 & 9 9! % -, = J H E N Note: 1. It also can set cascade mode by software. User must set the Master in master mode and Slaves in slave mode with command. The CS pin must be connected to MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. Rev. 1.20 16 June 28, 2011

32 8 COM example (COM with transistor buffer)!, + 7 %, 0 6 $! + = I J A H 9 5 ; + 9! &! 9 % 9 9! -, = J H E N, 0 6 $! + 5 = L A -, = J H E N 9 9! 5 ; +! 9 9 9!, 0 6 $! + 5 = L A 5 ; + 9 9!! 9 9 9! -, = J H E N Note: 1. It also can set cascade mode by software. User must set the Master in master mode and Slaves in slave mode with command. The CS pin must be connected to MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. Rev. 1.20 17 June 28, 2011

2 16 COM example (direct drive)!, + 7 9 9!, 0 6 $! + = I J A H 5 ; + " 9 $ # 9 9! # -, = J H E N 9 9!, 0 6 $! + 5 = L A 5 ; + " 9 $ # 9 9! # -, = J H E N 9 9!, 0 6 $! + 5 = L A 5 ; + " 9 $ # 9 9! # -, = J H E N Note: 1. It also can set cascade mode by software. User must set the Master in master mode and Slaves in slave mode with command. The CS pin must be connected to MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. Rev. 1.20 18 June 28, 2011

2 16 COM example (COM with transistor buffer)!, + 7 #, 0 6 $! + = I J A H 9 5 ; + 9! $ " 9 # 9 9! -, = J H E N, 0 6 $! + 5 = L A -, = J H E N 9 9! 5 ; + " 9 9 9!, 0 6 $! + 5 = L A 5 ; + 9 9! " 9 9 9! -, = J H E N Note: 1. It also can set cascade mode by software. User must set the Master in master mode and Slaves in slave mode with command. The CS pin must be connected to MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. Rev. 1.20 19 June 28, 2011

Cascade Control Flow 2 M A H 5 ; 5, 1 5 = I J A H 5 = L A F J E = I J A H 5 = L A = I J A H @ A = I J A H 5 = L A @ A 5 = L A 5 ; 5 = JIA H 5 = L A -, = I J A H 5 = L A 9 H E J A ), = J = = I J A H 5 = L A 7 F @ = J A ), = J = = I J A H 5 = L A Rev. 1.20 20 June 28, 2011

Command Summary Name ID Command Code D/C Function Default READ 110 A6A5AA3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 101 A6A5AA3A2A1A0D0D1D2D3 D Write data to the RAM READ-MODIFY- WRITE 101 A6A5AA3A2A1A0D0D1D2D3 D Read and Write data to the RAM SYS DIS 100 0000-0000-X C Turn off both system oscillator and LED duty cycle generator Yes SYS EN 100 0000-0001-X C Turn on system oscillator LED Off 100 0000-0010-X C Turn off LED duty cycle generator Yes LED On 100 0000-0011-X C Turn on LED duty cycle generator BLINK Off 100 0000-1000-X C Turn off blinking function Yes BLINK On 100 0000-1001-X C Turn on blinking function SLAVE Mode 100 0001-0XXX-X C Set slave mode and clock source from external clock, the system clock input from OSC pin and synchronous signal input from SYN pin RC Master Mode 100 0001-10XX-X C Set master mode and clock source from on-chip RC oscillator, the system clock output to OSC pin and synchronous signal output to SYN pin Yes EXT CLK Master Mode 100 0001-11XX-X C Set master mode and clock source from external clock, the system clock input from OSC pin and synchronous signal output to SYN pin COM Option 100 0010-abXX-X C ab=00: N-MOS open drain output and 8 COM option ab=01: N-MOS open drain output and 16 COM option ab=10: P-MOS open drain output and 8 COM option ab=11: P-MOS open drain output and 16 COM option ab =00 100 101X-0000-X C PWM 1/16 duty 100 101X-0001-X C PWM 2/16 duty 100 101X-0010-X C PWM 3/16 duty 100 101X-0011-X C PWM /16 duty 100 101X-0100-X C PWM 5/16 duty 100 101X-0101-X C PWM 6/16 duty 100 101X-0110-X C PWM 7/16 duty PWM Duty 100 101X-0111-X C PWM 8/16 duty 100 101X-1000-X C PWM 9/16 duty 100 101X-1001-X C PWM 10/16 duty 100 101X-1010-X C PWM 11/16 duty 100 101X-1011-X C PWM 12/16 duty 100 101X-1100-X C PWM 13/16 duty 100 101X-1101-X C PWM 1/16 duty 100 101X-1110-X C PWM 15/16 duty 100 101X-1111-X C PWM 16/16 duty Yes Rev. 1.20 21 June 28, 2011

Note: HT1632C X: Dont care A6~A0: RAM addresses D3~D0: RAM data D/C: Data/command mode Default: Power on reset default All the bold forms, namely110,101,and100,aremode commands. Among these,100indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base clock frequency can be derived from an on-chip RC oscillator or an external clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1632C after power on reset, for power on reset may fail, which in turn leads to the malfunction of the HT1632C Rev. 1.20 22 June 28, 2011

Package Information 52-pin QFP (1mm1mm) Outline Dimensions +! ', % / 0 1 " $. ) * - # "! Symbol Dimensions in inch Min. Nom. Max. A 0.681 0.689 B 0.57 0.555 C 0.681 0.689 D 0.57 0.555 E 0.039 F 0.016 G 0.098 0.122 H 0.13 I 0.00 J 0.029 0.01 K 0.00 0.008 0 7 Symbol Dimensions in mm Min. Nom. Max. A 17.30 17.50 B 13.90 1.10 C 17.30 17.50 D 13.90 1.10 E 1.00 F 0.0 G 2.50 3.10 H 3.0 I 0.10 J 0.73 1.03 K 0.10 0.20 0 7 Rev. 1.20 23 June 28, 2011

Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 6729 Fremont Blvd., Fremont, CA 9538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright 2011 by HOLTEK SEMICDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 2 June 28, 2011