Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Input Clamping Diodes Simplify System Design Open-Collector Drivers for Indicator Lamps and Relays Inputs Fully Compatible With Most TTL Circuits description These TTL hex inverter buffers/drivers feature high-voltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are characterized for use as inverter buffers for driving TTL inputs. The SN0 and SN70 have minimum breakdown voltages of 0 V. The SN and SN7 have minimum breakdown voltages of V. The maximum sink current is 0 ma for the SN0 and SN, and 0 ma for the SN70 and SN7. SN0, SN, SN70, SN7 SDLS0 DECEMBER 9 REVISED DECEMBER 200 SN0, SN...J OR W PACKAGE SN70... D, N, OR NS PACKAGE SN7...D OR N PACKAGE (TOP VIEW) A Y A Y 2 7 2 0 9 V CC A A SN0... FK PACKAGE (TOP VIEW) Y 2 20 9 7 7 9 0 2 Y V CC A A No internal connection ORDERING INFORMATION TA PACKAGE ORDERABLE PART NUMBER SN70D SOIC D Tape and reel SN70DR SN7D 0 C to 70 C Tape and reel SN7DR C to 2 C PDIP N SN70N SN7N TOP-SIDE MARKING 70 7 SN70N SN7N SOP NS Tape and reel SN70NSR SN70 CDIP J CDIP W SNJ0J SNJ0J SNJJ SNJJ SNJ0W SNJ0W SNJW SNJW LCCC FK SNJ0FK SNJ0FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 200, Texas Instruments Incorporated On products compliant to MIL-PRF-, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 0 DALLAS, TEXAS 72
SDLS0 DECEMBER 9 REVISED DECEMBER 200 logic diagram (positive logic) 2 Y A Y A 9 0 A 2 Y = A schematic (each buffer/driver) 0, VCC kω. kω Input A 2 kω. kω Output Y 00 Ω kω Resistor values shown are nominal. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, V CC (see Note )............................................................. 7 V Input voltage, V I (see Note )................................................................ V Output voltage, V O (see Notes and 2): SN0, SN70...................................... 0 V SN, SN7...................................... V Package thermal impedance, θ JA (see Note ): D package................................... C/W N package................................... 0 C/W NS package................................. 7 C/W Storage temperature range, T stg................................................... C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. Voltage values are with respect to network ground terminal. 2. This is the maximum voltage which should be applied to any output when it is in the off state.. The package thermal impedance is calculated in accordance with JESD -7. 2 POST OFFICE BOX 0 DALLAS, TEXAS 72
SDLS0 DECEMBER 9 REVISED DECEMBER 200 recommended operating conditions SN0 SN SN70 SN7 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage...7.2 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0. 0. V High-level output voltage 0 0 0 IOL Low-level output current 0 0 ma TA Operating free-air temperature 2 0 70 C V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS SN0 SN SN70 SN7 MIN TYP MAX MIN TYP MAX VIK VCC = MIN, II = 2 ma.. V IOH VCC = MIN, VIL = 0. V, = 0.2 0.2 ma VOL VCC = MIN, VIH =2V IOL = ma 0. 0. IOL = 0.7 0.7 II VCC = MAX, VI =. V ma IIH VCC = MAX, VIH = 2. V 0 0 µa IIL VCC = MAX, VIL = 0. V.. ma ICCH VCC = MAX 0 0 ma ICCL VCC = MAX 2 2 ma For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. All typical values are at VCC = V, TA = 2 C. = 0 V for 0 and V for. IOL = 0 ma for SN and 0 ma for SN7. UNIT V switching characteristics, V CC = V, T A = 2 C (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) A Y RL = 0 Ω, CL = pf TEST CONDITIONS MIN TYP MAX UNIT 0 2 ns POST OFFICE BOX 0 DALLAS, TEXAS 72
SDLS0 DECEMBER 9 REVISED DECEMBER 200 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test RL CL (see Note A) Test Point LOAD CIRCUIT Input V 0 V High-Level Pulse In-Phase Output VOL tw Low-Level Pulse Out-of-Phase Output VOL VOLTAGE WAVEFORMS PULSE WIDTHS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, tr 7 ns, tf 7 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 0 DALLAS, TEXAS 72
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