SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS
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1 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS Choice of Open-Collector or Active Pullup (Totem-Pole) Outputs Single 5-V Supply Differential Line Operation Dual-Channel Operation TTL Compatible ± 15-V Common-Mode Input Voltage Range Optional-Use Built-In 13-Ω Line- Terminating Resistor Individual Frequency-Response Controls Individual Channel Strobes Designed for Use With SN55113, SN75113, SN5511, and SN7511 Drivers Designed to Be Interchangeable With National DS9615 Line Receivers SLLS72D SEPTEMBER 1973 REVISED MAY 1998 SN J OR W PACKAGE SN N PACKAGE (TOP VIEW) 1YS 1YP 1STRB 1RTC 1B 1R T 1A GND V CC 2YS 2YP 2STRB 2RTC 2B 2R T 2A SN FK PACKAGE (TOP VIEW) 1YP 1YS NC VCC 2YS description The SN55115 and SN75115 dual differential line receivers are designed to sense small differential signals in the presence of large common-mode noise. These devices give TTL-compatible output signals as a function of the differential input voltage. The open-collector output configuration permits the wire-anding of similar TTL outputs (such as SN51/SN71) or other SN55115/SN75115 line receivers. This permits a level of logic to be implemented without extra delay. The output stages are similar to TTL totem-pole outputs, but with sink outputs, 1YS and 2YS, and the corresponding active pullup terminals, 1YP and 2YP, available on adjacent package pins. The frequency response and noise immunity may be provided by a single external capacitor. A strobe input is provided for each channel. With the strobe in the low level, the receiver is disabled and the outputs are forced to a high level. The SN55115 is characterized for operation over the full military temperature range of 55 C to 125 C. The SN75115 is characterized for operation from C to 7 C. STRB FUNCTION TABLE DIFF INPUT (A AND B) 1STRB 1RTC NC 1B 1R T OUTPUT (YP AND YS TIED TOGETHER) L X H H L H H H L H = VI VIH min or VID more positive than VT+ max L = VI VIL max or VID more negative thanvt max X = irrelevant A GND NC 2A 2RT NC No internal connection 2YP 2STRB NC 2RTC 2B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1998, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS
2 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 logic symbol 1B 1A 1RT 1STRB 1RTC 2B 2A 2RT 2STRB 2RTC RT RSP & YP 1YS 2YP 2YS This symbol is in accordance with ANSI/IEEE Std and IEC Publication logic diagram (positive logic) 1B 1A 1RT 1RTC 1STRB YP (Pullup) 1 1YS (Sink) 11 2B 9 2A 1 2RT 12 2RTC 13 2STRB YP (Pullup) 2YS (Sink) 2 POST OFFICE BOX DALLAS, TEXAS 75265
3 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 schematic (each receiver) 1 k 1 k R T 6,1 Strobe 3,13 Response Time Control,12 V 2.7 k V 2 k V 16 VCC 1 pf 1.5 k 1.6 k 1.6 k 13 1 pf 2.6 k 2.6 k Input 7.9 A 8 k 7 k 8 k 7 k k 2 2,1 Pullup YP Input 5.11 B 3 k ,15 Sink Output YS k 8 GND Common to Both Receivers 2.5 k V 15 Resistor values are nominal and in ohms. Pin numbers shown are for the J, N, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, V CC (see Note 1) V Input voltage V I (A, B, and R T ) ±25 V Input voltage V I (STRB) V Off-state voltage applied to open-collector outputs V Continuous total power dissipation See Dissipation Rating Table Storage temperature range, T stg C to 15 C Case temperature for 6 seconds: FK package C Lead temperature 1,6 mm (1/16 inch) from case for 6 seconds: J or W package C Lead temperature 1,6 mm (1/16 inch) from case for 1 seconds: N package C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential input voltage, are with respect to network ground terminal. POST OFFICE BOX DALLAS, TEXAS
4 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 PACKAGE TA 25 C POWER RATING DISSIPATION RATING TABLE DERATING FACTOR ABOVE TA = 25 C TA = 7 C POWER RATING TA = 125 C POWER RATING FK 1375 mw 11. mw/ C 88 mw 275 mw J 1375 mw 11. mw/ C 88 mw 275 mw N 115 mw 9.2 mw/ C 736 mw W 1 mw 8. mw/ C 6 mw 2 mw In the FK, J, and W packages, SN55115 chips are either silver glass or alloy mounted. SN75115 chips are glass mounted. recommended operating conditions SN55115 SN75115 MIN NOM MAX MIN NOM MAX UNIT Supply voltage, VCC V High-level input voltage at STRB, VIH V Low-level input voltage at STRB, VIL.. V High-level output current, IOH 5 5 ma Low-level output current, IOL ma Operating free-air temperature, TA C POST OFFICE BOX DALLAS, TEXAS 75265
5 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VIT + VIT VICR VOH VOL IIL ISH ISL I(RTC) IO(off) RT IOS PARAMETER Positive-going threshold voltage Negative-going threshold voltage Common-mode input voltage range TEST CONDITIONS SN55115 SN75115 MIN TYP MAX MIN TYP MAX VO =. V, IOL = 15 ma, VIC = 5 5 mv VO = 2. V, IOH = 5 ma, VIC = 5 5 mv VID = ±1 V High-level l ouput VCC = MIN, VID =.5 V, voltage IOH = 5mA Low-level output voltage VCC = MIN, IOL = 15 ma VID =.5 V, Low-level l input VCC = MAX, VI =. V, current Other input at V +15 to to to 15 TA = MIN to 19 UNIT TA = 25 C V TA = MAX V TA = MIN.9.9 TA = 25 C ma TA = MAX.7.7 High-level strobe VCC = MIN, VID =.5 V, TA = 25 C 2 5 current Vstrobe =.5 V TA = MAX 5 1 Low-level strobe current Response-timecontrol current VCC = MAX, Vstrobe =. V VCC = MAX, VRC = VID =.5 V, VID =.5 V, V µa TA = 25 C ma TA = 25 C ma VCC = MIN, VOH = 12 V, TA = 25 C 1 Off-state VID =.5 V TA = MAX 2 open-collector output current VCC = MIN, VOH = 5.25 V, TA = 25 C 1 VID =.75 V TA = MAX 2 Line-terminating resistance Supply-circuit output current# VCC = 5 V TA = 25 C Ω VCC = MAX, VO = VCC = MAX, VIC = VID =.5 V, µa TA = 25 C ma Supply current VID =.5 V, ICC (both receivers) TA = 25 C ma Unless otherwise noted, Vstrobe = 2. V. All parameters with the exception of off-state open-collector output current are measured with the active pullup connected to the sink output. All typical values are at VCC = 5 V, TA = 25 C, and VIC =. Differential voltages are at the B input terminal with respect to the A input terminal. The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltages only. # Only one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second. POST OFFICE BOX DALLAS, TEXAS
6 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 switching characteristics, V CC = 5 V, C L = 3 pf, T A = 25 C tplh tphl PARAMETER Propagation delay time, low-to-high level output Propagation delay time, high-to-low level output TEST CONDITIONS SN55115 SN75115 MIN TYP MAX MIN TYP MAX UNIT RL = 3.9 kω, See Figure ns RL = 39 Ω, See Figure ns PARAMETER MEASUREMENT INFORMATION Open 2. V 5 V Input Pulse Generator (see Note A) B A RT STRB YP YS Response Time Control Open RL VO CL = 3 pf (see Note B) 5 ns Differential Input 1% Output 5 ns 9% 9% V V 1% tphl tplh 1.5 V 1.5 V 3 V 3 V VOH VOL TEST CIRCUIT VOLTAGE WAVEFORM NOTES: A. The pulse generator has the following characteristics: ZO = 5 Ω, PRR 5 khz, tw 1 ns, duty cycle = 5%. B. CL includes probe and jig capacitance. Figure 1. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX DALLAS, TEXAS 75265
7 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS TYPICAL CHARACTERISTICS SLLS72D SEPTEMBER 1973 REVISED MAY INPUT CURRENT INPUT VOLTAGE VCC = 5 V Input Not Under Test at V TA = 25 C II Input Current ma VI Input Voltage V Figure ICC Output Voltage V Î VCC =.5 V OUTPUT VOLTAGE FREE-AIR TEMPERATURE VOH (VID =.5 V, IOH = 5 ma) Î Î VOL (VID =.5 V, IOL = 15 ma) Î TA Free-Air Temperature C Figure 3 VO V O Output Voltage V OUTPUT VOLTAGE COMMON-MODE INPUT VOLTAGE No Load TA = 25 C 5 Î VCC = 5.5 V VCC = 5 V Î VCC =.5 V 3 Î VID = 1 V VID = 1 V Figure VIC Common-Mode Input Voltage V Data for temperatures below C and above 7 C and for supply voltages below.75 V and above 5.25 V are applicable to SN55115 circuits only. These parameters were measured with the active pullup connected to the sink output. POST OFFICE BOX DALLAS, TEXAS
8 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 TYPICAL CHARACTERISTICS VOH V High-Level Output Voltage V HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT CURRENT Î VID =.5 V Î TA = 25 C Î Î VCC = 5.5 V Î VCC = 5 V Î VCC =.5 V Î VOL V Low-Level Output Voltge V LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT VID =.5 V TA = 25 C VCC =.5 V Î VCC = 5.5 V IOH High-Level Output Current ma IOL Low-Level Output Current ma 3 Figure 5 Figure 6 VO V O Output Voltage V Á Á 1.2 OUTPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE TA = 125 C TA = 25 C VCC = 5 V Load = 2 kω to VCC TA = 55 C VO V O Output Voltage V OUTPUT VOLTAGE DIFFERENTIAL INPUT VOLTAGE VCC = 5.5 V VCC = 5 V VCC =.5 V Load = 2 kω to VCC TA = 25 C VID Differential Input Voltage V VID Differential Input Voltage V Figure 7 Figure 8 8 POST OFFICE BOX DALLAS, TEXAS 75265
9 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS TYPICAL CHARACTERISTICS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 VO V O Output Voltage V VCC = 5.5 V VCC = 5 V VCC =.5 V OUTPUT VOLTAGE STROBE INPUT VOLTAGE Á No Load Á Î VID =.5 V Á Î TA = 25 C Á VO V O Output Voltage V OUTPUT VOLTAGE STROBE INPUT VOLTAGE TA = 125 C TA = 55 C TA = 25 C VCC = 5 V No Load VID =.5 V Vstrobe Strobe Input Voltage V Vstrobe Strobe Input Voltage V Figure 9 Figure 1 ICC Supply Current ma No Load TA = 25 C SUPPLY CURRENT (BOTH RECEIVERS) SUPPLY VOLTAGE B Input at VCC A Input at V B Input at V A Input at VCC ICC Supply Current ma SUPPLY CURRENT (BOTH RECEIVERS) FREE-AIR TEMPERATURE 1 VCC = 5.5 V 5 B Input at 5.5 V A Input at V VCC Supply Voltage V TA Free-Air Temperature C Figure 11 Figure 12 Data for temperatures below C and above 7 C and for supply voltages below.75 V and above 5.25 V are applicable to SN55115 circuits only. These parameters were measured with the active pullup connected to the sink output. POST OFFICE BOX DALLAS, TEXAS
10 SN55115, SN75115 DUAL DIFFERENTIAL RECEIVERS SLLS72D SEPTEMBER 1973 REVISED MAY 1998 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIMES FREE-AIR TEMPERATURE MAXIMUM OPERATING FREQUENCY RESPONSE-TIME-CONTROL CAPACITANCE Propagation Delay Times ns VCC = 5 V See Figure 1 tphl (RL = 39 Ω) tplh (RL = 3.9 kω) TA Free-Air Temperature C 125 fmax Maximum Operating Frequency Hz 1M 1M 1k 1k VCC = 5 V Input:.5-V to.5-v Square Wave ÎÎ TA = 25 C Response-Time-Control Capacitance µf 1 Figure 13 Figure 1 Data for temperatures below C and above 7 C and for supply voltages below.75 V and above 5.25 V are applicable to SN55115 circuits only. These parameters were measured with the active pullup connected to the sink output. APPLICATION INFORMATION Location 3 Location 5 ZO ZO Location 1 Location 6 Location 2 Twisted Pair Location SN75113 Driver SN75115 Receiver ZO = RT. A capacitor may be connected in series with ZO to reduce power dissipation. Figure 15. Basic Party-Line or Data-Bus Differential Data Transmission 1 POST OFFICE BOX DALLAS, TEXAS 75265
11 PACKAGE OPTION ADDENDUM 17-Dec-215 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp ( C) A ACTIVE LCCC FK 2 1 TBD POST-PLATE N / A for Pkg Type -55 to A SNJ55 115FK Device Marking FA ACTIVE CFP W 16 1 TBD A2 N / A for Pkg Type -55 to FA SNJ55115W JM3851/1BEA ACTIVE CDIP J 16 1 TBD A2 N / A for Pkg Type -55 to 125 JM3851 /1BEA M3851/1BEA ACTIVE CDIP J 16 1 TBD A2 N / A for Pkg Type -55 to 125 JM3851 /1BEA SN55115J ACTIVE CDIP J 16 1 TBD A2 N / A for Pkg Type -55 to 125 SN55115J (/5) Samples SN75115D ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) SN75115DE ACTIVE SOIC D 16 Green (RoHS & no Sb/Br) SN75115DR ACTIVE SOIC D Green (RoHS & no Sb/Br) SN75115N ACTIVE PDIP N Pb-Free (RoHS) SN75115NE ACTIVE PDIP N Pb-Free (RoHS) SN75115NSR ACTIVE SO NS 16 2 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-26C-UNLIM to 7 SN75115 CU NIPDAU Level-1-26C-UNLIM to 7 SN75115 CU NIPDAU Level-1-26C-UNLIM to 7 SN75115 CU NIPDAU N / A for Pkg Type to 7 SN75115N CU NIPDAU N / A for Pkg Type to 7 SN75115N CU NIPDAU Level-1-26C-UNLIM to 7 SN75115 SNJ55115FK ACTIVE LCCC FK 2 1 TBD POST-PLATE N / A for Pkg Type -55 to A SNJ55 115FK SNJ55115J ACTIVE CDIP J 16 1 TBD A2 N / A for Pkg Type -55 to 125 SNJ55115J SNJ55115W ACTIVE CFP W 16 1 TBD A2 N / A for Pkg Type -55 to FA SNJ55115W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. Addendum-Page 1
12 PACKAGE OPTION ADDENDUM 17-Dec-215 NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. () There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN55115, SN75115 : Catalog: SN75115 Military: SN55115 NOTE: Qualified Version Definitions: Addendum-Page 2
13 PACKAGE OPTION ADDENDUM 17-Dec-215 Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications Addendum-Page 3
14 PACKAGE MATERIALS INFORMATION 1-Jul-212 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A (mm) B (mm) K (mm) P1 (mm) W (mm) Pin1 Quadrant SN75115DR SOIC D Q1 SN75115NSR SO NS Q1 Pack Materials-Page 1
15 PACKAGE MATERIALS INFORMATION 1-Jul-212 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75115DR SOIC D SN75115NSR SO NS Pack Materials-Page 2
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