Bin. Befehl mnem. Op. meaning operation Flags clocks

Bin. Befehl mnem. Op. meaning operation Flags clocks 0000000000000000 nop no operation 00000001ddddrrrr movw v,v copy register word Rd+1:Rd Rr+1:Rr 1 00000010ddddrrrr muls d,d multiply signed R1:R0 Rd*Rr ZC 2 000000110ddd0rrr mulsu a,a multiply signed with unsigned R1:R0 Rd*Rr ZC 2 000000110ddd1rrr fmul a,a fractional multiply unsigned R1:R0 (Rd*Rr)<<1 ZC 2 000000111ddd0rrr fmuls a,a fractional multiply signed R1:R0 (Rd*Rr)<<1 ZC 2 000000111ddd1rrr fmulsu a,a fr. multiply signed with unsigned R1:R0 (Rd*Rr)<<1 ZC 2 000001rdddddrrrr cpc r,r compare with carry Rd Rr ZCNVH 1 000010rdddddrrrr sbc r,r subtract with carry Rd Rd - Rr - C ZCNVH 1 000011rdddddrrrr lsl r logical shift left Rd (n+1) Rd (n),rd (0) 0 ZCNV 1 000011rdddddrrrr add r,r add two registers Rd Rd + Rr ZCNVH 1 000100rdddddrrrr cpse r,r compare, skip if equal if (Rd==Rr) PC+=2 or 3 1/2/3 000101rdddddrrrr cp r,r compare Rd Rr ZCNVH 1 000110rdddddrrrr sub r,r subtract two registers Rd Rd Rr ZCNVH 1 000111rdddddrrrr rol r rotate left through carry Rd (0) C,Rd (n+1) Rd (n),c Rd (7) ZCNV 1 000111rdddddrrrr adc r,r add with carry Rd Rd + Rr + C ZCNVH 1 001000rdddddrrrr and r,r logical AND Rd Rd & Rr ZNV 1 001000rdddddrrrr tst r test for zero or minus Rd Rd and Rd ZNV 1 001001rdddddrrrr eor r,r exclusiv or Rd Rd xor Rr ZNV 1 001001rdddddrrrr clr r clear register Rd Rd xor Rd ZNV 1 001010rdddddrrrr or r,r logical OR Rd Rd Rr ZNV 1 001011rdddddrrrr mov r,r move between registers Rd Rr 1 0011KKKKddddKKKK cpi d,m compare reg with constant Rd K ZNVCH 1 0100KKKKddddKKKK sbci d,m subtract with carry const from reg Rd Rd -C -K ZNVCH 1 0101KKKKddddKKKK subi d,m subtract constant from register Rd Rd -K ZNVCH 1 0110KKKKddddKKKK ori d,m logical OR with constant Rd Rd K ZNV 1 Seite 1

0110KKKKddddKKKK sbr d,m set bits in register Rd Rd K ZNV 1 0111KKKKddddKKKK andi d,m logical and with immidiate Rd Rd and K ZNV 1 0111KKKKddddKKKK cbr d,n clear bits in register Rd Rd and (0xFF K) ZNV 1 100!000dddddee-+ ld r,e load from X,Y,Z Rd [X],[Y],[Z],/++/--, pre/post 2 100!001rrrrree-+ st e,r store into X,Y,Z [X],[Y],[Z],/++/--, pre/post Rr 2 1001000ddddd0000 lds r,i load direct fvrom SRAM Rd [16 Bit Constant] 2 1001000ddddd010+ lpm r,z load program memory Rd [Z], ev. Z++ 3 1001000ddddd011+ elpm r,z 1001000rrrrr1111 pop r pop register from stack Rd Stack 2 1001001ddddd0000 sts i,r store direct to SRAM [16 Bit Constant] Rr 1001001rrrrr1111 push r push register into stack Stack Rr 2 1001010000001000 sec set carry C 1 C 1 1001010000001001 ijmp indirect jump to Z PC Z 2 1001010000011000 sez set zero flag Z 0 Z 1 1001010000101000 sen set negative flag N 1 N 1 1001010000111000 sev set Two complents overflow V 1 V 1 1001010001001000 ses set signed test flag S 1 S 1 1001010001011000 seh set half carry flag H 1 H 1 1001010001101000 set set T in SREG T 1 T 1 1001010001111000 sei set global Interrupt (enable Int) I 1 I 1 100101000SSS1000 bset S set flag SREG[s]=1 S 1 1001010010001000 clc clear carry C 0 C 1 1001010010011000 clz clear zero flag Z 0 Z 1 1001010010101000 cln clear negative flag N 0 N 1 1001010010111000 clv clear two complents overflow V 0 V 1 1001010011001000 cls clear signed test flag S 0 S 1 1001010011011000 clh clear half carry flag H 0 H 1 1001010011101000 clt clear T in SREG T 0 T 1 Seite 2

1001010011111000 cli clear global Interrupt (disable Int) I 0 I 1 100101001SSS1000 bclr S clear flag SREG[s]=0 S 1 1001010100001000 ret return PC Stack 4 1001010100001001 icall indirect call to Z PC Z 3 1001010100011000 reti return from Int PC Stack I 4 1001010100011001 eicall 1001010110001000 sleep sleep 1 1001010110011000 break 1001010110101000 wdr watch dog reset 1 1001010111001000 lpm? load program memory R0 [Z] 3 1001010111011000 elpm? 1001010111101000 spm store into program memory [Z] R1:R0 0 1001010hhhhh110h jmp h 1001010hhhhh111h call h 1001010rrrrr0000 com r one's complement Rd 0xFF - Rd ZCNV 1 1001010rrrrr0001 neg r two's complement Rd 0x00 - Rd ZCNV 1 1001010rrrrr0010 swap r swap nibbles Rd (0..3) Rd (4..7) 1 1001010rrrrr0011 inc r increment register Rd++ ZNV 1 1001010rrrrr0101 asr r arithmetic shift right Rd (n) Rd (n+1),n=0..6 ZCNV 1 1001010rrrrr0110 lsr r logical shift right Rd (n+1) Rd (n), Rd 0 (0) 1001010rrrrr0111 ror r rotation rignt over carry Rd (7) C, Rd (n) Rd (n+1),c Rd (0) ZCNV 1 1001010rrrrr1010 dec r decrement register Rd-- ZNV 1 10010110KKddKKKK adiw w,k add immediate to word Rdh:Rdl Rdh:Rdl + Constant CZHVS 2 10010111KKddKKKK sbiw w,k subtract constant from wordreg. Rdh:Rdl Rdh:Rdl - Constant CZHVS 2 10011000pppppsss cbi p,s clear bit in I/O register I/O(P,b) 0 2 10011001pppppsss sbic p,s skip, if Bit in I/O reg. Is clear If P(b) ==0 PC PC+ 2, 3 1/2/3 10011010pppppsss sbi p,s set bit in I/O register I/O(P,b) 1 2 10011011pppppsss sbis p,s skip, if bit in I/O reg. Is set If P(b) ==1 PC PC+ 2, 3 1/2/3 Seite 3

100111rdddddrrrr mul r,r multiply unsigned R1:R0 RD*Rr ZC 2 10110PPdddddPPPP in r,p in port Rd Port 1 10111PPrrrrrPPPP out P,r out to port Port Rr 1 10o0oo0dddddbooo ldd r,b load indirect with displacement Rd [Y+disp], Rd [Z+disp] 2 10o0oo1rrrrrbooo std b,r store indirect with displacement [Y+disp] Rd, [Z+disp] Rd 2 1100LLLLLLLLLLLL rjmp L relative jump PC PC + k +1 2 1101LLLLLLLLLLLL rcall L relative call PC PC + k +1 3 11101111dddd1111 ser d set register Rd 0xFF 1 1110KKKKddddKKKK ldi d,m load immidiate Rd K 1 111100lllllll000 brcs l branch, if C ist set if (C==1) PC PC + k + 1 1/ 2 111100lllllll000 brlo l branch, if lower if (C==1) PC PC + k + 1 1/ 2 111100lllllll001 breq l branch, if equal if (Z==1) PC PC + k + 1 1/ 2 111100lllllll010 brmi l branch, if minus if (N==1) PC PC + k + 1 1/ 2 111100lllllll011 brvs l branch, if overflow is set if (V==1) PC PC + k + 1 1/ 2 111100lllllll100 brlt l branch, if less then zero signed if ((N xor V)==1) PC PC + k + 1 1/ 2 111100lllllll101 brhs l branch, if halfcarry if (H==1) PC PC + k + 1 1/ 2 111100lllllll110 brts l branch, if T is set if (T==1) PC PC + k + 1 1/ 2 111100lllllll111 brie l branch, if interrupt enabled if (I==1) PC PC + k + 1 1/ 2 111100lllllllsss brbs s,l branch, if status flag set if (SREG(s)==1) PC PC + k + 1 1/ 2 111101lllllll000 brsh l branch, if same or higher if (C==0) PC PC + k + 1 1/ 2 111101lllllll000 brcc l branch, if carry cleared if (C==0) PC PC + k + 1 1/ 2 111101lllllll001 brne l branch, if not equal if (Z==0) PC PC + k + 1 1/ 2 111101lllllll010 brpl l branch, if plus if (N==0) PC PC + k + 1 1/ 2 111101lllllll011 brvc l branch, if overflow is clear if (V==0) PC PC + k + 1 1/ 2 111101lllllll100 brge l branch, if geater oder equal, signed if ((N xor V) ==0) PC PC + k + 1 1/ 2 111101lllllll101 brhc l branch, if halfcarry clear if (H==0) PC PC + k + 1 1/ 2 111101lllllll110 brtc l branch, if T claer if (T==0) PC PC + k + 1 1/ 2 111101lllllll111 brid l branch, if interrupt disabled if (I==0) PC PC + k + 1 1/ 2 Seite 4

111101lllllllsss brbc s,l branch, if status flag clear if (SREG(s)==0) PC PC + k + 1 1/ 2 1111100ddddd0sss bld r,s bit load from T to register Rd(s) T 1 1111101ddddd0sss bst r,s bit store from register to T T Rd(s) 1 1111110rrrrr0sss sbrc r,s skip, if bit in reg. Is clear If R(b) ==0 PC PC+ 2, 3 1/2/3 1111111rrrrr0sss sbrs r,s skip, if bit in reg. Is set If R(b) ==1 PC PC+ 2, 3 1/2/3 1001010000011001 eijmp Legend: r any register d `ldi' register (r16-r31) v `movw' even register (r0, r2,..., r28, r30) a `fmul' register (r16-r23) w `adiw' register (r24,r26,r28,r30) e pointer registers (X,Y,Z) b base pointer register and displacement ([YZ]+disp) z Z pointer register (for [e]lpm Rd,Z[+]) M immediate value from 0 to 255 n immediate value from 0 to 255 ( n = ~M ). s immediate value from 0 to 7 P Port address value from 0 to 63. (in, out) p Port address value from 0 to??? (cbi, sbi, sbic, sbis) K immediate value from 0 to 63 (used in `adiw', `sbiw') i immediate value l signed pc relative offset from -64 to 63 L signed pc relative offset from -2048 to 2047 h absolute code address (call, jmp) S immediate value from 0 to 7 (S = s << 4)? use this opcode entry if no parameters, else use next opcode entry Seite 5

Zusammengestellt aus: http://sourceware.org/binutils/docs-2.20/as/avr-opcodes.html#avr-opcodes Manual Atmega8, instruction summery A. Beck, 2010 Atmega8 Maschinenbefehle A. Beck, 04/2010 Seite 6

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T ist ein Bitspeicher für 1 Bit Seite 8

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