User manual Spice model tutorial for Power MOSFETs Introduction This document describes ST s Spice model versions available for Power MOSFETs. This is a guide designed to support user choosing the best model for his goals. In fact, it explains the features of different model versions both in terms of static and dynamic characteristics and simulation performance, in order to find the right compromise between the computation time and accuracy. For example, the self-heating model (V3 version), which accurately reproduces the thermal response of all electrical parameters, requires a considerable simulation effort. Finally, an example shows how the self-heating model works. Spice models describe the characteristics of typical devices and don't guarantee the absolute representation of product specifications and operating characteristics; the datasheet is the only document providing product specifications. Although simulation is a very important tool to evaluate the device s performance, the exact device s behavior in all situations is not predictable, therefore the final laboratory test is necessary. November 2013 Doc ID 023670 Rev 1 1/24 www.st.com
Spice model versions UM1575 1 Spice model versions ST provides 6 model versions on each part number: partnumber_v1c partnumber_v1t partnumber_v2 partnumber_v3 partnumber_v4 partnumber_tn V1C version It is the basic model (LEVEL =3) enclosing C oss and C rss modeling through capacitance profile tables. It is an empirical model, and it assumes a 27 C constant temperature. V1T version It comes directly from V1C version and it also includes the package thermal modeling through a thermal equivalent network and presents two additional external thermal nodes T j and T case. This version hasn't the dynamic link between Power MOSFET temperature and internal parameters. V2 version It is more advanced than V1C, in fact it takes into account the temperature dependence and capacitance profiles too. It allows the static and dynamic behavior to be reproduced by user at fixed temperatures. By using this version, the simulation of self-heating effects isn't possible. V3 version It comes directly from V2 version and includes the package thermal model through a thermal equivalent network and presents two additional external thermal nodes: T j and T case. In this version, during each transient, the current power dissipation is calculated and a current proportional to this power is fed into the thermal network. In this way, the voltage at T j node contains all the information about the junction temperature, which changes internal device s parameters. Since it is a monitoring node, usually T j pin is not connected (however, to avoid warning messages on this node, the user has to add a floating wire - see Figure 1). On contrary, T case node has to be connected, either to a constant voltage source Vdc representing the ambient temperature or to a heat sink modeled by its own thermal network (Figure 1). V4 version It comes directly from V3 version considering the device sited in free air. It includes the package thermal modeling through a thermal equivalent network and presents three additional external thermal nodes: T j, T case and T amb. The voltage at T j node and T case node contains all the information about the junction temperature and case temperature which change internal device s parameters. Since they are monitoring nodes, usually T j and T case pins are not connected (however, to avoid warning messages on this node, the user has to add a floating wire - see Figure 1). Conversely, T amb node has to be connected: to a constant voltage source Vdc, representing the ambient temperature. 2/24 Doc ID 023670 Rev 1
Spice model versions TN version It includes the RC thermal network only, which represents the thermal model of the package. Its symbol has two pins: T j and T case. Figure 1. Self-heating model (V3 version) D TJ D TJ R1 R2 G S Zth Tcase 25 Tamb G S Zth Tcase C1 C2 25 Tamb 0 0 GIPD081020130954FSR Note: T j is a monitoring node and it is not connected; T case is connected either by using a Vdc, representing the ambient temperature (on the left-side), or by heat-sink thermal network (on the right-side). Doc ID 023670 Rev 1 3/24 24
Spice model symbol UM1575 2 Spice model symbol For each model version, ST provides the appropriate symbol as shown below: Figure 2. Model symbols V1C version V2 version V4 version D G Zth TJ Tcase S Tamb V1T version V3 version TN version TJ D Tcase G Zth TJ 1 TJ TCASE 2 Tcase S GIPD081020131007FSR 4/24 Doc ID 023670 Rev 1
Spice models - instructions to simulate 3 Spice models - instructions to simulate In Spice simulator, user has to upload the device symbol (.OLB file) and the Spice model (.LIB file) to simulate transistors in the schematic. 3.1 Installation In the package model, there are the following files: name.lib text file representing the model library written as a Spice code; name.olb symbol file to use the model into Orcad capture user interface. In Capture open the menu dialog window "Pspice" "Edit Simulation Profile". Go to "Configuration Files" tab and "Library" category. Select the library (*.lib) path by "Browse " button and click to "Add to Design" (see Figure 3) Figure 3. Capture dialog window to select the library (*.lib) GIPD081020131721FSR To include the symbol *.olb in the schematic view, open the menu dialog window "Place" "Part" (or simply pressing "P" key in keyboard) and click the "Add Library " button (or pressing Alt+"A") to select the file (see figure below). Doc ID 023670 Rev 1 5/24 24
Spice models - instructions to simulate UM1575 Figure 4. Capture dialog window to include the symbol (*.olb) Finally, you can simulate your circuit choosing the simulation type and parameters. GIPD081020131724FSR 3.2 Typical simulation parameters / options As our models contain many non-linear elements, the standard simulation parameters are often not suitable. The following values can facilitate convergence (set them in dialog window "Pspice" "Edit Simulation Profile" "Options" tab): ABSTOL= 1nA CHGTOL= 1 pc..10 pc ITL1= 150 ITL2= 20...150 ITL4= 20...150 RELTOL= 0.001...0.01 (best accuracy of currents) (best accuracy of charges) (DC and bias 'blind' iteration limit) (DC and bias 'best guess' iteration limit) (transient time point iteration limit) (relative accuracy of voltages and currents) Note: If the following error message appears during the simulation of one of device models: ==> INTERNAL ERROR -- Overflow in device... <== you have to edit the 'PSPICE.INI' file by inserting the following line behind the headline [PSPICE] as follows: [PSPICE] MathExceptions = off... DO NOT CHANGE ANY OTHER LINES ALREADY PRESENT 6/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) 4 A brief description of self-heating model (V3 version) Power MOSFET s Spice models are behavioral and achieved by fitting simulated data with static and dynamic characterization results. The behavioral model is the best approach because it reproduces the electrical and thermal behavior of the power device through a simplified physical description of the device consisting in a set of equations ruling its behavior at terminal level. The self-heating model (V3 version) includes different analog behavioral models (ABM) to describe resistors, voltage and current generator, which are temperature-dependent. A curve fit optimization algorithm extracts the mathematical expression for ABM, which yields a good representation of Power MOSFET s static and dynamic characteristics. In Figure 5, the self-heating spice model (V3 version) schematic is shown. Doc ID 023670 Rev 1 7/24 24
A brief description of self-heating model (V3 version) UM1575 Figure 5. Power MOSFET self-heating model schematic R_g3 Rdd11 G63 IN+ IN- G_Rmos OUT+ OUT- 0Vdc IN+ IN- G_Rs OUT+ OUT- 1 IN+ IN- E22 OUT+ OUT- V_sense3 RTj13 RTj14 RTj15 RTj16 RTj6 T1 T2 T3 T4 IN+ ss IN- OUT+ Cj1 Cj2 Cj3 Cj4 Cj5 OUT- G_power R_Gpower 1 2 2 Ecap (table) IN+ IN- OUT+ OUT- IN+ IN- E2 OUT+ OUT- 2 Lg g2 1 2 Rg6 IN+ OUT+ IN- OUT- Gcdg Rdd9 Rdd10 0Vdc 2 1 1 2 Gate Crss modeling alfa 0 40 Cref 50 V2 0 R_cgs Rcap g Crss modeling CGS 0 DC modelling 1 RLd d1k d1y d1x d1 dd d IN+ IN- OUT+ OUT- G_Rmos s Ls 3 Drain Ld Coss modeling Rd Rx1 Vread2 R_Gdiode R_Rmos DC diode modeling d1z G60 OUT+ IN+ OUT- IN- G_R_did G59 OUT+ IN+ OUT- IN- G_R_did Ecap2 (table) IN+ IN- OUT+ OUT- 402 0 alfa2 502 Cref2 V22 Rcap2 R_ds Coss modelling IN+ IN- Gcdg2 OUT+ OUT- OUT+ OUT- d1bvdss1 sx OUT+ IN+ OUT- IN- G_BVdss R_GBDSS BVdss modelling 0 C_Cds 0 d d_dedep edep R_edep OUT+ OUT- IN+ IN- E_E001 Recovery diode modelling R_R003 aa 0 C 0 R_R001 ba IN+ IN- E_E001 Tj Cj6 Tcase RLs 0 0 Source Thermal impedance modeling GIPD081020131034FSR 8/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) 4.1 Thermal network Thermal impedance network represents the basic element, which is featured inside the macro-model. It is used to transform the power dissipated inside the junction into a voltage representing the temperature (T j ). Figure 6. Physical structure The voltage drop across the network is detected and used as emitter value inside behavioral equations used to model other parameters. Thermal impedance is the experimental data required to obtain the Cauer model (see Figure 6). Figure 7. Thermal impedance profile and Cauer model Doc ID 023670 Rev 1 9/24 24
A brief description of self-heating model (V3 version) UM1575 4.2 Experimental data used to fit the model The model implementation requires the following experimental data: Typ. output characteristics at different temperatures Typ. transfer characteristics at different temperatures Typ. drain source breakdown voltage at different temperatures Typ. drain source on state resistance vs temperature Typ. gate threshold voltage vs temperature Typ. forward diode characteristics Typ. capacitances profile vs VDS Typ. gate charge Typ. switching on resistive load Typ. switching on inductive load Typ. free-wheeling diode characteristics Unclamped inductive switching Switching losses vs gate resistance Equivalent capacitance time related (C o(tr) ) Equivalent capacitance energy related (C o(er) ) Max. transient thermal impedance Figure 8. Simulated and measured output characteristics Figure 9. Simulated curves at V GS = 10 V 10/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) Figure 10. Normalized R DS(on) vs temperature Figure 11. Normalized gate threshold voltage vs temperature RDS(on) (norm) 2.1 ID=2.5A AM06484v1 VGS(th) (norm) 1.10 ID=250µA AM06483v1 1.9 1.7 1.00 1.5 1.3 0.90 1.1 0.9 0.80 0.7 0.5-50 -25 0 25 50 75 100 TJ( C) 0.70-50 -25 0 25 50 75 100 TJ( C) 4.3 C OSS and C RSS model Charge and current formulas for a linear capacitor are: Q = C V it () = C dv ------ dt For a non linear (voltage-dependent) time-independent capacitor these formulas become: Q dv = C( V) dv it () = CV ( ) ------ dt The C(V) function is obtained by lookup table. Figure 12. Capacitance profiles C (pf) AM06481v1 1000 Ciss 100 10 Coss Crss 1 0.1 1 10 100 VDS(V) Doc ID 023670 Rev 1 11/24 24
A brief description of self-heating model (V3 version) UM1575 4.4 Example of dynamic characteristics 4.4.1 Gate charge Figure 13. Gate charge - schematic Rload1 Ipulse1 R127 0 0 0 0 Vdd1 GIPD251020131424FSR Figure 14. Gate charge - simulated waveforms 12/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) Figure 15. Gate charge - experimental waveforms GIPD251020131457FSR 4.4.2 Switching on inductive load Figure 16. Switching on inductive load - schematic Iload1 Lpar1 R127 Vdd1 Rgate1 Vpulse1 L33 0 GIPD251020131432FSR Doc ID 023670 Rev 1 13/24 24
A brief description of self-heating model (V3 version) UM1575 Figure 17. Switching on inductive load - simulated waveforms Figure 18. Switching on inductive load - experimental waveforms GIPD251020131502FSR 14/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) 4.4.3 E off vs R gate Figure 19. E off vs R gate - schematic Iload1 Lpar1 R127 Vdd1 Rgate1 Vpulse1 L33 0 GIPD251020131432FSR Figure 20. E off vs R gate - experimental waveforms GIPD251020131506FSR Doc ID 023670 Rev 1 15/24 24
A brief description of self-heating model (V3 version) UM1575 Table 1. E off (comparison simulated/measured) R G (Ω) Measured E off (µj) Simulated E off (µj) 4.7 4.1 3.9 10 4.31 4.4 47 6.8 7.1 200 27 29 4.4.4 Recovery diode Figure 21. Recovery diode - schematic Iload1 Lpar1 R127 Vdd1 Rgate1 Vpulse1 L33 0 GIPD251020131432FSR 16/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) Figure 22. Recovery diode - simulated waveforms Doc ID 023670 Rev 1 17/24 24
A brief description of self-heating model (V3 version) UM1575 4.4.5 Unclamped inductive switching Table 2. Simulated test conditions Test T C Energy I drain ΔT j 1 110 C 0.3 J 83 A 83 C 2 110 C 0.3 J 203 A 133 C Figure 23. Unclamped inductive switching - schematic Figure 24. Unclamped inductive switching - simulated waveforms (test 1) GIPD251020131511FSR 18/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) Figure 25. Unclamped inductive switching - simulated waveforms (test 2) GIPD251020131513FSR Figure 26. Unclamped inductive switching - experimental waveforms GIPD251020131518FSR Doc ID 023670 Rev 1 19/24 24
A brief description of self-heating model (V3 version) UM1575 4.4.6 Short-circuit test Figure 27. Short-circuit test - schematic Figure 28. Short-circuit test - waveforms 20/24 Doc ID 023670 Rev 1
A brief description of self-heating model (V3 version) 4.4.7 Flyback simulated by self-heating model Figure 29. Flyback simulated by self-heating model - schematic Figure 30. Flyback simulated by self-heating model - simulated waveforms GIPD251020131521FSR Doc ID 023670 Rev 1 21/24 24
A brief description of self-heating model (V3 version) UM1575 where: Blue line = (Tx current sec)/10 Black line = (Tx current Pri) Red line = MOSFET drain current If you have further questions, feel free to contact us via our local sale offices. 22/24 Doc ID 023670 Rev 1
Revision history 5 Revision history Table 3. Document revision history Date Revision Changes 25-Nov-2013 1 Initial release. Doc ID 023670 Rev 1 23/24 24
Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 24/24 Doc ID 023670 Rev 1