Data Sheet FEATURES High speed MHz bandwidth, gain = V/µs slew rate 9 ns settling time to.% Ideal for video applications.% differential gain. differential phase Low noise.7 nv/ Hz input voltage noise. pa/ Hz input current noise Excellent dc precision mv maximum input offset voltage (over temperature). µv/ C input offset drift Flexible operation Specified for ± V to ± V operation ± V output swing into a Ω load External compensation for gains to ma supply current Available in tape and reel in accordance with EIA-8A standard GENERAL DESCRIPTION The is a low noise (.7 nv/ Hz), high speed op amp with custom compensation that provides the user with gains of to while maintaining a bandwidth > MHz. Its. differential phase and.% differential gain performance at.8 MHz and. MHz, driving reverse-terminated Ω or 7 Ω cables, makes it ideally suited for professional video applications. The achieves its V/µs uncompensated slew rate and 7 MHz gain bandwidth while requiring only ma of current from power supplies. The external compensation pin of the gives it exceptional versatility. For example, compensation can be selected to optimize the bandwidth for a given load and power supply voltage. As a gain-of- line driver, the db bandwidth can be increased to 9 MHz at the expense of db of peaking. Its output can also be clamped at its external compensation pin. The exhibits excellent dc performance. It offers a minimum open-loop gain of V/mV into loads as low as Ω, a low input voltage noise of.7 nv/ Hz, and a low input offset voltage of mv maximum. Common-mode rejection and power supply rejection ratios are both db. This op amp is also useful in multichannel, high speed data conversion where its fast (9 ns to.%) settling time is important. In such applications, the serves as an input buffer for 8-bit to -bit ADCs and as an output I/V converter for high speed DACs. Rev. I Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. High Speed, Low Noise Video Op Amp CONNECTION DIAGRAM OFFSET NULL IN +IN V S TOP VIEW (Not to Scale) Figure. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) NC IN NC +IN 7 NC 8 NC OFFSET NULL NC = NO CONNECT 9 9 V NC NC OFFSET NULL Figure. -Terminal LCC 8 OFFSET NULL 7 +V S OUTPUT 8 NC 7 +V NC OUTPUT NC Operating as a traditional voltage feedback amplifier, the provides many of the advantages that a transimpedance amplifier offer. A bandwidth > MHz can be maintained for a range of gains through the replacement of the external compensation capacitor. The and the transimpedance amplifier are both unity-gain stable and provide similar voltage noise performance (.7 nv/ Hz); however, the current noise of the (. pa/ Hz) is less than % of the noise of transimpedance amplifiers. The inputs of the are symmetrical. PRODUCT HIGHLIGHTS. The input voltage noise of nv/ Hz, current noise of. pa/ Hz, and MHz bandwidth for gains of to make the an ideal preamp.. A differential phase error of. and a.% differential gain error, at the.8 MHz NTSC,. MHz PAL, and SECAM color subcarrier frequencies, make the op amp an outstanding video performer for driving reverse-terminated Ω and 7 Ω cables to ± V (at their terminated end).. The can drive heavy capacitive loads.. Performance is fully specified for operation from ± V to ± V supplies.. The is available in PDIP, CERDIP, and small outline packages. Chips and MIL-STD-88B parts are also available. The 8-lead SOIC is available for the extended temperature range ( C to + C). One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 78.9.7 www.analog.com Fax: 78.. Analog Devices, Inc. All rights reserved. NC TOP VIEW (Not to Scale) NC NC 88-88-
TABLE OF CONTENTS Features... General Description... Connection Diagram... Product Highlights... Revision History... Specifications... Absolute Maximum Ratings... Thermal Characteristics... Metallization Photo... ESD Caution... Typical Performance Characteristics... Data Sheet Test Circuits... Theory of Operation... Externally Compensating the... Shunt Compensation... Current Feedback Compensation... Low Error Video Line Driver... High Gain Video Bandwidth, -Op-Amp Instrumentation Amplifier... Outline Dimensions... 7 Ordering Guide... 9 REVISION HISTORY / Rev. H to Rev. I Change to Table... /9 Rev. G to Rev. H Changes to Features... Changes to Quiescent Current Parameter, Table... Changes to Table... Added Thermal Characteristics Section and Table... Updated Outline Dimensions... 7 Changes to Ordering Guide... 9 / Rev. E to Rev. F Renumbered Figures... Universal Changes to Product Highlights... Changes to Specifications... Changes to Absolute Maximum Ratings... Changes to Ordering Guide... Updated Outline Dimensions... / Rev. F to Rev. G Added Figure ; Renumbered Sequentially... Changes to Ordering Guide... Updated Table I... Updated Figure... Updated Figure... Updated Outline Dimensions... Rev. I Page of
Data Sheet SPECIFICATIONS TA = C and VS = ± V dc, unless otherwise noted. Table. JR AR AQ/S Parameter Conditions VS Min Typ Max Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE tmin to tmax ± V,.... mv ± V. mv Offset Voltage Drift ± V,... µv/ C ± V INPUT BIAS CURRENT ± V,. 7. 7. 7 µa ± V tmin to tmax 8. 9. 9. µa INPUT OFFSET CURRENT ± V, na ± V tmin to tmax na Offset Current Drift ± V,... na/ C ± V OPEN-LOOP GAIN VO = ±. V, ± V V/mV RL = Ω RL = Ω V/mV tmin to tmax V/mV VO = ± V, ± V V/mV RL = kω RL = Ω 8 8 8 V/mV tmin to tmax V/mV DYNAMIC PERFORMANCE Gain Bandwidth Product ± V MHz ± V 7 7 7 MHz Full Power Bandwidth, VO = V p-p, ± V MHz RL = Ω VO = V p-p, ± V... MHz RL = kω Slew Rate RL = Ω ± V V/µs RL = kω ± V V/µs Settling Time to.% AV = 9. V to ± V ns +. V V step ± V 9 9 9 ns Phase Margin CL = pf ± V RL = kω Degrees DIFFERENTIAL GAIN ERROR RL = Ω, ± V... % CCOMP = pf DIFFERENTIAL PHASE ERROR RL = Ω, ± V... Degrees CCOMP = pf COMMON-MODE REJECTION VCM = ±. V ± V db VCM = ± V ± V db tmin to tmax 9 9 9 db POWER SUPPLY REJECTION VS = ±. V 98 98 98 db to ±8 V tmin to tmax 9 9 9 db INPUT VOLTAGE NOISE f = khz ± V.7.7.7 nv/ Hz INPUT CURRENT NOISE f = khz ± V... pa/ Hz Rev. I Page of
Data Sheet JR AR AQ/S Parameter Conditions VS Min Typ Max Min Typ Max Min Typ Max Unit INPUT COMMON-MODE ± V +. +. +. V VOLTAGE RANGE.8.8.8 V ± V +. +. +. V.8.8.8 V OUTPUT VOLTAGE SWING RL = Ω ± V ±. ±. ±. ±. ±. ±. V RL = Ω ± V ±. ±. ±. ±. ±. ±. V RL = Ω ± V ±. ±. ±. V RL = kω ± V ± ±. ± ±. ± ±. V RL = Ω ± V ± ±. ± ±. ± ±. V Short-Circuit Current ± V, ma ± V INPUT CHARACTERISTICS Input Resistance kω (Differential) Input Capacitance pf (Differential) Input Capacitance... pf (Common Mode) CLOSED-LOOP OUTPUT AV = +, mω RESISTANCE f = khz POWER SUPPLY Operating Range ±. ±8 ±. ±8 ±. ±8 V Quiescent Current ± V... ma tmin to tmax 8. 8. 8.7 ma ± V..8..8..8 ma tmin to tmax 8. 9. 9. ma TRANSISTOR COUNT Number of transistors Full power bandwidth = slew rate/ π VPEAK. Tested at gain =, CCOMP = pf..8 MHz (NTSC) and. MHz (PAL and SECAM). Differential input capacitance consists of. pf package capacitance plus. pf from the input differential pair. Rev. I Page of
Data Sheet ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage ±8 V Internal Power Dissipation 8-Lead PDIP (N). W 8-Lead SOIC (R).9 W 8-Lead CERDIP (Q). W -Terminal LCC (E).8 W Differential Input Voltage ± V Output Short-Circuit Duration Indefinite Storage Temperature Range 8-Lead CERDIP (Q) and -Terminal LCC (E) C to + C 8-Lead PDIP (N) and 8-Lead SOIC (R) C to + C Operating Temperature Range J C to 7 C A C to + C S C to + C Lead Temperature (Soldering, sec) C Maximum internal power dissipation is specified so that TJ does not exceed C at an ambient temperature of C. If the differential voltage exceeds V, external series protection resistors should be added to limit the input current. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Table. Package Type θja Unit 8-Lead PDIP (N) (derates at 8.7 mw/ C) C/W 8-Lead CERDIP (Q) (derates at 8.7 mw/ C) C/W -Lead LCC (E) 77 C/W 8-Lead SOIC (R) (derates at mw/ C) C/W METALLIZATION PHOTO IN +IN OFFSET NULL SUBSTRATE CONNECTED TO +V S Figure. Metallization Photo; Contact Factory for Latest Dimensions, Dimensions Shown in Inches and (Millimeters) MAXIMUM POWER DISSIPATION (W)..... ESD CAUTION PDIP CERDIP.7 (.7) SOIC OFFSET NULL 8 +V S 7 LCC Figure. Maximum Power Dissipation vs. Temperature OUTPUT. (.7) V S 7 8 9 AMBIENT TEMPERATURE ( C) 88-88- Rev. I Page of
Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS. INPUT COMMON-MODE RANGE (V) +V OUT V OUT QUIESCENT CURRENT (ma)... SUPPLY VOLTAGE (±V) 88-. SUPPLY VOLTAGE (±V) 88-8 Figure. Input Common-Mode Range vs. Supply Voltage Figure 8. Quiescent Current vs. Supply Voltage MAGNITUDE OF THE OUTPUT VOLTAGE (V) +V OUT V OUT SUPPLY VOLTAGE (±V) R L = kω 88- INPUT BIAS CURRENT (µa) V S = ±V, ±V 8 TEMPERATURE ( C) 88-9 Figure. Output Voltage Swing vs. Supply Voltage Figure 9. Input Bias Current vs. Temperature OUTPUT VOLTAGE SWING (V p-p) k LOAD RESISTANCE (Ω) ±V SUPPLIES ±V SUPPLIES Figure 7. Output Voltage Swing vs. Resistive Load k 88-7 CLOSED-LOOP OUTPUT IMPEDANCE (Ω).. A V = = pf A V = = 8pF. k k k M M FREQUENCY (Hz) Figure. Closed-Loop Output Impedance vs. Frequency 88- M Rev. I Page of
Data Sheet 7 PHASE QUIESCENT CURRENT (ma) V S = ±V V S = ±V OPEN-LOOP GAIN (db) 8 GAIN ±V SUPPLIES Ω LOAD GAIN ±V SUPPLIES kω LOAD 8 PHASE (Degrees) 8 TEMPERATURE ( C) 88- = pf k k k M M FREQUENCY (Hz) M 88- Figure. Quiescent Current vs. Temperature Figure. Open-Loop Gain and Phase vs. Frequency SHORT-CIRCUIT CURRENT LIMIT (ma) POSITIVE CURRENT LIMIT NEGATIVE CURRENT LIMIT 8 AMBIENT TEMPERATURE ( C) V S = ±V Figure. Short-Circuit Current Limit vs. Ambient Temperature 88- OPEN-LOOP GAIN (db) 9 9 8 8 V S = ±V V S = ±V 7 k LOAD RESISTANCE (Ω) Figure. Open-Loop Gain vs. Resistive Load k 88- db BANDWIDTH (MHz) V S = ±V A V = + = pf PSRR (db) 8 SUPPLY +SUPPLY 8 TEMPERATURE ( C) Figure. db Bandwidth vs. Temperature 88- = pf k k k M M FREQUENCY (Hz) Figure. Power Supply Rejection Ratio (PSRR) vs. Frequency 88- M Rev. I Page 7 of
Data Sheet 7 7 8 V IN = V RMS A V = = pf C L = pf CMRR (db) 8 THD (db) 8 9 9 R L = Ω = pf k k k M M FREQUENCY (Hz) Figure 7. Common-Mode Rejection Ratio (CMRR) vs. Frequency 88-7 M R L = kω k k k k FREQUENCY (Hz) Figure. Total Harmonic Distortion (THD) vs. Frequency k 88- OUTPUT VOLTAGE (V p-p) V S = ±V R L = Ω A V = + = pf V S = ±V R L = kω A V = + = pf THD (db) V IN =.V RMS A V = R L = C L = pf = pf THIRD HARMONIC SECOND HARMONIC INPUT FREQUENCY (MHz) 88-8 7 k.m.m FREQUENCY (Hz).M 88- Figure 8. Large Signal Frequency Response Figure. Second and Third THD vs. Frequency 8 OUTPUT SWING FROM TO ±V % %.%.% ERROR A V = 9 = pf INPUT VOLTAGE NOISE (nv/ Hz) 8 8 SETTLING TIME (ns) 88-9 k k k M FREQUENCY (Hz) 88- M Figure 9. Output Swing and Error vs. Settling Time Figure. Input Voltage Noise Spectral Density Rev. I Page 8 of
Data Sheet A V = + SLEW RATE % TO 9% mv ns % 9 SLEW RATE (V/µs) V S = ±V RISE FALL RISE FALL V S = ±V 8 TEMPERATURE ( C) Figure. Slew Rate vs. Temperature 88- % Figure. Gain-of- Follower Small Signal Pulse Response (See Figure ) 88-8. V ns DIFFERENTIAL PHASE (Degrees)... DIFFERENTIAL GAIN.. DIFFERENTIAL PHASE DIFFERENTIAL GAIN (%) % 9 %. ± ± SUPPLY VOLTAGE (V) Figure. Differential Phase and Gain vs. Supply Voltage ± 88- Figure 7. Gain-of- Follower Large Signal Pulse Response (See Figure ) 88- mv ns mv ns % 9 9 % 88-7 % 88- Figure. Gain-to- Follower Large Signal Pulse Response (See Figure ) Figure 8. Gain-of- Follower Small Signal Pulse Response (See Figure ) Rev. I Page 9 of
Data Sheet mv ns mv ns % 9 % 9 % % 88-88- Figure 9. Unity-Gain Inverter Large Signal Pulse Response (See Figure ) Figure. Unity-Gain Inverter Small Signal Pulse Response (See Figure ) Rev. I Page of
Data Sheet TEST CIRCUITS (EXTERNAL) +V S 7 + kω 8 OFFSET NULL ADJUST Figure. Offset Null and External Shunt Compensation Connections V S 88- +V pf HP8A ns RISE TIME 7 + V pf kω TEKTRONIX TYPE 7A PREAMP kω Figure. Follower Connection, Gain = 88- +V HP8A ns RISE TIME Ω Ω Ω 7 + V pf kω FET PROBE TEKTRONIX TYPE 7A PREAMP = pf kω Figure. Follower Connection, Gain = 88-9 pf Ω HP8A ns RISE TIME Ω +V 7 + pf TEKTRONIX TYPE 7A PREAMP V Figure. Unity-Gain Inverter Connection 88- Rev. I Page of
Data Sheet THEORY OF OPERATION The is fabricated on the Analog Devices, Inc., proprietary complementary bipolar (CB) process, which provides PNP and NPN transistors with similar fts of MHz. As shown in Figure, the input stage consists of an NPN differential pair in which each transistor operates at a µa collector current. This gives the input devices a high transconductance, which in turn gives the a low noise figure of nv/ Hz at khz. +IN.mA IN OFFSET NULL C.pF R Ω Figure. Simplified Schematic OUTPUT The input stage drives a folded cascode that consists of a fast pair of PNP transistors. These PNPs drive a current mirror that provides a differential-input-to-single-ended-output conversion. The high speed PNPs are also used in the current-amplifying output stage, which provides a high current gain of,. Even under heavy loading conditions, the high fts of the NPN and PNPs, produced using the CB process, permit cascading two stages of emitter followers while maintaining phase margin at closed-loop bandwidths greater than MHz. Two stages of complementary emitter followers also effectively buffer the high impedance compensation node (at the CCOMP pin) from the output so that the can maintain a high dc openloop gain, even into low load impedances (9 db into a Ω load and db into a kω load). Laser trimming and PTAT biasing ensure low offset voltage and low offset voltage drift, enabling the user to eliminate ac coupling in many applications. For added flexibility, the provides access to the internal frequency compensation node. This allows users to customize the frequency response characteristics for a particular application. Unity-gain stability requires a compensation capacitance of 8 pf (Pin to ground), which yields a small signal bandwidth of MHz and slew rate of V/µs. The slew rate and gain bandwidth product varies inversely with compensation capacitance. Table and Figure 7 show the optimum compensation capacitance and the resulting slew rate for a desired noise gain. For gains between and, choose CCOMP to keep the small signal bandwidth relatively constant. The minimum gain that will still provide stability depends on the value of the external compensation capacitance. Ω Ω +V S V S 88- Rev. I Page of An RC network in the output stage (see Figure ) completely removes the effect of capacitive loading when the amplifier compensates for closed-loop gains of or higher. At low frequencies, and with low capacitive loads, the gain from the compensation node to the output is very close to unity. In this case, C is bootstrapped and does not contribute to the compensation capacitance of the device. As the capacitive load increases, a pole forms with the output impedance of the output stage, which reduces the gain, and subsequently, C is incompletely bootstrapped. Therefore, some fraction of C contributes to the compensation capacitance, and the unity-gain bandwidth falls. As the load capacitance is further increased, the bandwidth continues to fall, and the amplifier remains stable. EXTERNALLY COMPENSATING THE The is stable with no external compensation for noise gains greater than. For lower gains, two different methods of frequency compensating the amplifier can be used to achieve closed-loop stability: shunt and current feedback compensation. SHUNT COMPENSATION Figure and Figure 7 show that shunt compensation has an external compensation capacitor, CCOMP, connected between the compensation pin and ground. This external capacitor is tied in parallel with approximately pf of internal capacitance at the compensation node. In addition, a small capacitance, CLEAD, in parallel with resistor R, compensates for the capacitance at the inverting input of the amplifier. V IN + R +V S Figure. Inverting Amplifier Connection Using External Shunt Compensation V IN COAX R + Figure 7. Noninverting Amplifier Connection Using External Shunt Compensation Table gives the recommended CCOMP and CLEAD values, as well as the corresponding slew rates and bandwidth. The capacitor values were selected to provide a small signal frequency response with < db of peaking and <% overshoot. For Table, ± V 7 V S 7 V S +V S C LEAD R R kω kω C LEAD V OUT 88-7 88- V OUT
Data Sheet supply voltages should be used. Figure 8 is a graphical extension of Table, which shows the slew rate/gain trade-off for lower closed-loop gains, when using the shunt compensation scheme. (pf) Figure 8. Value of CCOMP and Slew Rate vs. Noise Gain CURRENT FEEDBACK COMPENSATION Bipolar, nondegenerated, single-pole, and internally compensated amplifiers have their bandwidths defined as f where: T = π r C e NOISE GAIN COMP I = kt π C q V S = ±V COMP ft is the unity-gain bandwidth of the amplifier. I is the collector current of the input transistor. SLEW RATE k SLEW RATE (V/µs) 88-8 CCOMP is the compensation capacitance. re is the inverse of the transconductance of the input transistors. kt/q approximately equals mv at 7 C. Because both ft and slew rate are functions of the same variables, the dynamic behavior of an amplifier is limited. Because then Slew Rate = I Slew Rate = π f T kt q This shows that the slew rate is only. V/µs for every megahertz of bandwidth. The only way to increase the slew rate is to increase the ft, and that is difficult because of process limitations. Unfortunately, an amplifier with a bandwidth of MHz can only slew at. V/µs, which is barely enough to provide a full power bandwidth of khz. The is especially suited to a form of current feedback compensation that allows for the enhancement of both the full power bandwidth and the slew rate of the amplifier. The voltage gain from the inverting input pin to the compensation pin is large; therefore, if a capacitance is inserted between these pins, the bandwidth of the amplifier becomes a function of its feedback resistor and the capacitance. The slew rate of the amplifier is now a function of its internal bias (I) and the compensation capacitance. Table. Component Selection for Shunt Compensation Follower Gain Inverter Gain R (Ω) R (Ω) CLEAD (pf) CCOMP (pf) Slew Rate (V/µs) db Small Signal Bandwidth (MHz) Open 8 k k 8 7. k 7 9 7 9. k 9 k.9 9 99 k 7. Rev. I Page of
Because the closed-loop bandwidth is a function of RF and CCOMP (see Figure 9), it is independent of the amplifier closedloop gain, as shown in Figure. To preserve stability, the time constant of RF and CCOMP needs to provide a bandwidth of < MHz. For example, with CCOMP = pf and RF = kω, the small signal bandwidth of the is MHz. Figure shows that the slew rate is in excess of V/µs. As shown in Figure, the closed-loop bandwidth is constant for gains of to ; this is a property of the current feedback amplifiers. Data Sheet Figure is an oscilloscope photo of the pulse response of a unitygain inverter that has been configured to provide a small signal bandwidth of MHz and a subsequent slew rate of 8 V/µs; RF = kω and CCOMP = pf. Figure shows the excellent pulse response as a unity-gain inverter, this using component values of RF = kω and CCOMP = pf. % V ns R F 9 V IN COAX R C* IN8 +V S 7 + R L kω V OUT % *RECOMMENDED VALUE OF FOR C <7pF pf 7pF pf V S SHOULD NEVER EXCEED pf FOR THIS CONNECTION Figure 9. Inverting Amplifier Connection Using Current Feedback Compensation 88-9 Figure. Large Signal Pulse Response of the Inverting Amplifier Using Current Feedback Compensation, CCOMP = pf, RF = kω, R = kω ns 88- V ns % 9 % 9 % % 88- mv Figure. Small Signal Pulse Response of Inverting Amplified Using Current Feedback Compensation, CCOMP = pf, RF = kω, R = kω 88- Figure. Large Signal Pulse Response of Inverting Amplifier Using Current Feedback Compensation, CCOMP = pf, C = pf RF = kω, R = kω CLOSED-LOOP GAIN (db) 9 GAIN = db @ 8.MHz GAIN = db @ 9.MHz GAIN = db @.MHz V IN = dbm V S = ±V 9 R L = kω R F = kω = pf C = pf k M M FREQUENCY (Hz) Figure. Closed-Loop Gain vs. Frequency for the Circuit of Figure 8 88- M Rev. I Page of
Data Sheet Figure and Figure show the closed-loop frequency response of the for different closed-loop gains and different supply voltages. CLOSED-LOOP GAIN (db) 9 GAIN = = pf GAIN = = pf GAIN = = pf 9 V S = ±V R L = kω R F = kω V IN = dbm FREQUENCY (MHz) Figure. Closed-Loop Frequency Response for the Inverting Amplifier Using Current Feedback Compensation OUTPUT LEVEL (db) 7 9 8 V IN = dbm R L = kω R F = kω GAIN = = pf 7 FREQUENCY (MHz) Figure. Closed-Loop Frequency Response vs. Supply for the Inverting Amplifier Using Current Feedback Compensation ±V ±V 88-88- V IN 7 + Figure. Noninverting Amplifier Connection Using Current Feedback Compensation V IN COAX 7Ω +V V +V 7 + pf V Figure 7. Video Line Driver with a Flatness over Frequency Adjustment LOW ERROR VIDEO LINE DRIVER The buffer circuit shown in Figure 7 drives a back-terminated 7 Ω video line to standard video levels ( V p-p), with. db gain flatness to MHz and with only. and.% differential phase and gain at the. MHz PAL color subcarrier frequency. This level of performance, which meets the requirements for high definition video displays and test equipment, is achieved using only ma quiescent current. pf kω kω 7Ω Ω Ω COAX COAX kω 7Ω OPTIONAL pf TO 7pF FLATNESS TRIM V OUT 88- V OUT 88-7 When a noninverting amplifier configuration using a current feedback compensation is needed, the circuit shown in Figure is recommended. This circuit provides a slew rate twice that of the shunt compensated noninverting amplifier of Figure 7 at the expense of gain flatness. Nonetheless, this circuit delivers 9 MHz bandwidth with db flatness into a back-terminated cable, with a differential gain error of only.% and a differential phase error of only. at. MHz. Rev. I Page of
Data Sheet HIGH GAIN VIDEO BANDWIDTH, -OP-AMP INSTRUMENTATION AMPLIFIER Figure 8 shows a -op-amp instrumentation amplifier circuit that provides a gain of at video bandwidths. At a circuit gain of, the small signal bandwidth equals 8 MHz into a FET probe. Small signal bandwidth equals. MHz with a Ω load. The.% settling time is ns. The input amplifiers operate at a gain of, while the output op amp runs at a gain of. In this circuit, the main bandwidth limitation is the gain/bandwidth product of the output amplifier. Extra care should be taken while breadboarding this circuit because even a couple of extra picofarads of stray capacitance at the compensation pins of A and A will degrade circuit bandwidth. +V IN pf (G = ) A kω pf TO 8pF SETTLING TIME AC CMR ADJUST kω R G Ω pf pf kω Ω Ω A AD88 (G = ) kω INPUT FREQUENCY CMRR A pf 97Ω DC CMR ADJUST +V Hz MHz MHz.dB.7dB.9dB +V S PIN 7 +V IN pf (G = ) Ω CIRCUIT GAIN = R G + COMM V µf µf µf µf V S PIN EACH AMPLIFIER 88-8 Figure 8. High Gain Video Bandwidth, -Op-Amp In-Amp Circuit Rev. I Page of
Data Sheet OUTLINE DIMENSIONS. (.98).8 (.89). (.7).8 (.97) 8. (.).8 (.8). (.98). (.) COPLANARITY. SEATING PLANE.7 (.) BSC.7 (.88). (.). (.). (.) 8. (.98).7 (.7). (.9). (.99).7 (.). (.7) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 9. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 7-A. (.). (9.7). (9.). (.) MAX. (.8). (.). (.9). (.).8 (.). (.) 8. (.) BSC.8 (7.). (.). (.). (.8) MIN SEATING PLANE. (.) MIN. (.) MAX. (.8) GAUGE PLANE. (8.). (7.87). (7.). (.9) MAX.9 (.9). (.). (.9). (.). (.).8 (.).7 (.78). (.). (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 7-A Rev. I Page 7 of
Data Sheet. (.) MIN. (.) MAX 8. (7.87). (.9). (.) BSC. (.8) MAX. (.9) MAX. (.). (.8). (8.).9 (7.7). (.8). (.8). (.8). (.).7 (.78). (.7). (.8) MIN SEATING PLANE. (.8).8 (.) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Lead Ceramic Dual In-Line [CERDIP] (Q-8) Dimensions shown in inches and (millimeters).8 (9.9). (8.9) SQ. (.). (.).8 (9.9) MAX SQ.88 (.). (.7).7 (.9) REF.9 (.).7 (.9). (.8).7 (.8) R TYP.7 (.9) REF. (.). (.) 9 8 BOTTOM VIEW 8 9. (.8) BSC. (.8) REF. (.) REF. (.8) MIN.8 (.7). (.). (.7) BSC TYP CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. -Terminal Ceramic Leadless Chip Carrier [LCC] (E--) Dimensions shown in inches and (millimeters) -A Rev. I Page 8 of
Data Sheet ORDERING GUIDE Model Temperature Range Package Description Package Option AR C to + C 8-Lead SOIC_N R-8 AR-REEL C to + C 8-Lead SOIC_N R-8 AR-REEL7 C to + C 8-Lead SOIC_N R-8 ARZ C to + C 8-Lead SOIC_N R-8 ARZ-REEL C to + C 8-Lead SOIC_N R-8 ARZ-REEL7 C to + C 8-Lead SOIC_N R-8 JN C to 7 C 8-Lead PDIP N-8 JNZ C to 7 C 8-Lead PDIP N-8 JR C to 7 C 8-Lead SOIC_N R-8 JR-REEL C to 7 C 8-Lead SOIC_N R-8 JR-REEL7 C to 7 C 8-Lead SOIC_N R-8 JRZ C to 7 C 8-Lead SOIC_N R-8 JRZ-REEL C to 7 C 8-Lead SOIC_N R-8 JRZ-REEL7 C to 7 C 8-Lead SOIC_N R-8 AQ C to + C 8-Lead CERDIP Q-8 SQ C to + C 8-Lead CERDIP Q-8 SQ/88B C to + C 8-Lead CERDIP Q-8 9-99MPA C to + C 8-Lead CERDIP Q-8 SE/88B C to + C -Lead LCC E-- 9-99MA C to + C -Lead LCC E-- JCHIPS Die SCHIPS Die AR-EBZ Evaluation Board Z = RoHS Compliant Part. Rev. I Page 9 of
Data Sheet NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D88--/(I) Rev. I Page of