CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS

CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS Chapter Outline 10.1 The Two-Stage CMOS Op Amp 10.2 The Folded-Cascode CMOS Op Amp 10.3 The 741 Op-Amp Circuit 10.4 DC Analysis of the 741 10.5 Small-Signal Analysis of the 741 10.6 Gain, Frequency Response, and Slew Rate of the 741 10.7 Modern Techniques for the Design of BJT Op Amp NTUEE Electronics L.H. Lu 10-1

10.1 The Two-Stage CMOS Op Amp Multi-stage amplifiers Practical transistor amplifiers usually consist of a number of stages connected in cascade Input stage: High input resistance to avoid signal loss due to high-resistance source Voltage gain Large CMRR for differential amplifiers Middle stages: Voltage gain Shifting of the dc level for required voltage swing Differential to single-ended conversion if necessary Output stage: Low output resistance to avoid loss of gain due to low-resistance load Current supply required by the load Sufficient voltage swing required by the load Small-signal approximation may not apply NTUEE Electronics L.H. Lu 10-2

Circuit Configuration Most widely used op amp in VLSI circuits Bias circuit: I REF and Q 8 Input stage: Q 1 -Q 5 Active-loaded MOS differential pair Differential input and single-ended output Provides voltage gain and high input resistance Output stage: Q 6 -Q 7 Active-loaded common-source amplifier Provides voltage gain High output resistance (not suitable for low-impedance loads) DC arrangement: The bias current of the input differential pair is provided by Q 5 The bias current of the second stage is provided by Q 7 To avoid systematic (predictable) offset: NTUEE Electronics L.H. Lu 10-3

Input common-mode range and output swing The transistors are supposed to be in saturation for proper circuit operation ICMR: Output swing: Voltage gain Low-frequency small-signal gain: Amplifier prototype: Input resistance: Output resistance: Transconductance: Common-mode rejection ratio: NTUEE Electronics L.H. Lu 10-4

Frequency response Poles and zeros f P2 decreases for a capacitive load May result in stability issue Unity-gain frequency for a dominant pole case and Phase margin NTUEE Electronics L.H. Lu 10-5

Phase margin improvement technique Adding a series resistance in the feedback path The zero is defined by Slew rate The zero can be moved toward higher frequencies for better phase margin Slew rate is defined as the maximum voltage change rate at output Associated with charging/discharging time of C C Extreme cases: Limited by bias current of Q 5 (typical case): SR = I/C C Limited by bias current of Q 7 : SR = I 7 /C C Relationship between SR and f t SR = 2 f t V OV = t V OV Slew rate is determined by the overdrive voltage for a given unity-gain frequency PMOS devices are preferred for the differential pair with a fixed current I at the cost of lower gain NTUEE Electronics L.H. Lu 10-6

Power-supply rejection ratio (PSRR) PSRR is defined as the ratio of the amplifier differential gain to the gain from the supply voltage Design trade-offs CMOS two-stage op amp performance is determined by The channel length of the MOSFETs The overdrive voltage of the MOSFETs Performance benefit for a larger channel length: gain, CMRR, PSRR Performance benefit for a smaller overdrive voltage: gain, CMRR, PSRR, ICMR, output swing and offset Performance benefit for a larger overdrive voltage: high-frequency characteristics (gain) For modern submicron CMOS technologies: Typical V OV between 0.1 to 0.3 V Channel length is at least 1.5 to 2 times minimum length (L min ) NTUEE Electronics L.H. Lu 10-7

10.2 The Folded-Cascode CMOS Op Amp Circuit Configuration Cascode topology to increase the gain of the input differential pair Folded topology to improve the ICMR and to reduce the required supply voltage Is generally considered a single-stage amplifier Also called operational transconductance amplifier (OTA) DC bias: Bias current for Q 1 -Q 2 is I/2 Bias current for Q 3 -Q 8 is I B I/2 I B can be realized by MOS current mirrors NTUEE Electronics L.H. Lu 10-8

Input common-mode range and output swing ICMR: Output swing: Voltage gain High voltage gain due to increased output resistance Not desirable for applications where low output resistance is needed for the op amp Frequency response Dominant pole at the output node Excellent high-frequency response Slew rate The slew rate is limited by the bias current I and the load C L Slew rate SR = I/C L = 2 f t V OV1 for I B > I Typically I B is set 10% ~ 20% larger than I NTUEE Electronics L.H. Lu 10-9

Increasing the ICMR: rail-to-rail input operation NMOS and PMOS differential pairs in parallel ICMR exceeds the power supply voltage Differential output voltage provided ICM in the middle: Both pairs operate simultaneously A v = 2G m R o ICM near supply voltage: Only one of the pairs is operational Gain drops to half Increasing the output voltage range: wide-swing current mirror Modified cascode current mirror Output swing increased by V t Output resistance remains the same A proper dc bias voltage V BIAS is needed NTUEE Electronics L.H. Lu 10-10

8.3 The 741 Op-Amp Circuit 741 Op-Amp Device parameters: npn: I S = 10-14 A, = 200, V A = 125 V pnp: I S = 10-14 A, = 50, V A = 50 V NTUEE Electronics L.H. Lu 10-11

Bias circuit: Reference current generated by Q 11, Q 12 and R 5 Bias for input stage: Widlar current source (Q 10, Q 11 and R 4 ) and current mirror Q 8, Q 9 Bias for second stage: current mirror Q 12, Q 13B (Q 13 is a two-output current source) Bias for output stage: current mirror Q 12, Q 13A /Q 18 -Q 19 provides 2V BE drop between V B14 and V B20 Input stage: (Q 1 -Q 7, R 1 -R 3 ) Input emitter follower (Q 1 -Q 2 ): high input resistance Current-mirror load (Q 5 -Q 7, R 1 -R 3 ):high output resistance and differential to single-ended conversion Level shifting (Q 3 and Q 4 ): for required voltage swing and dc level at the input of the second stage Second stage: (Q 16 -Q 17, Q 13B, R 8 -R 9 ) Emitter follower Q 16 for high input resistance Common-emitter Q 17 for voltage gain Miller compensation technique by C C Output stage: (Q 14, Q 20 ) Complementary pair Q 14 and Q 20 Low output resistance Relatively large load current without dissipating a large amount of power Emitter follower Q 23 to increase input resistance of the output stage Short-circuit protection circuitry Q 15, Q 21, Q 24, Q 22, R 6, R 7, R 11 NTUEE Electronics L.H. Lu 10-12

10.4 DC Analysis of the 741 Reference bias current Provided by Q 11, Q 12 and R 5 I REF = 0.73 ma (for V CC = V EE = 15 V) Input-stage bias Widlar current source Q 11, Q 10 and R 4 : I C10 = 19 A Current mirror Q 8 and Q 9 : I C1 = I C2 I C3 = I C4 = 9.5 A Q 1 -Q 4 and Q 8 -Q 9 form a negative feedback loop Bias current can be stabilized by the negative feedback NTUEE Electronics L.H. Lu 10-13

Current-source load Q 5 -Q 7 and R 1 -R 3 I C7 = 10.5 A Input bias current and offset currents Input bias current: I B = 47.5 na Input offset current: Non-zero input offset due to mismatches in the value Input common-mode range: Input common-mode voltage over which the input stage remains in the linear active mode The upper end limited by saturation of Q 1 and Q 2 The lower end limited by saturation of Q 3 and Q 4 NTUEE Electronics L.H. Lu 10-14

Second-stage bias I C17 I C13B = 550 A V EB17 = 618 mv and I C16 = 16.2 A Output-stage bias DC for Q 23 : I C23 180 A (I B23 3.6 A negligible for I C17 ) DC for Q 18 -Q 19 : I C18 165 A and I C19 V BE18 /R 10 + I B18 = 15.8 A DC for Q 14 and Q 20 : V BB = V BE18 + V BE19 = 588 mv + 530 mv = 1.118 V I C14 = I C20 = 154 A (for I S14 = I S20 = 3 10-14 A) NTUEE Electronics L.H. Lu 10-15

10.5 Small-Signal Analysis of the 741 The input stage Differential input resistance: r e = 2.63 k and R id = 2.1 M Transconductance: G m1 = 0.19 ma/v Output resistance: R o4 = r o4 [1 + g m4 (r e4 r 2 )] = 10.5 M R o6 = r o6 [1 + g m6 (R 2 r 6 )] = 18.2 M R o1 = R o4 R o6 = 6.7 M Equivalent circuit for the input stage: NTUEE Electronics L.H. Lu 10-16

The second stage Input resistance R i2 4 M Transconductance G m2 = 6.5 ma/v Output resistance R o2 = 81 k Equivalent circuit for the second stage: NTUEE Electronics L.H. Lu 10-17

The output stage Output voltage limits approximately 1 V below V CC and 1.5 V above V EE Input resistance (for R L = 2 k, I C20 = 5 ma and I C14 =0) R in3 3.7 M Open-circuit voltage gain Transconductance NTUEE Electronics L.H. Lu 10-18

Output resistance R out 34 Equivalent circuit for the output stage Output short-circuit protection One of the two output transistors could conduct a large amount of current if output is short-circuited Short-circuit protection is adopted in the 741 op amp For current source case (I C14 > 20 ma) V BE15 > 540 ma Q 15 turns on and takes away the base current of Q 14 I C14 is limited as the base current is reduced Similar case for current sink case (I C20 >20 ma) NTUEE Electronics L.H. Lu 10-19

10.6 Gain, Frequency Response and Slew Rate of the 741 Small-signal gain A v = 243147 V/V = 107.7 db Frequency response Slew rate f P = 4.1 Hz f t = 1 MHz SR = 0.63 V/ s Relationship between f t and slew rate Slew rate of MOS opamp with same f t is 2~3 times higher than the 741 G m -reduction method: total bias current is kept constant with reduced G m1 NTUEE Electronics L.H. Lu 10-20