Optimizing PCB Thermal Performance for Cree XLamp LEDs

Product design Guide Optimizing PCB Thermal Performance for Cree XLamp LEDs CLD-AP37 Rev 2H Table Contents Introduction...1 Thermal Management Principles...2 XLamp LED Thermal Characteristics...2 PCB Thermal Characteristics...3 Designing Thermal Vias...4 Open Vias vs. Filled Vias...5 Thermal Performance Simulations...7 Surface Thermal Dissipation...7 Thermal Dissipation with Vias...8 Combined Surface and Via Studies.10 Summary Results Thermal Simulations...12 Temperature Verification Measurements...13 Recommended Board Layouts...15 Gerber files...15 FR-4 Boards for XLamp XP and XT LED Packages...16 FR-4 Boards for XLamp XB LED Package...17 FR-4 Boards for XLamp MX LED Package...19 FR-4 Boards for XLamp ML LED Package...20 Chemical Compatibility...21 References...21 Introduction This Cree application note outlines a technique to assist with development cost-effective rmal management for XT, XP, XB, MX and ML families XLamp LEDs. One most critical design parameters for an LED illumination system is system s ability to draw heat away from LED junction. High operating temperatures at LED junction adversely affect performance LEDs, resulting in decreased light output and lifetime. 1 To properly manage this heat, specific practices should be followed in design, assembly and operation LEDs in lighting applications. This application note outlines a technique for designing a low-cost printed circuit board (PCB) layout that optimizes transfer heat from LED. The technique involves use FR-4-based PCBs, which cost less than metal core printed circuit boards (MCPCB), but have greater rmal resistance. The use metal-lined holes or vias underneath LED rmal pads is a method to dissipate heat through an FR-4 PCB and into an appropriate heat sink. metalized vias in FR-4 PCBs. For certain illumination systems design, rmal vias enable use FR-4 circuit boards instead metal core circuit boards. This can deliver system cost savings in circuit board and heat sink selection. This application note serves as a practical guideline based on heat transfer fundamentals and includes suggestive, but not definitive, simulation and measurement data. Cree advocates this technique as appropriate design for certain lighting applications and encourages Cree s customers to evaluate this option when considering many rmal management techniques available. For additional guidelines on LED rmal management, refer to Thermal Management application note. www.cree.com/xlamp Cree XLamp LEDs are designed with an electrically isolated rmal path. Cree pioneered this LED feature almost ten years ago to enable use 1 See Long-Term Lumen Maintenance application note. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty information, please contact Cree Sales at sales@cree.com. Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300

Thermal Management Principles Figure 1. Cree XLamp XP LED Package The technique in this application note is not recommended for Cree LEDs that consume more than 5 W power, including MC-E, MP-L and MT-G. For low power applications, this technique can be used for XM-L and XM-L EZW LEDs. XLamp LED Thermal Characteristics All XLamp LED packages have an electrically isolated rmal pad. The pad provides an effective channel for heat transfer and optimizes rmal resistance from LED chip junction to rmal pad. The pad is electrically isolated from anode and cathode LED and can be soldered or attached directly to grounded elements on board or heat sink system. Lens LED chip Anode Thermal pad Cathode Ceramic substrate AlNsubstrate Figure 1: Cree XLamp XP LED package Heat is conducted from LED package through rmal pad and into a PCB that should be mounted to a heat sink to transfer conducted heat into operating environment. 2 Tables 1 and 2 list typical rmal resistance values (junction to solder point) for various XLamp series LEDs. Table 1: Typical rmal resistance values for Cree XLamp white LEDs Color White (cool, neutral, warm) ML-B ML-C ML-E MX-3 MX-6 XB-D XM-L Thermal Resistance (ºC/W) XM-L EZW XM-L HVW XP-C XP-E XP-G XT-E 25 13 11 11 5 6.5 2.5 2.5 3.5 12 9 4 5 6.5 XT-E HVW Table 2: Typical rmal resistance values for Cree XLamp color LEDs n/a indicates an LED that Cree does not fer Color Thermal Resistance (ºC/W) ML-E XP-C XP-E Royal blue n/a 12 9 Blue 11 12 9 Green 15 20 15 Amber n/a 15 10 Red 15 10 10 Red-orange n/a 10 10 2 For subsequent discussion and simulation in this document, we assume PCB is mounted to an infinite heat sink that maintains back side board at 25 ºC. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 2

Figure 2: FR-4 cross-sectional geometry (not to scale) PCB Thermal Characteristics FR-4 FR-4 is one most commonly used PCB materials and is National Electrical Manufacturers Association (NEMA) designation for a flame retardant, fiberglass-reinforced epoxy laminate. A by-product this construction is that FR-4 has very low rmal conductivity. Figure 2 below shows a typical cross-sectional geometry for a two-layer FR-4 board. Heat source Thermal pad Top layer Cu Solder mask FR4 dielectric Bottom layer Cu ENIG Figure 2: FR-4 cross-sectional geometry (not to scale) Using rmal conductivity values in Table 3 below, total rmal resistance for an FR-4 board can be calculated by adding rmal resistances layers. For a given layer rmal resistance is given by formula: θ PCB = θ layer1 + θ layer2 + θ layer3... + θ layern (1) θ = l / (k x A) (2) where l is layer thickness, k is rmal conductivity, and A is area normal to heat source. For a 1.6-mm thick star board approximately 270 mm 2, calculated through-plane rmal resistance is approximately 30 ºC/W. Bear in mind that this calculation is one-dimensional and does not account for size heat source, spreading, convection rmal resistances or boundary conditions. If a smaller heat source size is considered, for example 3.3 mm x 3.3 mm, resulting onedimensional rmal resistance increases to over 700 ºC/W. Table 3: Typical rmal conductivities FR-4 board layers Layer/Material Thickness (µm) Thermal conductivity (W/mK) SnAgCu solder 75 58 Top layer copper 70 398 FR-4 dielectric 1588 0.2 Bottom layer copper 70 398 Electroless Nickel/Immersion Gold (ENIG) 5 4.2 Metal-Core Printed Circuit Board A simple one-layer MCPCB is comprised a solder mask, copper circuit layer, rmally conductive dielectric layer, and metal core base layer, as shown below in Figure 3. These three layers are laminated and bonded toger, providing a path for heat to dissipate. Often metal substrate is aluminum, though steel and copper can also be used. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 3

Heat source Thermal pad Top layer Cu Solder mask Dielectric layer Al substrate Figure 3: MCPCB cross-sectional geometry (not to scale) Using rmal conductivity values in Table 4 below, one-dimensional through-plane rmal resistance for a 1.6-mm-thick star board approximately 270 mm 2 is roughly 0.2 ºC/W. If a smaller heat source size is considered, resulting rmal resistance is 5.3 ºC/W. In this case, limiting factor is PCB dielectric. Table 4: Typical rmal conductivities MCPCB layers Layer/Material Thickness (µm) Thermal conductivity (W/mK) SnAgCu solder 75 58 Top layer copper 70 398 PCB dielectric 100 2.2 Al plate 1588 150 Designing Thermal Vias An inexpensive way to improve rmal transfer for FR-4 PCBs is to add rmal vias - plated through-holes (PTH) between conductive layers. Vias are created by drilling holes and copper plating m, in same way that a PTH or via is used for electrical interconnections between layers. Figure 4: FR-4 cross-sectional geometry with rmal vias (not to scale) Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 4

Application Note: Optimizing PCB Thermal Performance for Cree XLampLEDs Optimizing AN_100302-draft8e.docx PCB Thermal Performance 0.3 mm dia. via with 35 µm plating Solder mask Top layer Cu 0.6 mm dia. via with 35 µm plating FR4 dielectric Bottom layer Cu Figure 5. Cross-sectional geometry small and large rmal vias in FR-4 substrate Figure 5: Cross-sectional geometry small and large rmal vias in FR-4 substrate Adding vias in an appropriate way will improve rmal resistance an FR-4 board. The rmal Adding vias resistance in appropriate a single way will via improve can be calculated rmal resistance by same an formula, FR-4 board. l The / (k x rmal A). Using resistance values a single via can be calculated by Table same 4, a formula, single solid θ = l via / (k with x A). a Using diameter values 0.6 in mm Table results 5, a single (1.588 solder-filled x 10-3 ) via / (58 with x a ( diameter x (0.5 x 0.6 x mm results in (1.588 x 10-3 ) 10 / (58-3 ) 2 )) x ( = x 96.8 (0.5 x ºC/W. 0.6 x 10 However, -3 ) 2 )) = 96.8 when ºC/W. N However, vias are when used, N vias area are used, increases area by increases a factor by a Nfactor vias, resulting N vias, resulting in: in: θ vias = l / (N vias x k x A) (3) vias l / (N vias x k x A) (3) Note that this is applicable only if heat source is directly normal to rmal via; orwise, resistance increases due to rmal Keep in mind this is applicable only if heat source is directly normal to rmal via; orwise, spreading effects. resistance To calculate will increase total rmal due to resistance rmal spreading for region effects. underneath To calculate (or normal to) total LED rmal rmal resistance pad, equivalent rmal resistance for for region dielectric underneath layer (or and normal vias must to) be determined. LED rmal For simplicity, pad, equivalent two resistances rmal are resistance treated as for parallel applying dielectric layer and vias should be determined. For simplicity, two resistances are treated as this formula. parallel applying this formula: θ vias FR-4 = [ (1/θ vias ) + (1/θ FR-4 ) ] -1 (4) vias FR-4 = [ (1/ vias) + (1/ FR-4) ] -1 (4) Using values Using Table values 5, for a in 270 table mm4, 2 board for a with 270mm five 0.6-mm-diameter 2 board with five solder-filled 0.6mm diameter vias results solid in vias an approximate results in an rmal resistance 12 ºC/W, a approximate 60% improvement rmal over resistance initial 30 12ºC/W, derived a 250% from improvement data in Table over 3. initial 30ºC/W derived in from data in Table 2. Table 5: Typical rmal conductivities FR-4 board layers including rmal vias Layer/Material Thickness (µm) Thermal conductivity (W/mK) SnAgCu solder 75 58 Top-layer copper 70 398 FR-4 1588 0.2 Filled vias (SnAgCu) 1588 58 Bottom-layer copper 70 398 Solder mask (optional) 25 0.2 Table 4. Thermal conductivities FR-4 board layers including rmal vias Open Vias vs. Filled Vias Layer/Material Thickness (um) Thermal conductivity (W/mK) SnAgCu solder 75 58 Top layer copper 70 398 FR-4 1588 0.2 Filled vias (SnAgCu) 1588 58 Bottom layer copper 70 398 Solder mask (optional) 25 0.2 2.3 Open Vias vs. Filled Vias Open vias result in a higher rmal resistance than filled vias because area normal to heat source is reduced per formula: Open vias will result in A a = higher x (D x t rmal t 2 ) resistance compared to filled vias because area (5) normal to heat source is reduced per formula: where D is via diameter and t is plating thickness. A = x (D x t t 2 ) (5) where D is via diameter and t is plating thickness. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document For a is provided 0.6mm for informational diameter purposes via with only and 35is not m a (1 warranty oz.) or copper a specification. plating, For product specifications, area (normal please see to data sheets rmal available pad) at www.cree.com. is For warranty only 0.06mm 2 compared to 0.28mm 2 for a solid via, resulting in a rmal resistance 441 ºC/W per 5

Application Note: Optimizing PCB Thermal Performance for Cree XLampLEDs AN_100302-draft8e.docx Application Note: Optimizing PCB Thermal Performance for Cree XLampLEDs AN_100302-draft8e.docx Application Note: Optimizing PCB Thermal Performance for Cree XLampLEDs AN_100302-draft8e.docx Optimizing PCB Thermal Performance via compared to 96.8 ºC/W. For same sized board and number vias as in previous example, resulting via compared through-plane to 96.8 rmal ºC/W. For resistance same becomes sized board ~28 ºC/W. and number vias as in previous example, via compared resulting to through-plane 96.8 ºC/W. For rmal same resistance sized board becomes and ~28 number ºC/W. vias as in previous example, However, resulting ability through-plane to create solid rmal (copper) resistance filled vias becomes delivers ~28 additional ºC/W. reduced rmal resistance, For a 0.6-mm diameter via with 35 µm (1 oz.) copper plating, area normal to rmal pad is only 0.06 mm 2 compared to 0.28 mm as compared 2 However, to vias filled ability with to create SnAgCu solid solder. (copper) filled vias delivers additional reduced rmal resistance, for a solder-filled via, However, as resulting compared in ability a to rmal vias to filled create resistance with solid SnAgCu (copper) 64 ºC/W solder. filled per via vias compared delivers to additional 42 ºC/W if reduced filled with rmal solder or resistance, 14 ºC/W if filled completely In with general, copper. as compared increasing to vias plating filled thickness with SnAgCu during solder. PCB production will improve rmal resistance vias. Consult In with general, your PCB increasing manufacturer plating thickness to determine during if thicker PCB production plating is feasible. will improve rmal resistance vias. In In general, increasing Consult general, plating with increasing thickness your during PCB plating manufacturer thickness PCB production to during improves determine PCB production if rmal thicker resistance plating will improve is feasible. rmal resistance vias. vias. In example above, increasing Non-filled Consult vias with may your become PCB filled manufacturer with solder to during determine reflow. if thicker However, plating depending is feasible. on a number plating thickness to 70 µm (2 oz.) lowers rmal resistance to 34 ºC/W per via. Consult your PCB manufacturer to determine if factors, Non-filled this may not vias occur may become reliably. filled The vias, with solder if not reliably during filled, reflow. are However, not an effective depending heat on a number thicker plating management is feasible. Non-filled factors, tool. this vias may may not become occur filled reliably. with The solder vias, during if not reflow. reliably However, filled, are depending not an effective on a number heat factors, management this may tool. not occur reliably. The vias, if not reliably filled, are not an effective heat Non-filled vias Or may management than become creating filled tool. a with solid solder via during reflow. plating However, process depending PCB on production, a number factors, anor this option may is not to occur fill reliably and as a result, vias vias with Or will copper conduct than (or creating heat some less or a effectively. solid rmally via during conductive plating material process such in PCB as conductive production, epoxy) anor as option part is to fill PCB fabrication Or vias with than process. copper creating (or But a some solid this via or adds during an rmally additional plating conductive step process to fabrication material in PCB such production, and as may conductive increase anor epoxy) option cost as is part to fill An option to creating board. vias PCB with a solid fabrication copper (or via during process. some or plating But process this rmally adds in PCB an conductive production additional material is step to fill to fabrication such as conductive vias with and a rmally may epoxy) increase as conductive part material cost such PCB fabrication board. process. But this adds an additional step to fabrication and may increase cost as epoxy as Solder part voiding board. PCB fabrication in open PTH process. vias. This adds an additional step to fabrication and may increase cost board. Solder voiding in open Solder PTH voiding vias in open PTH vias. Figure Solder 6a shows voiding an example in open PTH unfilled vias. vias after reflow, and Figure 6b shows an example solder Figure 6 shows voids an underneath example Figure 6a unfilled shows device vias an example after (shown reflow. in red). unfilled Figure The 7 vias shows voids after an will example reflow, increase and solder Figure rmal voids 6b underneath shows resistance example device (shown solder in red). rmal Figure The voids increase voids interface. 6a rmal underneath shows Also, an resistance example solder device may rmal (shown unfilled overfill interface. vias red). hole after Also, The leading reflow, voids solder will and to bumps may increase Figure on 6b overfill shows hole rmal bottom an leading resistance example board to bumps solder on bottom which voids can rmal reduce underneath interface. contact Also, area device between (shown solder may in board red). overfill The and voids heat hole sink. will leading increase Steps to can bumps be rmal taken on to resistance bottom limit board board amount that can rmal reduce contact area between board and heat sink. which solder can interface. wicking. reduce Also, contact One way solder area is to between may maintain overfill a board via diameter hole and leading heat smaller sink. to bumps than Steps 0.3 on can mm. be bottom With taken smaller to limit board vias, which amount surface can reduce tension solder contact wicking. liquid area One between solder way is inside to maintain board via and a is via more heat diameter sink. capable Steps smaller countering can than be 0.3 taken mm. to force With limit smaller Steps can be gravity taken amount vias, on to limit solder. surface amount If wicking. tension via solder structure One wicking. way liquid is is constructed to One solder maintain way inside is to following a maintain via diameter via is a more via guidelines smaller diameter capable than mentioned smaller 0.3 countering mm. than above, 0.3 With mm. smaller force With smaller vias, surface holding tension vias, gravity inside via on surface diameter liquid solder. tension to If around inside via liquid 0.25 structure via is mm solder better is 0.3 inside constructed able mm, to counter minimal via following is more solder force capable wicking guidelines gravity is on countering achieved. mentioned solder. The If above, force via structure drawback gravity is constructed following holding to this on inside approach solder. guideline via above, diameter is If that via smaller holding to structure around open inside 0.25 is vias constructed via mm will diameter result 0.3 mm, following a to around minimal higher overall 0.25 solder guidelines mm wicking rmal mentioned 0.3 mm, is resistance. minimal achieved. above, solder The wicking is holding drawback inside to this via diameter approach to is around that smaller 0.25 mm open vias 0.3 mm, will result minimal in a solder higher wicking overall is rmal achieved. resistance. The achieved. The drawback to this to approach this approach is that is smaller that smaller open vias open result vias in a will higher result overall in a rmal higher overall resistance. rmal resistance. Figure 6a. Unfilled vias Figure 6b. Solder voiding (not to scale) Figure Figure 6: 6a. Unfilled Unfilled vias vias Figure 6b. Solder Figure voiding 7: Solder (not voiding to scale) (not to scale) Figure 6a. Unfilled vias Figure 6b. Solder voiding (not to scale) Anor technique Anor for technique limiting solder for limiting wicking solder involves wicking using solder involves mask using to restrict solder mask flow to solder restrict from flow top side solder PCB to from Anor top side technique PCB for to limiting bottom solder side. wicking One involves process, using called solder tenting, mask uses to restrict solder mask flow to bottom side. One process, called tenting, uses solder mask to prevent solder from eir entering or exiting rmal vias, solder depending prevent Anor from solder technique from top side eir for entering limiting PCB or solder to exiting wicking bottom rmal side. involves One vias, using process, depending solder called mask on tenting, to side restrict uses solder board flow to mask solder to on side which board from prevent solder on which top solder mask side from is solder placed. mask eir PCB Tenting entering to is placed. bottom Tenting or exiting bottom side. side One bottom rmal with process, side solder with vias, called mask solder depending tenting, to mask cover to on and cover uses side plug and solder plug mask rmal board to vias to can prevent rmal solder prevent from which vias flowing can solder prevent solder down from mask into solder eir is vias from entering placed. and flowing onto Tenting or exiting down bottom into bottom rmal via side board. and vias, with onto In depending top-side solder bottom mask via on tenting, to cover side small board. and areas plug In board solder to mask which solder can mask prevent is placed. solder Tenting from flowing bottom down into side with via solder and onto mask to bottom cover and plug board. are placed over top-side rmal via tenting, vias on small top areas side solder PCB mask to prevent are placed solder from over flowing rmal into vias vias on from top top side side board. In PCB to rmal top-side prevent vias via solder can tenting, from prevent small flowing solder areas into from solder flowing vias from mask down are into top placed side via over and board. onto rmal bottom vias on top board. side In top-side PCB to via prevent tenting, solder small from areas flowing solder into mask vias are from placed top over side rmal board. vias on top side PCB to prevent solder from flowing into vias from top side board. Figure 8: Tented vias with bottom-side solder mask (not to scale) Figure 7: Tented vias with bottom-side solder mask (not to scale) Figure 7: Tented vias with bottom-side solder mask (not to scale) In general Cree advocates creating Figure copper-filled 7: Tented vias vias with as bottom-side being a more solder practical mask (not and to scale) effective technique, In general preferable Cree to advocates solder-filled creating vias. copper-filled vias as being a more practical and effective In technique, general Cree preferable advocates to solder-filled creating copper-filled vias. vias as being a more practical and effective technique, preferable to solder-filled vias. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 2010-02-16 Cree Company Confidential Page 6 17 6 2010-02-16 2010-02-16 Cree Company Confidential Cree Company Confidential Page 6 17 Page 6 17

Application Note: Optimizing PCB Thermal Performance for Cree XLampLEDs AN_100302-draft8e.docx Optimizing PCB Thermal Performance 3 Thermal Performance Simulations Thermal Performance The following section Simulations presents results obtained from computational rmal analysis for a series PCB configurations 4. This section presents results obtained from computational rmal analysis for a series PCB configurations. 3 3.1 Surface Thermal Dissipation Surface Thermal Dissipation The first configuration, The first shown configuration, in Figure as 9, shown consists in Figure a star 8, FR-4 consists PCB with a varying star FR-4 widths PCB with varying rmal widths pad and for two board thicknesses (0.8 mm and 1.6 rmal mm); pad bottom and two copper board layer thicknesses is solid and (0.8mm re and are no 1.6mm); rmal vias. bottom copper layer is solid and re are no rmal vias. Chart 1 Figure 8: Variation in rmal pad width on top side PCB Figure 9: Variation in rmal pad width on top side PCB The results shown in Chart 1 show for 1.6mm-thick board increasing width beyond 12mm The analysis results provides in Chart little improvement, 1 show that, for while for 1.6-mm 0.8mm-thick board, board, increasing improvement rmal pad tapers width f beyond 12 a mm provides little improvement and, width for 16mm. 0.8-mm thick board, improvement diminishes beyond a 16-mm width. Thermal Resistance, Solder point through Board ( C/W) 70 60 50 40 30 20 10 70.00 FR4 No Vias: Top Trace Size- Solder point through board FR4 No Vias: Top Trace Size- Solder point through board Thermal Resistance, Solder point through Board ( C/W) 60.00 50.00 40.00 30.00 20.00 10.00 1.6mm thick FR4 No Vias 0.8mm thick FR4 No 1.6mm Vias thick FR4 No Vias 0.8mm thick FR4 No Vias 0.00 0 5 10 15 20 25 Length/Width top trace (mm) Chart 1: Thermal resistance for FR-4 PCB with no vias with varying rmal pad size 0 0 5 10 15 20 25 The next configuration is same except board is a MCPCB. Data in chart 2 shows for eir Length/Width top trace (mm) board thickness re is little benefit to extending rmal pad width beyond 6mm. Chart 1: Thermal resistance for FR-4 PCB with no vias with varying rmal pad size The next configuration is same as first except board is an MCPCB. Chart 2 shows re is little benefit to extending rmal pad width beyond 6 mm for eir board thickness. 4 Cree used Ansys Design Space, http://www.ansys.com/products/structural-mechanics/products.asp 3 Cree used Ansys Design Space, www.ansys.com/products/structural-mechanics/products.asp 2010-02-16 Cree Company Confidential Page 7 17 Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 7

Chart 2 Optimizing PCB Thermal Performance 5.0 MCPCB: Top Trace Size- Solder point through board Thermal Resistance, solder point through Board ( C/W) 1.6mm thick MCPCB 4.5 0.8mm thick MCPCB 4.0 3.5 3.0 2.5 2.0 1.5 1.0 Figure 9: FR-4 board with 5 and 15 0.7mm diameter vias and 1mm pitch 0.5 0.0 0 5 10 15 20 25 Length/Width top trace (mm) Chart 2: Thermal resistance for MCPCB with varying rmal pad size Thermal Dissipation with Vias Chart 3 shows effects various filling materials for 0.7-mm diameter vias with 1-mm center-to-center spacing for both 1.6-mm and 0.8-mm board thicknesses, shown in Figure 10. The analysis data indicate solid copper filled vias result in lower rmal resistance and unfilled vias deliver higher rmal resistance. A via filled with conductive epoxy performs only slightly better than an unfilled via. Figure 10: FR-4 board with five and fifteen 0.7-mm-diameter vias and 1-mm pitch Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 8

Chart 3: Thermal resistance for FR-4 vias filled with materials differing conductivity Optimizing PCB Thermal Performance Thermal Resistance, Solder point through Board ( C/W) 14.00 12.00 10.00 8.00 6.00 4.00 2.00 Unfilled Conductive Epoxy Solder 1.6mm thick FR4 PCB, 5 vias 0.8mm thick FR4 PCB, 5 vias 1.6mm thick FR4 PCB, 15 vias 0.8mm thick FR4 PCB, 15 vias Copper 0.00-25 0 25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 Via Thermal Conductivity (W/mK) Chart 3: Thermal resistance for FR-4 vias filled with materials differing conductivity Chart 4 shows effect changing diameter and number vias. This chart assumes vias are filled with SnAgCu solder. As expected, larger diameter via, lower rmal resistance becomes. Increasing number vias shows considerable improvement for smaller via diameters. Chart 4 Thermal Resistance, solder point through board ( C/W) 30 25 20 15 10 5 Via Size 91 Vias, 1.6mm PCB 91 Vias, 0.8mm PCB 47 Vias, 1.6mm PCB 47 Vias, 0.8mm PCB 15 Vias, 1.6mm PCB 15 Vias, 0.8mm PCB 5 Vias, 1.6mm PCB 5 Vias, 0.8mm PCB 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Via Diameter (mm) Chart 4: FR-4 PCB with various via diameters and numbers vias Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 9

Figure 10: FR-4 board with varying numbers rmal vias (2, 6, 8, 14, 58, and 102) The next case considers effect varying number rmal vias as shown in Figure 11. These vias are solid-plated copper with a diameter 0.254 mm (0.010 in.) and center-to-center spacing 0.635 mm (0.025 in.). The results in Chart 5 indicate that increasing number vias beyond fourteen shows little improvement. (This is maximum achievable density area normal to LED rmal pad.) Chart 5 Figure 11: FR-4 board with varying numbers rmal vias (2, 6, 8, 14, 58, and 102) 20 Filled Via Count: Ø10mil, 25.4mil pitch Thermal Resistance, Solder point through Board ( C/W) 18 16 14 12 10 8 6 4 2 1.6mm thick FR4 PCB 0.8mm thick FR4 PCB 1.6mm MCPCB 0.8mm MCPCB 0 0 20 40 60 80 100 120 # Filled Copper Vias Chart 5: Thermal resistance values FR-4 board for varying numbers copper-filled rmal vias Combined Surface and Via Studies The next configuration is an FR-4 PCB with fourteen 0.254-mm diameter copper plated vias with rmal pad widths shown in Figure 12. The bottom copper layer is solid. The data in Chart 6 show that, beyond a 6-mm width, re is little improvement in rmal resistance. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 10

Figure 11: FR-4 PCB with 14 rmal vias and varying top rmal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm) Optimizing PCB Thermal Performance Chart 6 Figure 12: FR-4 PCB with 14 rmal vias and varying top rmal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm) 9 FR4 14 vias: Top Trace Size- Solder point through board Thermal Resistance, Solder point through Board ( C/W) 8 7 6 5 4 3 2 1 1.6mm thick FR4 PCB 0.8mm thick FR4 PCB 0 0 5 10 15 20 25 Trace Width (mm) Chart 6: Thermal resistance FR-4 PCB with 14 vias and varying rmal pad widths Finally, previous scenario is repeated with bottom rmal pad widths shown in Figure 13. The results, shown in Chart 7, indicate that re is a small difference in rmal resistance that decreases as width bottom pad increases. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 11

Figure 12: FR-4 PCB with 14 rmal vias and varying bottom rmal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm) Optimizing PCB Thermal Performance Chart 7 Figure 13: FR-4 PCB with 14 rmal vias and varying bottom rmal pad widths (3.3, 4.0, 6.0, 10.0, 14.0, 20.0 mm) Thermal Resistance, Solder point through Board ( C/W) 10 9 8 7 6 5 4 3 2 1 FR4 14 vias: Top + Bottom Trace Size- Solder point through board Full Backside & Changing Frontside_ 1.6mm PCB Full Backside & Changing Frontside_ 0.8mm PCB Changing Back & Frontside, 1.6mm PCB Changing Back & Frontside, 10.8mm PCB 0 0 5 10 15 20 25 Top + Bottom Trace Width (mm) Chart 7: Thermal resistance FR-4 PCB with 14 vias and varying top and bottom rmal pad widths Summary Results Thermal Simulations 1. The results from various simulations show that dielectric thickness should be 0.8 mm to achieve lowest possible rmal resistance for an FR-4 board. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 12

2. Although making vias as large as possible reduces rmal resistance, cost manufacturing board must also be considered. Larger unfilled vias introduce possibility vias becoming partially filled during soldering process. Smaller, closely spaced vias are a better solution. 3. Finally, adding additional vias and increasing width rmal pad beyond a certain point have diminishing returns because rmal spreading resistance. Based on se conclusions, on page 15 Cree recommends an optimal rmal pad size, via size and spacing that is both rmally effective and manufacturable. Temperature Verification Measurements Because LED junction temperature affects LED lifetime, Cree recommends performing a rmal verification test on LED-board assembly under real-life conditions. 4 This section illustrates practical LED board rmal measurement using rmocouples, which fers some corroboration for simulations on which we base our recommendations. Figure 13: Thermocouple placement Figure 14 shows a type-k rmocouple attached to top copper layer close to rmal pad. The solder mask (if present) should be removed to solder rmocouple to board. Alternately rmocouple can be attached using a rmal epoxy or aluminum tape. If more than one LED is on board, lamp with highest expected temperature should be selected. Anor rmocouple is attached to back heat sink using rmal epoxy. A third rmocouple is used to measure ambient (air) temperature. 5 The rmocouple wires are held in place with Kapton tape. To calculate actual heat sink to ambient rmal resistance, divide difference between Ths and Ta by power heat source. T hs1 T c T hs2 Figure 14: Thermocouple placement Table 6 below contains data from five sets five XLamp XP-E LEDs mounted on star boards. The first four sets are 1.6-mm thick FR-4 boards with via layouts similar to Figure 12 and Figure 13 with 10-mm wide bottom rmal pads; last set is 1.6-mm thick aluminum clad boards. The PCBs were mounted to a heat sink with rmal adhesive. 6 Measurements forward voltage (V f ) and 4 Normally junction temperature cannot be measured directly and must be derived from temperature measured at a reference point on top copper layer. 5 At least 2 mm away from heat sink and/or illumination source and not in path illuminance. 6 Aavid Thermalloy part number 374424B00035G, with Chomerics THERMATTACH T411 rmal tape for FR-4; CTS Electronics part number BDN10-5CB/A01for MCPCB Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 13

case temperature (T c ) were taken at 700 ma (I f ) at an ambient temperature 20 ºC (T a ). With se measurements, power (P), PCB rmal resistance (θ pcb ), case to ambient rmal resistance (θ ca ), and heat sink to ambient rmal resistance (θ hs-a ) can all be calculated per following equations. P = I f * V f (6) θ pcb = (T c - T hs ) / P (7) θ ca = (T c T a ) / P (8) θ pcb = (T hs T a ) / P (9) Table 6: PCB temperature measurements Board If (A) Vf (V) Power (W) Tc ( C) Ths ( C) Ta ( C) θpcb ( C/W) θca ( C/W) θhs-a ( C/W) 1 oz. #1 0.700 3.31 2.32 69.64 45.73 22.0 10.32 20.57 10.25 1 oz. #2 0.700 3.26 2.28 70.29 48.03 22.0 9.75 21.16 11.40 1 oz. #3 0.700 3.21 2.24 65.37 44.02 22.0 9.51 19.33 9.81 1 oz. #4 0.700 3.22 2.25 66.34 47.65 22.0 8.30 19.69 11.39 1 oz. #5 0.700 3.25 2.28 65.77 45.15 22.0 9.06 19.23 10.17 2 oz. #1 0.700 3.32 2.32 71.69 48.19 22.0 10.12 21.41 11.28 2 oz. #2 0.700 3.34 2.34 68.60 45.34 22.0 9.96 19.95 9.99 2 oz. #3 0.700 3.26 2.28 66.95 46.33 22.0 9.04 19.71 10.67 2 oz. #4 0.700 3.34 2.34 66.36 44.37 22.0 9.39 18.95 9.56 2 oz. #5 0.700 3.35 2.35 67.57 45.19 22.0 9.54 19.43 9.89 2 oz. filled #1 0.700 3.36 2.35 67.19 44.39 22.0 9.69 19.20 9.51 2 oz. filled #2 0.700 3.33 2.33 67.48 45.11 22.0 9.59 19.51 9.92 2 oz. filled #3 0.700 3.28 2.30 68.06 44.92 22.0 10.08 20.07 9.99 2 oz. filled #4 0.700 3.29 2.30 66.70 44.86 22.0 9.50 19.44 9.94 2 oz. filled #5 0.700 3.37 2.36 70.03 47.87 22.0 9.39 20.35 10.96 4 oz. #1 0.700 3.31 2.32 64.35 45.80 22.0 7.99 18.25 10.26 4 oz. #2 0.700 3.34 2.33 68.31 48.75 22.0 8.38 19.83 11.46 4 oz. #3 0.700 3.39 2.38 71.87 50.41 22.0 9.03 20.99 11.96 4 oz. #4 0.700 3.26 2.28 66.63 47.87 22.0 8.22 19.54 11.32 4 oz. #5 0.700 3.33 2.33 68.12 48.55 22.0 8.40 19.80 11.40 MCPCB #1 0.700 3.36 2.35 63.20 53.20 20.0 4.25 18.37 14.12 MCPCB #2 0.700 3.04 2.13 57.60 50.90 20.0 3.15 17.67 14.52 MCPCB #3 0.700 3.36 2.35 57.90 50.10 20.0 3.32 16.11 12.80 MCPCB #4 0.700 3.35 2.35 62.00 51.20 20.0 4.61 17.91 13.30 MCPCB #5 0.700 3.37 2.36 60.10 51.30 20.0 3.73 17.00 13.27 Avg. θpcb ( C/W) Avg. θca ( C/W) Avg. θhs-a ( C/W) 9.39 19.99 10.60 9.61 19.89 10.28 9.65 19.71 10.06 8.40 19.68 11.28 3.81 17.41 13.60 Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 14

The results are close to predicted performance in Chart 2 (which indicates a rmal resistance asymptote about 3.5 ºC/W for an MCPCB) and Chart 7 (which shows a fourteen-via 1.6-mm FR-4 board with a rmal resistance about 8 ºC/W for a 0.254-mm diameter, 2-oz. plated via). 7 Recommended Board Layouts Cree recommends creating areas 10-mil (0.254-mm) vias arranged on a 25-mil (0.635-mm) rectilinear grid. The reason for this choice is combination cost, performance and manufacturability. According to several PCB manufacturers, 10-mil holes and 25-mil spacing are reasonable and repeatable production choices when used with a 2-oz. plating solution. When using multiple LEDs, tighter spacing between emitters results in increased heating. The rmal pads can be connected toger and additional copper can be added, if possible. The following sections illustrate minimum recommended pad sizes for XT, XP, XB, MX and ML packages. Gerber files For ML, MX, XB, XP and XT families LEDs, Cree revised Gerber files for a star-shaped, single LED circuit board to include via drilling specifications. The Gerber files are.zip archives posted on Cree s website in Design Files area product pages for each XT, XP, XB, MX and ML products. 8 7 In general, rmal measurement LEDs is challenging and re are chances for error due to number variables involved. Thermocouple placement and subsequent calculations are but two concerns. We use se results for ir suggestive value rar than ir definitive result. 8 At Products page, select LED interest n select Documentation tab. Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 15

Application Note: CLD-AP37 AN_100302^rev1 draft5-20110404 (2).docx rev 1.4 Application Note: CLD-AP37 AN_100302^rev1 draft5-20110404 (2).docx rev 1.4 5.1 FR-4 boards for XLamp XP package FR-4 Boards 5.1 for XLamp FR-4 boards XP and XT for LED XLamp Packages XP package Dashed line represents optional 10-mm Dashed rmal line represents pad optional 10-mm rmal pad Figure 14: Recommended footprint for XLamp XP family LEDs on FR-4 PCB (top and bottom) Figure 14: Recommended footprint for XLamp XP family LEDs on FR-4 PCB (top and bottom) Figure 15: Recommended footprint for XLamp XP and XT family LEDs on FR-4 PCB (top and bottom) 2011-04-07 Cree Company Confidential Page 15 18 2011-04-07 Cree Company Confidential Page 15 18 Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 16

FR-4 Boards for XLamp XB LED Package XB-D FR4: Minimum Vias (5) Copyright 2011, Cree, Inc. Cree Proprietary & Confidential pg. 1 XB Back side: Minimum Vias (5) Copyright 2011, Cree, Inc. Cree Proprietary & Confidential pg. 2 Figure 16: Minimum footprint for XLamp XB family LEDs on FR-4 PCB (top and bottom) Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 17

XB-D FR4: Optional Vias (11) Copyright 2011, Cree, Inc. Cree Proprietary & Confidential pg. 3 XB Back side: Optional Vias (11) Copyright 2011, Cree, Inc. Cree Proprietary & Confidential pg. 4 Figure 17: Recommended footprint for XLamp XB family LEDs on FR-4 PCB (top and bottom) Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 18

Application Application Note: Note: CLD-AP37 CLD-AP37 AN_100302^rev1 draft5-20110404 (2).docx (2).docx rev 1.4 rev 1.4 FR-4 Boards 5.2 5.2 for FR-4 XLamp FR-4 boards boards MX for LED XLamp for Package XLamp MX MX package package Figure Figure 15: 15: Figure Recommended 18: Recommended footprint footprint footprint for XLamp for for XLamp MX package MX MX package on FR-4 on FR-4 PCB PCB PCB (top (top and and bottom) bottom) 2011-04-07 2011-04-07 Cree Cree Company Company Confidential Confidential Page Page 16 16 18 18 Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 19

Application Note: CLD-AP37 AN_100302^rev1 draft5-20110404 (2).docx rev 1.4 FR-4 5.3 Boards FR-4 for boards XLamp ML for LED XLamp Package ML package Figure 16: Recommended Figure 19: Recommended footprint for footprint XLamp for XLamp ML package ML package on on FR-4 PCB (top and and bottom) bottom) 6 Chemical compatibility It is important to verify chemical compatibility when selecting interface materials to use between board and heat sink, as well as or materials to which LEDs can be exposed. Certain materials from FR-4 board fabrication and assembly processes, e.g., adhesives, solder mask and flux residue, can outgas and react adversely with materials in LED package, especially at high temperatures when a non-vented secondary optic is used. This interaction can cause performance degradation and product Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 2011-04-07 Cree Company Confidential Page 17 18 20

Chemical Compatibility It is important to verify chemical compatibility when selecting interface materials to use between board and heat sink, as well as or materials to which LEDs can be exposed. Certain materials from FR-4 board fabrication and assembly processes, e.g., adhesives, solder mask and flux residue, can outgas and react adversely with materials in LED package, especially at high temperatures when a non-vented secondary optic is used. This interaction can cause performance degradation and product failure. Each family or individual LED product has an application note identifying substances known to be harmful to Cree LEDs. 10 Consult your PCB manufacturer to determine which materials it uses. References Electronics Cooling, September 1997, Vol.3, No.3, Calculation Corner: One-dimensional heat flow Bruce M. Guenin, Ph.D., Associate Editor Electronics Cooling, May 1998, Vol.4, No.2, Calculation Corner: Conduction heat transfer in a printed circuit board Bruce M. Guenin, Ph.D., Associate Editor Electronics Cooling, August 2004, Volume 10, Number 3, Calculation Corner: Thermal Vias A Packaging Engineer s Best Friend, Bruce M. Guenin, Ph.D., Associate Editor Thermal and High Current Multilayer Printed Circuit Boards With Thermagon T-lam and Hybrid Boards January 31, 2001, Thermagon, Inc., Courtney R. Furnival Thermal Considerations for QFN Packaged Integrated Circuits AN315 rev 1, July 2007, Cirrus Logic, Inc. 10 XT Family LEDs Soldering & Handling XP Family LEDs Soldering & Handling XB Family LEDs Soldering & Handling MX Family LEDs Soldering & Handling ML Family LEDs Soldering & Handling Copyright 2010-2016 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree and XLamp are registered trademarks and Cree logo is a trademark Cree, Inc. This document is provided for informational purposes only and is not a warranty or a specification. For product specifications, please see data sheets available at www.cree.com. For warranty 21