Single-Supply, Rail-to-Rail, Low Power, FET Input Op Amp AD82 FEATURES True single-supply operation Output swings rail-to-rail Input voltage range extends below ground Single-supply capability from 5 V to 3 V Dual-supply capability from ±2.5 V to ±5 V Excellent load drive Capacitive load drive up to 35 pf Minimum output current of 5 ma Excellent ac performance for low power 8 μa maximum quiescent current Unity-gain bandwidth:.8 MHz Slew rate of 3 V/μs Excellent dc performance 8 μv maximum input offset voltage 2 μv/ C typical offset voltage drift 25 pa maximum input bias current Low noise: 3 nv/ Hz @ khz APPLICATIONS Battery-powered precision instrumentation Photodiode preamps Active filters 2-bit to -bit data acquisition systems Medical instrumentation Low power references and regulators GENERAL DESCRIPTION The AD82 is a precision, low power FET input op amp that can operate from a single supply of 5 V to 36 V, or dual supplies of ±2.5 V to ±8 V. It has true single-supply capability, with an input voltage range extending below the negative rail, allowing the AD82 to accommodate input signals below ground in the single-supply mode. Output voltage swing extends to within mv of each rail, providing the maximum output dynamic range. Offset voltage of 8 μv maximum, offset voltage drift of 2 μv/ C, typical input bias currents below 25 pa, and low input voltage noise provide dc precision with source impedances up to GΩ..8 MHz unity gain bandwidth, 93 db THD at khz, and 3 V/μs slew rate are provided for a low supply current of 8 μa. The AD82 drives up to 35 pf of direct capacitive load and provides a minimum output current of 5 ma. This allows the amplifier to handle a wide range of load conditions. This combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single-supply user. PIN CONFIGURATIONS NULL IN 2 IN 3 V S NC IN 2 IN 3 V S AD82 TOP VIEW (Not to Scale) NC = NO CONNECT Figure. 8-Lead PDIP AD82 TOP VIEW (Not to Scale) NC = NO CONNECT 8 7 6 5 8 7 6 5 NC V S V OUT NULL NC V S V OUT NC Figure 2. 8-Lead SOIC_N and 8-Lead MSOP The AD82 is available in two performance grades. The A and B grades are rated over the industrial temperature range of C to 85 C. The AD82 is offered in three 8-lead package options: plastic DIP (PDIP), surface mount (SOIC) and (MSOP). 9 % V V V 873-2 873-2µs Figure 3. Gain-of-2 Amplifier; V S = 5 V, V, V IN = 2.5 V Sine Centered at.25 V 873- Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. Tel: 78.329.7 www.analog.com Fax: 78.6.33 9962 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS Features... Applications... Pin Configurations... General Description... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 9 Thermal Resistance... 9 ESD Caution... 9 Typical Performance Characteristics... Applications Information... 6 Input Characteristics... 6 Output Characteristics... 7 Single-Supply Half-Wave and Full-Wave Rectifiers... 7.5 V Low Dropout, Low Power Reference... 8 Low Power, 3-Pole, Sallen Key Low-Pass Filter... 8 Offset Voltage Adjustment... 9 Outline Dimensions... 2 Ordering Guide... 2 REVISION HISTORY 3/ Rev. G to Rev. H Changes to Figure 3... 8 2/ Rev. F to Rev. G Changes to Features Section... Changes to Open-Loop Gain Parameter... 3 Changes to Input Voltage Parameter... 9 Updated Outline Dimensions... 2 /8 Rev. E to Rev. F Added 8-Lead MSOP... Universal Changes to Features Section, Figure 2 Caption, and General Description Section... Changes to Settling Time Parameter, Common-Mode Voltage Range Parameter, and Power Supply Rejection Parameter in Table... 3 Changes to Settling Time Parameter, Common-Mode Voltage Range Parameter, and Power Supply Rejection Parameter in Table 2... 5 Changes to Settling Time Parameter, Common-Mode Voltage Range Parameter, and Power Supply Rejection Parameter in Table 3... 7 Changes to Table... 9 Added Thermal Resistance Section... 9 Added Table 5; Renumbered Sequentially... 9 Changes to Figure 26... 3 Changes to Figure 27... Changed Application Notes Section to Applications Information Section... 6 Changes to Figure, Figure, and Figure 2... 7 Changes to Figure... 8 Moved Offset Voltage Adjustment Section... 9 Updated Outline Dimensions... 2 Added Figure 9; Renumbered Sequentially... 2 Changes to Ordering Guide... 2 2/7 Rev. D to Rev. E Updated Format... Universal Updated Outline Dimensions... 2 Changes to the Ordering Guide... 22 5/2 Rev. C to Rev. D Change to SOIC Package (R-8) Drawing... 5 Edits to Features... Edits to Product Description... Delete Specifications for AD82A-3 V... 5 Edits to Ordering Guide... 6 Edits to Typical Performance Characteristics... 8 Rev. H Page 2 of 2
SPECIFICATIONS V S = V, 5 V @ T A = 25 C, V CM = V, V OUT =.2 V, unless otherwise noted. Table. AD82A AD82B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset..8.. mv Maximum Offset over Temperature.5.2.5.9 mv Offset Drift 2 2 μv/ C Input Bias Current V CM = V to V 2 25 2 pa At T MAX.5 5.5 2.5 na Input Offset Current 2 2 2 pa At T MAX.5.5 na Open-Loop Gain V OUT =.2 V to V R L = kω 5 V/mV T MIN to T MAX V/mV R L = kω 8 5 8 5 V/mV T MIN to T MAX 8 8 V/mV R L = kω 5 3 5 3 V/mV T MIN to T MAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise f =. Hz to Hz 2 2 μv p-p f = Hz 25 25 nv/ Hz f = Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise f =. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kω to 2.5 V f = khz V OUT =.25 V to.75 V 93 93 db DYNAMIC PERFORMANCE Unity Gain Frequency.8.8 MHz Full Power Response V OUT p-p =.5 V 2 2 khz Slew Rate 3 3 V/μs Settling Time V OUT =.2 V to.5 V To.%.. μs To.%.8.8 μs INPUT CHARACTERISTICS Common-Mode Voltage Range T MIN to T MAX.2.2 V CMRR V CM = V to 2 V 66 8 72 8 db T MIN to T MAX 66 66 db Input Impedance Differential 3.5 3.5 Ω pf Common Mode 3 2.8 3 2.8 Ω pf Rev. H Page 3 of 2
AD82A AD82B Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Saturation Voltage 2 V OL V EE I SINK = 2 μa 5 7 5 7 mv T MIN to T MAX mv V CC V OH I SOURCE = 2 μa mv T MIN to T MAX 2 2 mv V OL V EE I SINK = 2 ma 55 55 mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = 2 ma 8 8 mv T MIN to T MAX 6 6 mv V OL V EE I SINK = 5 ma 3 5 3 5 mv T MIN to T MAX mv V CC V OH I SOURCE = 5 ma 8 5 8 5 mv T MIN to T MAX 9 9 mv Operating Output Current 5 5 ma T MIN to T MAX 2 2 ma Short-Circuit Current 25 25 ma Capacitive Load Drive 35 35 pf POWER SUPPLY Quiescent Current T MIN to T MAX 62 8 62 8 μa Power Supply Rejection V = 5 V to 5 V 7 8 66 8 db T MIN to T MAX 7 66 db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V) V) to V. Common-mode error voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. 2 V OL V EE is defined as the difference between the lowest possible output voltage (V OL ) and the negative voltage supply rail (V EE ). V CC V OH is defined as the difference between the highest possible output voltage (V OH ) and the positive supply voltage (V CC ). Rev. H Page of 2
V S = ±5 V @ T A = 25 C, V CM = V, V OUT = V, unless otherwise noted. Table 2. AD82A AD82B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset..8.3. mv Maximum Offset over Temperature.5.5.5 mv Offset Drift 2 2 μv/ C Input Bias Current V CM = 5 V to V 2 25 2 pa At T MAX.5 5.5 2.5 na Input Offset Current 2 2 2 pa At T MAX.5.5 na Open-Loop Gain V OUT = V to V R L = kω V/mV T MIN to T MAX V/mV R L = kω 8 5 8 5 V/mV T MIN to T MAX 8 8 V/mV R L = kω 2 3 2 3 V/mV T MIN to T MAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise f =. Hz to Hz 2 2 μv p-p f = Hz 25 25 nv/ Hz f = Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise f =. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kω f = khz V OUT = ±.5 V 93 93 db DYNAMIC PERFORMANCE Unity Gain Frequency.9.8 MHz Full Power Response V OUT p-p = 9 V 5 5 khz Slew Rate 3 3 V/μs Settling Time V OUT = V to ±.5 V To.%.. μs To.%.8.8 μs INPUT CHARACTERISTICS Common-Mode Voltage Range T MIN to T MAX 5.2 5.2 V CMRR V CM = 5 V to 2 V 66 8 72 8 db T MIN to T MAX 66 66 db Input Impedance Differential 3.5 3.5 Ω pf Common Mode 3 2.8 3 2.8 Ω pf Rev. H Page 5 of 2
AD82A AD82B Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Saturation Voltage 2 V OL V EE I SINK = 2 μa 5 7 5 7 mv T MIN to T MAX mv V CC V OH I SOURCE = 2 μa mv T MIN to T MAX 2 2 mv V OL V EE I SINK = 2 ma 55 55 mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = 2 ma 8 8 mv T MIN to T MAX 6 6 mv V OL V EE I SINK = 5 ma 3 5 3 5 mv T MIN to T MAX mv V CC V OH I SOURCE = 5 ma 8 5 8 5 mv T MIN to T MAX 9 9 mv Operating Output Current 5 5 ma T MIN to T MAX 2 2 ma Short-Circuit Current 3 3 ma Capacitive Load Drive 35 35 pf POWER SUPPLY Quiescent Current T MIN to T MAX 65 8 62 8 μa Power Supply Rejection V = 5 V to 5 V 7 8 7 8 db T MIN to T MAX 7 7 db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V) V) to V. Common-mode error voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. 2 V OL V EE is defined as the difference between the lowest possible output voltage (V OL ) and the negative voltage supply rail (V EE ). V CC V OH is defined as the difference between the highest possible output voltage (V OH ) and the positive supply voltage (V CC ). Rev. H Page 6 of 2
V S = ±5 V @ T A = 25 C, V CM = V, V OUT = V, unless otherwise noted. Table 3. AD82A AD82B Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset. 2.3. mv Maximum Offset over Temperature.5 3.5 2 mv Offset Drift 2 2 μv/ C Input Bias Current V CM = V 2 25 2 pa V CM = V pa At T MAX V CM = V.5 5.5 2.5 na Input Offset Current 2 2 2 pa At T MAX.5.5 na Open-Loop Gain V OUT = V to V R L = kω 5 2 5 2 V/mV T MIN to T MAX 5 5 V/mV R L = kω 5 5 V/mV T MIN to T MAX V/mV R L = kω 3 5 3 5 V/mV T MIN to T MAX 2 2 V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise f =. Hz to Hz 2 2 μv p-p f = Hz 25 25 nv/ Hz f = Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise f =. Hz to Hz 8 8 fa p-p f = khz.8.8 fa/ Hz Harmonic Distortion R L = kω f = khz V OUT = ± V 85 85 db DYNAMIC PERFORMANCE Unity Gain Frequency.9.9 MHz Full Power Response V OUT p-p = 2 V 5 5 khz Slew Rate 3 3 V/μs Settling Time V OUT = V to ± V To.%.. μs To.%.5.5 μs INPUT CHARACTERISTICS Common-Mode Voltage Range T MIN to T MAX 5.2 5.2 V CMRR V CM = 5 V to 2 V 7 8 7 9 db T MIN to T MAX 7 7 db Input Impedance Differential 3.5 3.5 Ω pf Common Mode 3 2.8 3 2.8 Ω pf Rev. H Page 7 of 2
AD82A AD82B Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Saturation Voltage 2 V OL V EE I SINK = 2 μa 5 7 5 7 mv T MIN to T MAX mv V CC V OH I SOURCE = 2 μa mv T MIN to T MAX 2 2 mv V OL V EE I SINK = 2 ma 55 55 mv T MIN to T MAX 8 8 mv V CC V OH I SOURCE = 2 ma 8 8 mv T MIN to T MAX 6 6 mv V OL V EE I SINK = 5 ma 3 5 3 5 mv T MIN to T MAX mv V CC V OH I SOURCE = 5 ma 8 5 8 5 mv T MIN to T MAX 9 9 mv Operating Output Current 2 2 ma T MIN to T MAX 5 5 ma Short-Circuit Current 5 5 ma Capacitive Load Drive 35 35 pf POWER SUPPLY Quiescent Current T MIN to T MAX 7 9 7 9 μa Power Supply Rejection V = 5 V to 5 V 7 8 7 8 db T MIN to T MAX 7 7 db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V) V) to V. Common-mode error voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. 2 V OL V EE is defined as the difference between the lowest possible output voltage (V OL ) and the negative voltage supply rail (V EE ). V CC V OH is defined as the difference between the highest possible output voltage (V OH ) and the positive supply voltage (V CC ). Rev. H Page 8 of 2
ABSOLUTE MAXIMUM RATINGS Table. Parameter Supply Voltage Internal Power Dissipation 8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) Input Voltage Rating ±8 V.6 W. W.8 W ((V).2 V) to (V ) 2 V Output Short-Circuit Duration Indefinite Differential Input Voltage ±3 V Storage Temperature Range 8-Lead PDIP (N) 65 C to 25 C 8-Lead SOIC_N (R) 65 C to 5 C 8-Lead MSOP (RM) 65 C to 5 C Operating Temperature Range AD82A/AD82B C to 85 C Lead Temperature(Soldering, 6 sec) 26 C See Input Characteristics section. THERMAL RESISTANCE θ JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type θ JA Unit 8-Lead PDIP (N) 9 C/W 8-Lead SOIC_N (R) 6 C/W 8-Lead MSOP (RM) 9 C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. H Page 9 of 2
TYPICAL PERFORMANCE CHARACTERISTICS 5 5 V S = V, 5V NUMBER OF UNITS 3 2 INPUT BIAS CURRENT (pa) V S = ±5V V S = V, 5V AND ±5V.5..3.2...2.3..5 OFFSET VOLTAGE (mv) Figure. Typical Distribution of Offset Voltage (28 Units) 873-5 5 5 3 2 2 3 5 COMMON-MODE VOLTAGE (V) Figure 7. Input Bias Current vs. Common-Mode Voltage; V S = 5 V, V and V S = ±5 V 873-8 8 k % IN BIN V S = ±5V V S = ±5V 32 2 6 8 8 6 2 2 6 8 OFFSET VOLTAGE DRIFT (µv/ºc) Figure 5. Typical Distribution of Offset Voltage Drift (2 Units) 873-6 INPUT BIAS CURRENT (pa). 6 2 8 8 2 6 COMMON-MODE VOLTAGE (V) Figure 8. Input Bias Current vs. Common-Mode Voltage; V S = ±5 V 873-9 NUMBER OF UNITS 5 5 35 3 25 2 5 5 2 3 5 6 7 8 9 INPUT BIAS CURRENT (pa) Figure 6. Typical Distribution of Input Bias Current (23 Units) 873-7 INPUT BIAS CURRENT (pa) k k k. 2 6 8 2 TEMPERATURE (ºC) Figure 9. Input Bias Current vs. Temperature; V S = 5 V, V CM = V 873- Rev. H Page of 2
M OPEN-LOOP GAIN (V/V) M V S = ±5V k V S = V, 5V INPUT ERROR VOLTAGE (µv) 2 2 POSITIVE RAIL R L = 2kΩ POSITIVE RAIL R L = 2kΩ POSITIVE RAIL NEGATIVE RAIL NEGATIVE RAIL k k k k LOAD RESISTANCE (Ω) Figure. Open-Loop Gain vs. Load Resistance 873- R L = kω NEGATIVE RAIL 6 2 8 2 3 OUTPUT VOLTAGE FROM RAILS (mv) Figure 3. Input Error Voltage vs. Output Voltage Within 3 mv of Either Supply Rail for Various Resistive Loads; V S = ±5 V 873- M k OPEN-LOOP GAIN (V/V) M k R L = kω R L = kω R L = 6Ω V S = ±5V V S = V, 5V V S = ±5V V S = V, 5V V S = ±5V INPUT VOLTAGE NOISE (nv/ Hz) k 6 2 2 6 8 2 TEMPERATURE (ºC) Figure. Open-Loop Gain vs. Temperature V S = V, 5V 873-2 k k FREQUENCY (Hz) Figure. Input Voltage Noise vs. Frequency 873-5 INPUT ERROR VOLTAGE (µv) 3 2 R L = kω 2 3 6 2 8 8 2 6 OUTPUT VOLTAGE (V) R L = kω R L = 6Ω Figure 2. Input Error Voltage vs. Output Voltage for Resistive Loads 873-3 THD (db) 5 6 7 8 9 R L = kω A CL = V S = ±5V; V OUT = 2V p-p V S = ±5V; V OUT = 9V p-p V S = V, 5V; V OUT =.5V p-p k k k FREQUENCY (Hz) Figure 5. Total Harmonic Distortion vs. Frequency 873-6 Rev. H Page of 2
9 OPEN-LOOP GAIN (db) 8 6 2 GAIN R L = 2kΩ C L = pf 2 k k k M 2 M FREQUENCY (Hz) PHASE 8 6 2 PHASE MARGIN (DEGREES) 873-7 COMMON-MODE REJECTION (db) 8 7 6 5 3 2 V S = V, 5V V S = ±5V k k k M M FREQUENCY (Hz) 873-2 Figure 6. Open-Loop Gain and Phase Margin vs. Frequency Figure 9. Common-Mode Rejection vs. Frequency OUTPUT IMPEDANCE (Ω) k. A CL = V S = ±5V. k k k M M FREQUENCY (Hz) Figure 7. Output Impedance vs. Frequency 873-8 COMMON-MODE ERROR VOLTAGE (mv) 5 3 2 55ºC NEGATIVE RAIL 25ºC 25ºC 55ºC POSITIVE RAIL 25ºC 2 3 COMMON-MODE VOLTAGE FROM SUPPLY RAILS (V) Figure 2. Absolute Common-Mode Error vs. Common-Mode Voltage from Supply Rails (V S V CM ) 873-2 6 k OUTPUT SWING FROM TO ±V 2 % 8.%.% ERROR 8 % 2 6 2 3 5 873-9 OUTPUT SATURATION VOLTAGE (mv) V S V OH V OL V S... 873-22 SETTLING TIME (µs) LOAD CURRENT (ma) Figure 8. Output Swing and Error vs. Settling Time Figure 2. Output Saturation Voltage vs. Load Current Rev. H Page 2 of 2
k I SOURCE = ma 2 OUTPUT SATURATION VOLTAGE (mv) I SINK = ma I SOURCE = ma I SINK = ma I SOURCE = µa I SINK = µa 6 2 2 6 8 2 873-23 POWER SUPPLY REJECTION (db) 9 8 7 PSRR 6 PSRR 5 3 2 k k k M M 873-26 TEMPERATURE (ºC) FREQUENCY (Hz) Figure 22. Output Saturation Voltage vs. Temperature Figure 25. Power Supply Rejection vs. Frequency 8 3 SHORT-CIRCUIT CURRENT LIMIT (ma) 7 6 5 3 2 V S = V, 5V V S = V, 5V V S = ±5V V S = ±5V OUT 6 2 2 6 8 2 873-2 OUTPUT VOLTAGE (V) 25 2 5 5 k V S = V, 5V k V S = ±5V M R L = 2kΩ 873-27 M TEMPERATURE (ºC) FREQUENCY (Hz) Figure 23. Short-Circuit Current Limit vs. Temperature Figure 26. Large Signal Frequency Response QUIESCENT CURRENT (µa) 8 7 6 5 3 2 T = 25ºC T = 25ºC T = 55ºC 8 2 6 2 2 28 32 36 TOTAL SUPPLY VOLTAGE (V) Figure 2. Quiescent Current vs. Supply Voltage over Different Temperatures 873-25 Rev. H Page 3 of 2
5V 5µs V S.µF 3 7 V IN 6 AD82 2.µF R L pf V OUT 9 V S 873-28 % Figure 27. Unity-Gain Follower, Used for Figure 28 Through Figure 32 5V µs 9 % 873-29 Figure 28. 2 V, 25 khz Sine Input; Unity-Gain Follower; R L = 6 Ω, V S = ±5 V V 2µs 9 GND % 873-3 873-3 Figure 3. Large Signal Response Unity-Gain Follower; V S = ±5 V, R L = kω mv 5ns 9 % 873-32 Figure 3. Small Signal Response Unity-Gain Follower; V S = ±5 V, R L = kω V 2µs 9 GND % 873-33 Figure 29. V S = 5 V, V; Unity-Gain Follower Response to V to V Step Figure 32. V S = 5 V, V; Unity-Gain Follower Response to V to 5 V Step Rev. H Page of 2
V IN 3 AD82 2 V S.µF 7 6 R L pf V OUT 873-3 V IN kω 2kΩ V S.µF 2 7 6 AD82 3 R L V OUT pf 873-35 Figure 33. Unity-Gain Follower, Used for Figure 3 Figure 35. Gain-of-2 Inverter, Used for Figure 36 and Figure 37 mv 2µs V 2µS 9 9 GND % GND % 873-37 873-36 Figure 3. V S = 5 V, V; Unity-Gain Follower Response to mv Step Centered mv Above Ground Figure 36. V S = 5 V, V; Gain-of-2 Inverter Response to 2.5 V Step, Centered.25 V Below Ground mv 2µs 9 GND % 873-38 Figure 37. V S = 5 V, V; Gain-of-2 Inverter Response to 2 mv Step, Centered 2 mv Below Ground Rev. H Page 5 of 2
APPLICATIONS INFORMATION INPUT CHARACTERISTICS In the AD82, N-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input commonmode voltage extends from.2 V below V S to V less than V S. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figure 29 and Figure 32) and increased common-mode voltage error, as illustrated in Figure 2. The AD82 does not exhibit phase reversal for input voltages up to and including V S. Figure 38a shows the response of an AD82 voltage follower to a V to 5 V (V S ) square wave input. The input and output are superimposed. The output polarity tracks the input polarity up to V S with no phase reversal. The reduced bandwidth above a V input causes the rounding of the output waveform. For input voltages greater than V S, a resistor in series with the AD82 positive input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 38b. Because the input stage uses N-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than V S. V, the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 7. A current-limiting resistor should be used in series with the input of the AD82 if there is a possibility of the input voltage exceeding the positive supply by more than 3 mv, or if an input voltage is applied to the AD82 when ±V S = V. The amplifier can be damaged if left in that condition for more than seconds. A kω resistor allows the amplifier to withstand up to V of continuous overvoltage, and increases the input voltage noise by a negligible amount. Input voltages less than V S are a completely different story. The amplifier can safely withstand input voltages 2 V below the negative supply voltage as long as the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoamp level input currents across that input voltage range. The AD82 is designed for 3 nv/ Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to Figure ). This noise performance, along with the AD82 low input current and current noise, means that the AD82 contributes negligible noise for applications with source resistances greater than kω and signal bandwidths greater than khz. This is illustrated in Figure 39. 9 % GND V S 9 % GND INPUT VOLTAGE NOISE (µv rms) k k V V V V V IN R P V AD82 (a) (b) 5V 2µs µs V OUT Figure 38. (a) Response with R P = Ω; V IN from V to V S (b) V IN = V to V S 2 mv, V OUT = V to V S, R P = 9.9 kω k. k WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. RESISTOR JOHNSON NOISE khz k M M M G SOURCE IMPEDANCE (Ω) Hz AMPLIFIER-GENERATED NOISE Figure 39. Total Noise vs. Source Impedance 873-39 873- G Rev. H Page 6 of 2
OUTPUT CHARACTERISTICS The AD82 unique bipolar rail-to-rail output stage swings within 5 mv of the negative supply and mv of the positive supply with no external resistive load. The approximate output saturation resistance of the AD82 is Ω sourcing and 2 Ω sinking. This can be used to estimate output saturation voltage when driving heavier current loads. For instance, when sourcing 5 ma, the saturation voltage to the positive supply rail is 2 mv; when sinking 5 ma, the saturation voltage to the negative rail is mv. The open-loop gain characteristic of the amplifier changes as a function of resistive load, as shown in Figure through Figure 3. For load resistances over 2 kω, the AD82 input error voltage is virtually unchanged until the output voltage is driven to 8 mv of either supply. If the AD82 output is driven hard against the output saturation voltage, it recovers within 2 μs of the input returning to the linear operating region of the amplifier. Direct capacitive load interacts with the effective output impedance of the amplifier to form an additional pole in the amplifier feedback loop, which can cause excessive peaking on the pulse response or loss of stability. The worst case occurs when the amplifier is used as a unity-gain follower. Figure shows AD82 pulse response as a unity-gain follower driving 35 pf. This amount of overshoot indicates approximately 2 degrees of phase margin the system is stable, but is nearing the edge. Configurations with less loop gain, and as a result less loop bandwidth, are much less sensitive to capacitance load effects. Figure is a plot of noise gain vs. the capacitive load that results in a 2 degree phase margin for the AD82. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. P I NOISE GAIN ( ) P F 5 3 2 3 k 3k k 3k CAPACITIVE LOAD FOR 2º PHASE MARGIN (pf) R R F Figure. Noise Gain vs. Capacitive Load Tolerance Figure 2 shows a possible configuration for extending capacitance load drive capability for a unity-gain follower. With these component values, the circuit drives 5 pf with a % overshoot. V S.µF 3 7 V IN 6 AD82 2.µF Ω V OUT 873-2 V S 2pF 9 % 2mV 2µs Figure. Small Signal Response of AD82 as Unity-Gain Follower Driving 35 pf Capacitive Load 873-2kΩ Figure 2. Extending Unity-Gain Follower Capacitive Load Capability Beyond 35 pf SINGLE-SUPPLY HALF-WAVE AND FULL-WAVE RECTIFIERS An AD82 configured as a unity-gain follower and operated with a single supply can be used as a simple half-wave rectifier. The AD82 inputs maintain picoamp level input currents even when driven well below the negative supply. The rectifier puts that behavior to good use, maintaining an input impedance of over Ω for input voltages from V from the positive supply to 2 V below the negative supply. The full- and half-wave rectifier shown in Figure 3 operates as follows: when VIN is above ground, R is bootstrapped through the unity-gain follower, A, and the loop of Amplifier A2. This forces the inputs of A2 to be equal; thus, no current flows through R or R2, and the circuit output tracks the input. When VIN is below ground, the output of A is forced to ground. The 873-3 Rev. H Page 7 of 2
noninverting input of Amplifier A2 sees the ground level output of A; therefore, A2 operates as a unity-gain inverter. The output at Node C is then a full-wave rectified version of the input. Node B is a buffered half-wave rectified version of the input. Input voltages up to ±8 V can be rectified, depending on the voltage supply used. A 3 V IN 2 A 9 A V S 7 R kω.µf 6 AD82 2 3 A2 R2 kω V S.µF 7 6 AD82 C FULL-WAVE RECTIFIED OUPUT B HALF-WAVE RECTIFIED OUPUT With a ma load, this reference maintains the.5 V output with a supply voltage down to.7 V. The amplitude of the recovery transient for a ma to ma step change in load current is under 2 mv, and settles out in a few microseconds. Output voltage noise is less than μv rms in a 25 khz noise bandwidth. LOW POWER, 3-POLE, SALLEN KEY LOW-PASS FILTER The high input impedance of the AD82 makes it a good selection for active filters. High value resistors can be used to construct low frequency filters with capacitors much less than μf. The AD82 picoamp level input currents contribute minimal dc errors. Figure 5 shows an example of a Hz three-pole Sallen Key filter. The high value used for R minimizes interaction with signal source resistance. Pole placement in this version of the filter minimizes the Q associated with the two-pole section of the filter. This eliminates any peaking of the noise contribution of Resistor R, Resistor R2, and Resistor R3, thus minimizing the inherent output voltage noise of the filter. C2.22µF B C % V IN R 23kΩ R2 23kΩ C.22µF R3 23kΩ V S.µF 3 7 C3 6 AD82.22µF 2.µF V OUT Figure 3. Single-Supply Half- and Full-Wave Rectifier.5 V LOW DROPOUT, LOW POWER REFERENCE The rail-to-rail performance of the AD82 can be used to provide low dropout performance for low power reference circuits powered with a single low voltage supply. Figure shows a.5 V reference using the AD82 and the AD68, a low power 2.5 V band gap reference. R2 and R3 set up the required gain of.8 to develop the.5 V output. R and C2 form a lowpass RC filter to reduce the noise contribution of the AD68. 5V 3 C.µF 2 U AD68 6 2.5V ± mv R kω U2 AD82 7 6 3 2 C2.µF FILM R2 9kΩ (2kΩ) R3 kω (25kΩ) 873-5 2.5V OUTPUT.5V OUTPUT C3 µf/25v REF COMMON 873-6 FILTER GAIN RESPONSE (db) V S 2 3 5 6 7 8 9. k FREQUENCY (Hz) Figure 5. Hz Sallen Key Low-Pass Filter 873-7 Figure. Single Supply.5 V Low Dropout Reference Rev. H Page 8 of 2
OFFSET VOLTAGE ADJUSTMENT The offset voltage of the AD82 is low, so external offset voltage nulling is not usually required. Figure 6 shows the recommended technique for the AD82 packaged in plastic DIP. Adjusting offset voltage in this manner changes the offset voltage temperature drift by μv/ C for every millivolt of induced offset. The null pins are not functional for the AD82 in the 8-lead SOIC and MSOP packages. 3 2 AD82 5 2kΩ V S V S 7 6 Figure 6. Offset Null 873- Rev. H Page 9 of 2
OUTLINE DIMENSIONS. (.6).365 (9.27).355 (9.2).2 (5.33) MAX.5 (3.8).3 (3.3).5 (2.92).22 (.56).8 (.6). (.36) 8. (2.5) BSC 5.28 (7.).25 (6.35).2 (6.).5 (.38) MIN SEATING PLANE.5 (.3) MIN.6 (.52) MAX.5 (.38) GAUGE PLANE.325 (8.26).3 (7.87).3 (7.62).3 (.92) MAX.95 (.95).3 (3.3).5 (2.92). (.36). (.25).8 (.2).7 (.78).6 (.52).5 (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 7. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 766-A 5. (.968).8 (.89). (.57) 3.8 (.97) 8 5 6.2 (.2) 5.8 (.228).25 (.98). (.) COPLANARITY. SEATING PLANE.27 (.5) BSC.75 (.688).35 (.532).5 (.2).3 (.22) 8.25 (.98).7 (.67).5 (.96).25 (.99).27 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 8. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 27-A Rev. H Page 2 of 2
3.2 3. 2.8 3.2 3. 2.8 8 5 5.5.9.65 PIN IDENTIFIER.65 BSC.95.85.75.5.5 COPLANARITY...25. MAX 6 5 MAX.23.9 COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure 9. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters.8.55. -7-29-B ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD82AN C to 85 C 8-Lead PDIP N-8 AD82ANZ C to 85 C 8-Lead PDIP N-8 AD82AR C to 85 C 8-Lead SOIC_N R-8 AD82AR-REEL C to 85 C 8-Lead SOIC_N R-8 AD82AR-REEL7 C to 85 C 8-Lead SOIC_N R-8 AD82ARZ C to 85 C 8-Lead SOIC_N R-8 AD82ARZ-REEL C to 85 C 8-Lead SOIC_N R-8 AD82ARZ-REEL7 C to 85 C 8-Lead SOIC_N R-8 AD82ARMZ C to 85 C 8-Lead MSOP RM-8 A2L AD82ARMZ-RL C to 85 C 8-Lead MSOP RM-8 A2L AD82ARMZ-R7 C to 85 C 8-Lead MSOP RM-8 A2L AD82BR C to 85 C 8-Lead SOIC_N R-8 AD82BR-REEL C to 85 C 8-Lead SOIC_N R-8 AD82BRZ C to 85 C 8-Lead SOIC_N R-8 AD82BRZ-REEL C to 85 C 8-Lead SOIC_N R-8 AD82BRZ-REEL7 C to 85 C 8-Lead SOIC_N R-8 Z = RoHS Compliant Part. Rev. H Page 2 of 2
NOTES Rev. H Page 22 of 2
NOTES Rev. H Page 23 of 2
NOTES 9962 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D873--3/(H) Rev. H Page 2 of 2