Physics 226 FPGA Lab #1 SP Wakely I Terasic DE0 Board The DE0 Development and Education board is designed in a compact size with all the essential tools for novice users to gain knowledge in areas of digital logic, computer organization and FPGAs. It is equipped with Altera Cyclone III 3C16 FPGA device, which offers 15,408 LEs. The board provides 346 user I/O pins, and is loaded with a rich set of features that makes it suitable to be used for advanced university and college courses, as well as the development of sophisticated digital systems. The DE0 combines the Altera low-power, low-cost, and high performance Cyclone III FPGA to control the various features of the DE0 Board. The DE0 Development Board includes software, reference designs, and accessories required to ensure the user simple access in evaluating their DE0 Board. II Getting Started Be sure your Mac is booted into Windows XP mode. If you don t know how to do this, get help from Mark or your TA. Once booted, plug the DE0 the Mac using the USB cable. The 7segment readouts should begin counting from 0 to F and the LEDs should scan back and forth. If this doesn t happen, make sure the Run/Program switch is set to Run and the red push-button switch is ON. Now start up the Quartus II software and start a new project using: FILE-> New Project Wizard
The New Project Wizard dialog will open, like so: Click Next and pick directory and name for your project. It is a good idea to use a new subdirectory so that your files don t mingle with the files of other projects. Click Next here, and again at the Add Files page, to arrive at the Family and Device Setting dialog (page 3/5).
Once here, be sure that the Family field shows Cyclone III. Select the Device named EP3C16F484C6 (this is the FPGA type installed on the DE0 ): Now click Finish to complete the Project Wizard. Your screen should now look something like this:
III Hello World Now you are going to do the hardware equivalent of a Hello World program you are going to make an LED turn on. We ll learn about how to use the Quartus II software as we go. Select FILE->New. Under Design Files, select Block Diagram/Schematic File and then hit OK. You should now be in schematic entry mode, which allows you to draw devices on the screen to build up your circuits. You can add circuit elements by clicking on the Symbol Tool, indicated by the gate icon: You can add input or output ports by clicking on the Pin Tool, next to the symbol tool.
We connect circuit elements together by using the Node Tools, of which there are two: The first tool ( Orthogonal Node Tool ) is for right-angles connections, and the other ( Diagonal Node Tool ) is for direct, point-to-point connections. It will be less work to use the right angle connector, so consider using that most often. Now - click on the Pin Tool and select an OUTPUT. A little ghostly output pin will appear next to your cursor. Drag it to the middle of the screen and left-click to drop it. Next, click on the Symbol tool. This will bring up a dialog like so. Navigate down to Primitives Other and select the Vcc element.
Drag the Vcc element over to your schematic and place it to the left of your output pin. Now select the Orthogonal Node tool and connect the Vcc point to the output pin. Your schematic should look something like this: At this point save your schematic file by hitting control-s. Pick a filename and click Save. Now we will synthesize our schematic using the Start Analysis and Synthesis icon: This tool does a preliminary analysis of the schematic and attempts to convert it into logic-gate level form for the final compilation. It should take a short time to run and will probably give you a few warnings. This is ok. If you successfully synthesized, you will have a logical output pin that is defined, but not associated with any of the physical pins on the FPGA. To complete the design, you need to connect your logical pin to a physical pin using the Pin Planner Tool (under menu item Assignments, or via Control-Shift-N).
Click on the Pin Planner. A dialog will open which looks like this, showing all the 484 pins on the FPGA. To assign your pin properly, look at the bottom half of this dialog and click in the Location field in the row corresponding to your pin (in this case pin_name1 ), and type a pin number. A list of pin numbers is included in the DE0 manual and also at the end of this manual. In the present case, we will use PIN_J1, which corresponds to the 1 st green LED (LED Green[0]) on the DE0 board. Type Pin_J1 or just J1 into the field and hit enter. Now exit the Pin Planner (hit X button, upper right). Always be sure to synthesize your design before trying to assign pins, as the synthesis process identifies open pins and places them in this dialog for you to assign.
Looking back at the schematic there should now be a pin assignment tagged next to the output pin, like so: We are now ready to compile! Select the Compile button and wait with bated breath... The compilation process can take a minute or more, depending on how complicated your design is. You will likely get 10-20 warnings during the compilation. This is ok. If the compilation was successful, you now have a fully-defined design and you need to burn it into the FPGA. This is done using the Programmer function:
Running the Programmer will bring up a dialog like so: If USB-Blaster does not show up next to the Hardware Setup button, click that button and select it from the Currently Selected Hardware drop-down. If USB-Blaster is not an option, then your USB driver is not installed properly, and you may need to get help from the TA. If all is well, then click the Start button and the FPGA will be programmed. If the progress bar doesn t show 100% (Successful) within a few seconds, be sure that your device is in RUN mode. If all else fails, ask your TA. After the device is programmed, you should notice that the counting and flashing on the DE0 have stopped and that the right-most green LED is lit. Congratulations! You just made your Hello World program and learned how to use an FPGA.
IV Adding Input That was a little too easy, so now let s add some user input. Go to File->Save As and save your schematic under another name. We are going to add a few components. First - add another pin. This time an INPUT pin. Position it to the left of the output pin. Next, delete the Vcc pin and the connecting wires. To do this, click on them to make the blue selection indicators appear. Then hit the delete key. Now, using the Symbol Tool, add a NOT gate (it is under Primitives Logic) and connect one end to the input and one end to the output. Hit control-s to save. Now, synthesize and assign pins. You want to associate your login INPUT pin to an input on the DE0 board. We will use PIN_F1, which is push-button 2 (the left-most one). Your schematic should now look something like this: Now save (Control-S) and Compile and Program. The right-most green LED should now be dark, until you push button 2, when it will light up (you may have to push it hard on some of the DE0s). Congratulations! You have now performed IO with your FPGA. The reason that we had to put the inverter in there is that the default output signal associated with the three pushbutton inputs is HI (3.3V). By pressing the button, you are actually asserting a LO state. Remember this for later when you are assigning logic to the IO pins.
V Time to get Serious. In lab 14, you built a synchronous 2-bit counter now we are going to expand on this to make a 4- bit counter, using the DE0. If you can t remember how the counters worked, consult your lab manual or H&H. Let s start a new project for this circuit. Follow the instructions from section II, above. Make a schematic file and insert a JK Flip/Flop into the circuit (Symbol Tool Primitives Storage). Take the flip-flop and tie the J and K inputs together. Now copy and paste this 4 times. You should have something like this: Next, - working from the synchronous 2-bit counter in the lab manual (pg 338), connect the flip/flops properly to make a 4-bit counter. Some hints: 1) Tie the first FF s input to Vcc (Symbol Primitives Other) and chain the remaining FFs properly. 2) Tie button 2 (F1) to the clock inputs 3) Tie button 1 (G3) to the global reset. 4) Tie the output of the each stage to an LED, to display the count. Synthesize and add assign pins and your circuit should look something like this (this has output lines omitted).
Finally, add an output for each stage of the counter and tie it to an LED. Synthesize and assign pins. Now compile it and test your counter. Does your circuit operate like a 4-bit counter should? Can you figure out what is wrong with the logic? Rebuild the circuit with a few additional components needed to correct the action. Your circuit should ultimately look something like this: Compile, Program and Test.
VI More output options In addition to LEDs, the DE0 also has four 7-segment displays which can be used to show hexadecimal numbers. The connections on the DEX0 7-seg display are shown here: With the appropriate conversion logic, we can use one of these to display the output of our counter. However, if you think about it for a minute, you will see that it is not trivial. Here is what the gatelevel logic looks like:
Fortunately, there are ICs built to do the hard work for us and several of these ICs are modeled already in the Quartus software. This is one of the fabulous benefits of designing with FPGAs the entire phase space of available logical devices is there for you to use with just a few clicks. Go to the Symbol Tool and use the search field to locate a 7447 chip: Insert this into your schematic, along with 7 outputs for your 7seg display, like so. Be sure to get the pin assignments correct, or it won t work properly.
To enable the converter for your circuit, you will need to tie the LTN and BIN pins to VCC, as shown. Now hook up the 7447 inputs to your counter outputs. Your schematic should look something like this: Compile it and test it. How does it work? Why does it fail for counts greater than 9? How could you modify your counter to loop with the proper modulus to match the BCD display? Make sure that your additional logic doesn t conflict with your reset (you can t have 2 parts of the circuit asserting different levels, so you will need another gate). The result should look something like this. Test it.
VII Adding a Clock Many modern digital logic applications require a clock - a constant stream of fixed-interval logic transitions. The DE0 has several clocks available for use, but they are all at 50 MHz. If you need a lower clock rate for something, you have to divide down the 50 MHz to whatever you require. Let s do this now to make an LED blink. There are several ways to down-shift the clock, but we are going to use a built-in counter function called the lpm_counter. LPM stands for Library of Parameterized Modules which is a standard for implementing various kinds of digital logic structures on different architectures. The built-in counter allows us to reproduce our entire flip-flop counter with a few clicks. Let s add a counter to the schematic. Don t erase anything you have already done just add the new part to some unused corner in on the left side of the schematic. To add your lpm_counter, first click on the Symbol Tool to add a new device. This time, navigate to Megafunctions Arithmetic. Highlight lpm_counter and click OK. The MegaWizard dialog will now open and start to walk you through producing a custom counter, based on your specific needs.
Click Next to begin entering your parameters: At this dialog, you pick how many bits the counter will be. You need to select a bus width that is sufficiently large to accommodate the division you are attempting. We want to get 50MHz down to a few Hz, so we will need at least 24 bits (50MHz/2^24 ~ 3Hz). Click Next.
On this page, we have the option to pick a modulus for the counter other than a power of 2. We will just stick with a standard counter. Click Finish and then Finish again at page 7. If you get a dialog like this: Click the checkbox and then Yes. Now your cursor will have a ghostly counter attached to it. Drop the counter somewhere below your other devices. Now add an input pin to the left of the counter and connect it to the counter. It might be good at this point to double-check on the pin name (should be pin_name3 or something) and rename the pin to something like CLOCK. To do this, double-click on the name until it becomes editable. Now let s grab the output from the counter. There is one minor complexity in doing this. As this device is a 24-bit counter, it actually has 24 output pins, but for compactness, they are collected into a bus. Busses cannot be directly connected to output pins, because the compiler doesn t know which of the multiple bus lines you are interested in connecting. The solution is quite simple. You will need to use the Bus Tool or to extend the counter bus out in a little stub, then you will label the contents of the bus. To do this, draw a short line from the q[23..0] port on the counter. Hit escape and the end of the bus will turn into a little X. Now click the bus line again so it highlights blue and type cnt[23..0] and hit enter. This assigns a name ( cnt ) to contents of this bus, and tells the compiler that there are 24 lines in it. The counter and bus should look like this when you are done:
Now, add an output pin and connect it to the bus with a trace. You are going to label the trace cnt[23] so that the compiler know that you are only picking off the 24 th bit of this bus. Label the output pin LED1. Synthesize everything and associate the pins. You want to associate the clock pin with G21, which is one of the DE0 50MHz clocks. And you want to associate cnt[23] with J2, which is the 2 nd LED (LED1 when 0-indexed).. This part of your schematic should now look something like this (never mind if your counter is called lpm_counter0 or something different). If it does, compile the project and program the DE0. LED 1 should now be blinking at a few Hz and the rest of the board should continue to respond to presses on button 2. Neato! Now let s let our clock drive our counter circuit. Break the connection between button 2 and the clock and replace it with a tap off of the cnt[23] line. Compile, program and run. Now that looks cool, doesn t it? This is cool, but still a little boring. How would you speed up the counter rate? What will happen to the counting rate if you pick off bit 21 from the counter bus?
VIII Final Project Stopwatch Now let s put a bunch of these pieces together and build a stopwatch with millisecond resolution. We will need a clock, some conversion logic and display logic, and start/stop/reset inputs. Start a new project for this. For this project, you will need a binary->bcd->7seg converter with at least 12 bits of width. (In principle, we should have a 14-bit converter to allow a countup to at least 9999, but to simply things, we are only using 12.) If you have time, you can try implementing all this yourself - you will need 8 74185 chips and 4 7447s. You should also attach output pins to all of the 7447 chips and assign them to your 7seg displays. For added fun, pick off an output for each of the bits of the counter and assign them to an LED. If you don t have time to do all this, you can download a bdf file from the chalk site, with all of these things defined. It is under Course_Documents FPGA_LAB bcd_7seg_code_provided.bdf. You might have assign pins yourselves even with the bdf file. Now - start a new project and get your conversion logic in here is what the schematic should look like.
Working on the same schematic, let s begin adding more bits. Let s start by making our clock. We will use the same kind of lpm_counter object as in the last section, but this time we will give it a modulus of 50000 to give us a 1000Hz clock. Be sure to specify enough bits to accommodate a full 50,000 modulus. Now you have a 1kHz clock, and some display code, you will need to define the controls of your stopwatch. Consider the logic you will require for a start, stop, and reset. Make some inputs and associate them with some buttons. You will need something for these inputs to control another counter. This will be the heart of the stopwatch. Build another lpm_counter, with the proper characteristics. Remember that your 7seg logic is only 12 bits, so you only need a 12-bit counter. However, we do want 2 extra options: 1) a clear input (use the asynchronous clear) and 2) a carry-out feature. The carry-out sends a line high when the maximum count of the counter is reached. Your stopwatch should behave according to these rules 1) Upon programming, the clock should read 0000 and not be running. 2) Pushing Start should start the clock a. Repeated starts have no effect 3) Pushing Stop should stop the clock a. Repeated stops have no effect 4) Pushing Reset should reset the counter, even when running a. Reset should NOT stop the clock 5) When 4095 ms is hit, the clock should stop automatically and lock out further starts/stops until reset. When building your logic, remember that the pushbuttons are HI until pressed, which drives them LOW. Hint: you may want to make use of an unclocked SET/RESET flip flop for your start logic. Don t see one in the library? Can you build one from NOR gates?
APPENDIX: DE0 pin outs: