EM Noise Mitigation in Circuit Boards and Cavities

EM Noise Mitigation in Circuit Boards and Cavities Faculty (UMD): Omar M. Ramahi, Neil Goldsman and John Rodgers Visiting Professors (Finland): Fad Seydou Graduate Students (UMD): Xin Wu, Lin Li, Baharak Mohajeriravani, and Shahrooz Shahparnia Mechanical Engineering Department, Electrical and Computer Engineering Department and CALCE Electronic Products and Systems Center University of Maryland, College Park, MD Microwave Effects and Chaos in 21st Century Analog & Digital Electronics AFOSR MURI October 2004 Review MURI contract F496200110374 Rockville, MD Page 1

Previous Work and Recent Work Developing 3-dimensional full-wave predictive tools for cavity Resonance and S Parameters [Completed] Developing fast predictive modeling tools for PCB analysis [Completed] Using lossy material coating to reduce aperture radiation [Completed] Reduction of coupling between cavities using high-impedance surfaces [Completed] Page 2

Previous Work and Recent Work Reducing noise in printed circuit boards using high impedance surface Previous: 1. Concept development 2. Experimental verification 3. Wideband extension New: 1. Accurate wideband prediction 2. Wideband extension using advanced materials 3. Band gap design 4. Miniaturization Page 3

Reduce switching and other noise in Printed Circuit Boards Page 4

Importance of PCBs Everything will be printable! Cost Compactness PCB not radiating immune from external radiation Page 5

EM Noise in PCB signal power Active devices via A via C via D V DD ±δv 1 via B Gnd ±δv 2 3 Page 6

Motivation Problem: Switching noise. Noise-generating device Device subject to noise Signal passing through the power planes Signal Layers Power Bus Layers Digital Device Need to do something for mitigation of noise beyond ~ 500MHz Page 7

Coupling to Sensitive Devices in a Multi-Layer Stack up Incoming radiation outgoing waves 3 Page 8

Problem and Classical Solutions Interconnect and Board Inductance R-L circuit model for the power plane Power Distribution Network z + load current source y - x dielectric Copper Voltage drop between two points on the board depends on the inductance, L, and resistance R. V L = L eff i t Page 9

Decoupling Capacitors around Noise Source No decaps With decaps Experiment (with decaps) 0-10 -20 S12(dB) -30-40 load Noise Source -50-60 -70 experimental data with decaps from [5] simulation with decaps simulation without decaps 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (GHz) 8 decoupling capacitors around noise source: C=10nF, L=2nH, R=50mΩ 4 Page 10

Classical Methods: Ineffective at Microwave Frequencies Effect of Capacitors Placement at 200MHz and 1GHz Conclusion: Need to do something for mitigation 99 caps 200 MHz of noise beyond ~500MHz No caps 200 MHz Effective NOT Effective no caps 1 GHz 99 caps 1 GHz 4 Page 11

Possible Solutions Embedded Capacitance Embedded Capacitors capacitor 2 Page 12

Electromagnetic Band Gap Structures for switching noise mitigation Page 13

Electromagnetic Band Gap Structures (EBG) for Surface Wave Suppression gap Metallic patch a ε r t Top view of HIS with square patches Page 14

Interpretation: EBG as a Series of Parallel LC Resonators ω 0 = 1 LC Page 15

Suppression Mechanism Power planes radiate like patch antennas Dielectric (such as FR4) Radiation suppression HIS Power Bus Both propagation and emission from the board are suppressed with the employment of EEBG/EHIS structures. Page 16

Power Plane with Embedded HIS PCB HIS 0-10 -20-20 db band gap S12 [db] -30-40 -50-60 -70-80 fl fh 1 2 3 4 5 Frequency [GHz] 3 Page 17

Stop Band Prediction Analysis of a unit cell provides eigenmode solutions for Maxwell s equations 8 fh a Γ g/2 M X Frequency [GHz] 7 6 5 4 3 2 Mode 3 fl Mode 2 Light Line BAND GAP w 1 0 Mode 1 Γ-X X-M Phase constant β M-Γ Page 18

Widening the Gap: Concept: Vertical Integration lower via upper via Surface patches top plate g a bottom plate w a upper via Increasing inductance while maintaining constant periodicity lower via half-loop inductor normal to the vias 3 Page 19

EBG Inductance-Enhanced Power Planes Parallel plate With decaps Achieved a 3.2 GHz 20 db bandwidth! With HIS 5 Page 20

Experimental Validation 0-10 -20-30 S12 in db -40-50 -60-70 SMA 1 SMA 2-80 0 2 4 6 8 10 12 14 16 18 20 Frequency (GHz) 2x1.54mm HIS: period a = 10mm and gap g = 0.4 mm Page 21

Widening the Gap Concept: Cascading Concept: cascaded filter design 5mm HIS 10mm HIS 20mm HIS SMA Connector Locations 4 Page 22

Experimental Validation 0 Magnitude of S21(dB) -10-20 -30-40 -50-60 -70-80 0 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) S21 Board with HIS 5 Page 23

Experimental Validation Without HIS Magnitude of S21(dB) 0-10 -20-30 -40-50 -60-70 -80 Achieved 9GHz Stop Band! S21 Board with HIS S21 Board without HIS 0 1 2 3 4 5 6 7 8 9 10 Frequency (GHz) With HIS Page 24

Widening the Gap Concept: High Permittivity Material EBG gap Power plane copper thickness Above patch dielectric EBG patch thickness Below patch dielectric Power plane copper thickness EBG via diameter (a) Page 25

Numerical Validation Dispersion diagram for entries 5, 7 and 8 in Table I. Entry 5 can achieve and ultra-wide band gap (11 GHz) using high-dielectric material. Cascading entries 7 and 8 can also achieve a wide-band region (16 GHz) but at a far lower cost. Page 26

Numerical Validation Entry Number Patch size (mm) Above patch ε r Below patch ε r Above patch th. (um) Below patch th. (um) Patch th. (um) Gap size (um) Via diameter (um) f l f h 1 10x10 4.1 4.1 1540 1540 0 400 800 2.13 4.03 2 10x10 8.2 4.1 1540 1540 0 400 800 1.6 3.71 3 10x10 12.3 4.1 1540 1540 0 400 800 1.35 3.12 4 10x10 16.4 4.1 1540 1540 0 400 800 1.22 2.87 5 2x2 30 4.1 16 100 0 200 125 2.3 13.1 6 2x2 30 4.1 16 100 35 200 125 2.28 13.2 7 2x2 4.1 4.1 16 100 0 200 125 5.96 18.1 8 5x5 4.1 4.1 16 100 0 200 125 2.17 6.46 9 5x5 16.4 4.1 16 100 0 200 125 1.11 6.44 Page 27

Experimental Validation $$$ Page 28

Achievements EBG Structures Method Buried Capacitance Layers Surface Mounted Decoupling Capacitors 100KHz 1MHz 100MHz 1GHz 10GHz Frequency (MHz) Page 29

Part II: EMI Reduction from PCBs (Interference and Immunity) Page 30

External Radiation from PCBs High-Speed Gate i Load i GND Dielectric, ε r VDD Time-varying electromagnetic fields Page 31

EMI Reduction through EBGs Concept: Same as switching noise mitigation If waves don t travel within the PCB, they will not radiate! Vdd Plane d t a 2 Page 32

EMI Measurement Setup 5mm x 5mm patches BUT HIS Monopole SMA VNA 10cm x 6.5cm board Page 33

Effect of HIS on EMI Magnitude of S21 (db) -20-30 -40-50 -60-70 -80-90 Without HIS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz) 4 Page 34

Effect of HIS on EMI Magnitude of S21 (db) -20-30 -40-50 -60-70 -80-90 Without HIS With HIS ~4.5GHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Frequency (GHz) Page 35

Part III: Multiband EBG Design Page 36

Novel single-layer inductance-enhanced EBG a W2 g/2 W3 l1 l2 Ws W1 s Variable line width inductor used to replace patch of standard HIS Inductance of spiral adds in series to that of via High fringing capacitance through fat outer lines Additional design variables: number of turns, starting inner diameter, trace width W4 W implementation for a period of 10 mm Page 37

Electrical performance of novel EBG in parallel-plate environment Dispersion diagram S-parameters s=0.4 mm, W=9 mm, g=1 mm, a=10 mm, W1=3.5, W2=W3=W4=2.5 mm, l1=1.5 mm, l2= 2 mm, Ws = 0.5 mm Existence of two band-gaps Multiband noise mitigation possible Type of modes also analyzed by looking at field plots at different phase constant Page 38

Upper bandgap tuning using spacing Frequency[GHz] 4 3.5 3 2.5 2 1.5 1 0.5 0 Mode 1 Mode 2 Mode 3 Mode 1 Mode 2 Mode 3 0 0.2 0.4 0.6 0.8 1 k/pi[1/cm] Spacing (gap) is reduced from 1mm (filled symbols) to 0.4 mm (empty symbols) Upper band: Moves towards lower frequencies with slight variation in the bandwidth Lower band: Lower edge slightly affected Change can be compensated through variation in the spiral inductor geometry or period This indicates that the two bands can be tuned independently Page 39

Second band-gap disappearance in a structure with smaller periods Frequency [GHz 12 10 8 6 4 2 mode 1 mode 2 mode 3 g=0.6 mm 0 0 50 100 150 200 Phase ka [degrees] Page 40

Effect of number of turns on first band-gap Physical dimensions: a=5mm, g=0.6mm, t=d=1.54mm Band-gap shift to lower frequency, when traditional HIS replaced with novel EBG Band-gap lowering with increase in number of turns Fractional bandwidth > 40% at 2GHz Frequency [GHz] 10 8 6 4 2 0 center frequency lower corner freq. upper corner freq fractional bandwidth 0 1 2 3 Number of turns 80 70 60 50 40 30 20 10 0 Fractional bandwidth [%] Note: N=0 corresponds to standard HIS Page 41

Complementary Structure a W2 g/2 W3 l1 l2 Ws W1 W4 concept W Practical implementation for large period (a=10mm) Page 42

EBG using spiral with outer loop closed as patch: simulation results W=9 mm, g=1 mm, a=10 mm, W1=3.5, W2=W3=W4=2.5 mm, l1=1.5 mm, l2= 2 mm, Ws = 0.5 mm. Band-gap region at lower frequencies compared to power plane with standard HIS Page 43

EBG Structures embedded in PCB s The whole structure, acts as a band-stop filter by suppressing surface waves within a predictable range of frequencies. It also suppresses waves supporting surface currents This frequency range is a function of the geometrical features of the structure (such as periodicity, patch size, gap size, via diameter, via length and also board thickness) as well as the dielectric material used in the printed circuit board as substrate. Page 44

Part III: Accurate Band Gap Prediction Page 45

Electromagnetic Bandgap Structures: Lumped Element Perspective ω = 0 1 LC C L Normal Incident Waves Page 46

Design and simulation of EEBG structures is followed by fabrication using a commercial PCB process with FR-4 as dielectric. Design and Fabrication Buried via HIS Patch Power Bus Page 47

Need for Simple and Accurate Models Full wave simulations are slow and costly It is costly and not feasible to do trial and error experiments Engineers like to have initial but accurate estimations of the resulting bandgap by doing a couple of calculations Page 48

Fast and Simple Design Technique Lateral view of a single cell Physics-based circuit modeling HIS via (L value: approximate methods) Plate-to-Patch Capacitance (C 1 = ε r ε 0 S p2 / H v ) Patch-to-Plate Capacitance (C 2 = ε r ε 0 S p2 / H v ) 1 f res = 2 π L ( C 1 + C 2 ) Page 49

Accuracy of the Model Accuracy of the model while the patch sizes changes (C 1 and C 2 change) Accuracy of the model while the via radius changes (L changes) Center Frequency (f res ) Center Frequency (f res ) 9 8 7 6 5 4 3 2 1 4.25 4.00 3.75 3.50 3.25 3.00 2.75 2.50 Model Full wave 4 6 8 10 12 14 16 18 20 Patch size (S P ) Model Full wave 2.25 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Via radius (V D /2) Page 50

3D Model EEBG cell model integrated in a macro-model of power/ground planes. L L 5 L L 6 L L 3 C C 3 L L 5 C C 5 C C 1 L L L 6 L 3 L L 3 C C C 6C 3 C L L C 5L 4 L 5 C C 1 C C C C 1 L C 4 C 5 L 1 LC L LC6 6 L 3 L L L 4 L 5 C C C C 6C 3 C 2 C C C L C 1 C C 5L 4 L L 6 C C 6 L L 4 C C 4 L L 1 C C C 3 C 2 L L 1 C C 4 C C 2 L L 1 C C 2 Page 51

Why the circuit model? Reduce printed circuit board simulation time from HOURS to seconds! Page 52

Numerical and Experimental Results 0-25 Magnitude of S21(dB) -50-75 -100-125 -150 Model HFSS Measurements 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency (GHz) Page 53

Conclusions Provided accurate EBG-embedded PCB models Introduced multi-band EBG design concepts Introduced three different concepts for wideband applications Page 54

Future Work Miniaturization! Page 55