RTL8305S 5-PORT 10/100 MBPS SINGLE CHIP SWITCH CONTROLLER

Transcription

1 5-PRT 0/00 MBPS SNGLE CHP SWTCH CNTRLLER. Features General Description Block Diagram Pin Assignments Pin Descriptions Media Connection Pins Mode Pins Port Related Pins LED Pins Power Pins Miscellaneous Pins Reserved Pins Functional Description ntroduction Switch Core Functional verview Address Search, Learning and Aging Buffer Management Data Reception Data Forwarding Flow Control Back-off Algorithm nter-frame Gap llegal Frame Broadcast Storm Control Physical Layer Functional verview Auto-negotiation Base-T Transmit Function Base-T Receive Function Link Monitor Base-TX Transmit Function Base-TX Receive Function Power Saving Mode LED M Port General Description M/SN PHY Mode M MAC Mode Electrical Characteristics Absolute Maimum Ratings perating Range DC Characteristics (0 C<Ta<60 C, 3.5V<Vcc<3.5V) AC Characteristics (0 C<Ta<60 C, 3.5V<Vcc<3.5V) Digital Timing Characteristics Thermal Data Application nformation System Application Diagram Mechanical Dimensions /02/9

2 . Features 5-port integrated switch with physical layer and transceiver for 0Base-T and 00Base-TX with 5-port 0/00M UTP or -port 0/00M UTP + -port M/SN PHY mode M/SN interface for router application MAC mode M interface for HomeLAN/00Base-FX application Mbit internal RAM for packet buffer nternal K look-up table entries 25MHz crystal or SC input Non-blocking wire-speed reception and transmission Fully compliant with EEE 802.3/802.3u Supports broadcast storm filtering function Support full duple flow control and half duple back-pressure flow control LED indicators for link/activity, speed, full/half duple and collision LEDs blinking upon reset for LED diagnostics Unmanaged operation by strapping upon reset Power saving with cable detection Low power consumption at 3.3V operating voltage 28-pin PQFP package 2. General Description The is a highly integrated layer 2 single chip switch controller which incorporates 5 MACs (Media Access Controller), 5 physical layer transceivers, -Mbit SRAM and K-entry look-up table into one single chip. The contains 5 ports, and each one provides support for a 0Base-T (0Mbps) or 00Base-TX (00Mbps) network connection. The fifth port (port ) can be configured as a M/SN to work with a routing engine, HomePHY or a fiber transceiver for a 00Base-FX application. And each operation mode can be easily set up by hardware strapping upon restart or power-on. The is designed for a stand-alone switch system through hardware strapping upon reset to achieve unmanaged operation and can be easily integrated with DSL/Cable modem router. With the least peripheral components and using a 25MHz crystal, the has the best system cost structure. The integrated chip benefits from low power consumption and ease of use for SH 5-port switch or DSL/Cable router applications. 2002/02/9 2

3 3. Block Diagram ENBRDCTRL ENFCTRL ENBKPRS RESET# NWAYHALF# BREF Waveform Shaping Global functions X X2 CK25MUT RXP/N[0] TXP/N[0] 0BASE-T/ 00BASE-TX PHYceiver MAC0 Switch Engine 0 K-entry Look-up Table RXP/N[] TXP/N[] RXP/N[2] TXP/N[2] 0BASE-T/ 00BASE-TX PHYceiver 0BASE-T/ 00BASE-TX PHYceiver MAC MAC2 Switch Engine Switch Engine 2 Packet Buffer Space Page Pointer Space RAMFAL# 6K 6 bits memory RXP/N[3] TXP/N[3] 0BASE-T/ 00BASE-TX PHYceiver MAC3 Switch Engine 3 Buffer Manager RXP/N[] TXP/N[] TXC/RXC TXEN/RXDV TXD/RXD RXC/TXC RXDV/TXEN RXD/TXD CL 0BASE-T/ 00BASE-TX PHYceiver utput M MAC mode M PHY mode Revers circuit MAC Switch Engine LED controller PLNKSTA# PDUPSTA# PSPDSTA# PFLCTRL# SEL_MMAC# ENPLED DS_RST_BLNK# LED_BLNK_TME PMDE[:0] LED_ACT[:0] LED_DUP[:0] LED_SPD[:0] 2002/02/9 3

4 2002/02/9. Pin Assignments LED_SPD[2] LED_ACT[2] LED_DUP[2] LED_SPD[] LED_ACT[] LED_DUP[] LED_SPD[0] LED_ACT[0] BREF A TEST# LED_SPD[] LED_ACT[] LED_DUP[] LED_SPD[3] LED_ACT[3] LED_DUP[3] A RXP[0] RXN[0] R LED_DUP[0] DS_RST_BLNK# RESERVED MTXD[]/MRXD[] MRXD[0]/MTXD[0] MTXD[0]/MRXD[0] ENBRDCTRL NWAYHALF# ENFCTRL LED_BLNK_TME MRXD[3]/MTXD[3] CK25MUT SEL_MMAC# MRXD[2]/MTXD[2] DD MTXD[3]/MRXD[3] MRXC/MTXC MTXD[2]/MRXD[2] MCL MRXDV/MTXEN MRXD[]/MRXD[] M PSPDSTA# PDUPSTA# PLNKSTA# MTXC/MRXC MTXEN/MRXDV X PFLCTRL# X2 RESET# TESTDATA TESTCLK 050A TAWAN 0802T M ENPLED PMDE[0] PMDE[] ENBKPRS T RXN[] RXP[] R T TXP[] TXN[] T T TXN[0] TXP[0] R TXN[3] T T TXN[2] TXP[2] T R RXP[2] RXN[2] R TXP[3] T R RXP[] RXN[] R R RXN[3] RXP[3] R T TXP[] T TXN[] R

5 2002/02/9 5 ' ' stands for inputs; '' stands for outputs; 'A' stands for analog; 'D' stands for digital Name Pin No. Type Name Pin No. Type R T TXP[0] TXN[0] T T TXN[] TXP[] T R RXP[] RXN[] R R RXN[2] RXP[2] R T TXP[2] TXN[2] T T TXN[3] TXP[3] T R RXP[3] RXN[3] R R RXN[] RXP[] R T TXP[] TXN[] T M RESET# TESTCLK TESTDATA X X2 PFLCTRL# PSPDSTA# PDUPSTA# PLNKSTA# MTXC/MRXC MTXEN/MRXDV MTXD[0]/MRXD[0] MTXD[]/MRXD[] MTXD[2]/MRXD[2] MTXD[3]/MRXD[3] MCL MRXC/MTXC MRXDV/MTXEN MRXD[0]/MTXD[0] MRXD[]/MTXD[] M , A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A D D / D D / D / / D D MRXD[2]/MTXD[2] MRXD[3]/MTXD[3] SEL_MMAC# RESERVED CK25MUT NWAYHALF# ENFCTRL ENBKPRS ENBRDCTRL LED_BLNK_TME DS_RST_BLNK# ENPLED, PMDE[] PMDE[0] LED_DUP[0] LED_ACT[0] LED_SPD[0] LED_DUP[] LED_ACT[] LED_SPD[] LED_DUP[2] LED_ACT[2] LED_SPD[2] LED_DUP[3] LED_ACT[3] LED_SPD[3] LED_DUP[] LED_ACT[] LED_SPD[] TEST# A BREF A R RXN[0] RXP[0] D D D D D D D D D D A A A A A A

6 5. Pin Descriptions 5. Media Connection Pins Pin Name Pin No. Type Description Default RXP[:0] RXN[:0],2,5 6,27,28 3,32,27 28 A Differential Receive Data nput TXP[:0] TXN[:0] 3,,7,8 9,20,23 2,35, Mode Pins A Differential Transmit Data utput Pin Name Pin No. Type Description Default ENBKPRS 78 Enable Back Pressure: This pin has no effect on port if it is operated as an M port. : Enable (UTP ports only) 0: Disable ENFCTRL 77 Enable Flow Control: The will advertise its ability with flow control during auto-negotiation. This pin has no effect on port if it is operated as an M port. : Enable Flow control (UTP ports only) 0: Disable ENBRDCTRL 80 Enable Broadcast Control: This is for the UTP and M port. : Enable 0: Disable LED_BLNK_TME 89 LED Blinking Time: This pin controls the blinking speed of the activity and collision LEDs. : 3ms 0: 20ms DS_RST_BLNK# 90 Disable Reset Blinking: This pin controls the blinking of LEDs during reset and power up. Set to 0, the LEDs will not blink on reset or power up. : Enable 0: Disable NWAYHALF# 76 Nway Half Duple: This pin advertises Nway ability to the link partner. Setting this pin to 0 will advertise an Nway ability with 0/00 half duple only. : Nway ability supports full duple 0: Nway ability supports half duple only TEST# 2 Test: An internal test pin 2002/02/9 6

7 5.3 Port Related Pins MRXD[3:0] /MTXD[3:0] Pin Name Pin No. Type Description Default 67,66,63 6 For M MAC mode, these pins are MRXD[3:0], M receive data nibble. For M PHY mode, these pins are MTXD[3:0], M transmit data nibble. For SN PHY mode, MTXD[0] is serial transmit data. MRXDV/MTXEN 60 For M MAC mode, this pin represents MRXDV, M receive data valid. For M PHY mode, this pin represents MTXEN, M transmit enable. MRXC/MTXC 59 / For M MAC mode, it is receive clock, MRXC (acts as input). For M/SN PHY mode, it is transmit clock, MTXC (acts as output). MCL 58 / For M MAC mode, this pin represents collision (acts as input) For M/SN PHY mode, this pin represents collision (acts as output) MTXD[3:0] /MRXD[3:0] 57,56,55 5 For M MAC mode, these pins are MTXD[3:0], M transmit data nibble. For M PHY mode, these pins are MRXD[3:0], M receive data nibble. For SN PHY mode, MRXD[0] is serial receive data. MTXEN/MRXDV 52 For M MAC mode, this pin represents MTXEN, M transmit enable. For M PHY mode, this pin represents MRXDV, M receive data valid. MTXC/MRXC 5 / For M MAC mode, this pin is a transmit clock, MTXC (acts as input). For M/SN PHY mode, this pin is a receive clock, MRXC (acts as output). PMDE[:0] 97,98 Select Port perating Mode: 00: SN PHY mode 0: M PHY mode : UTP / M MAC mode PLNKSTA# 9 Port Link Status: When PMDE[]= (UTP/M MAC mode), this pin decides the link status of the M port. f both UTP and M MAC are linked K, UTP has higher priority. When PMDE[]=0 (PHY mode), this pin decides link status of Port. PDPXSTA# 8 Active Low Duple Status: : Half duple 0: Full duple When P is operated in UTP mode, this pin has no effect. PSPDSTA# 7 Active Low Speed Status: : 0Mbps 0: 00Mbps This pin must be kept floating for the three applications listed below. This is because the speed is either determined by auto-negotiation or fied at M/0M Hz.. For UTP mode, speed is determined by the auto-negotiation procedure. 2. For HomePNA (M MAC mode), speed is determined by RXC and TXC from HomePHY running at Mbps. 3. For SN PHY mode, speed is dedicated to 0MHz clock rate. PFLCTRL# 6 Active Low Flow Control Enable: When P is operated in UTP mode, this pin has no effect. : Disable 0: Enable ENPLED 9 Enable Port LED: n UTP applications, this pin should be floating to drive the LEDs of port. : Drive LED pins of port 0: Tri-state LED pins of port SEL_MMAC# 68 Select M MAC: When PMDE[]=, this pin indicates whether UTP path or M MAC path is selected. : UTP is selected 0: M port is selected While PMDE[]=, the supports UTP/M MAC auto-detect function via the link status of P UTP and the status of PLNKSTA# with priority UTP over M. 2002/02/9 7

8 5. LED Pins Pin Name Pin No. Type Description Default LED_ACT[:0] 9,6 Active low (Link + Activity) LED pins.,08 0 LED_DPX[:0] 8,5 Active low (Fullduple + Collision) LED pins. 0,07 03 LED_SPD[:0] 20,7 3,09 05 Active low Speed00 LED pins. 5.5 Power Pins Pin Name Pin No. Type Description Default T 5,6,2 P 3.3V Analog Transmit Power 22,37 R 3,,29 P 3.3V Analog Receive Power 30,26 A 25 P 3.3V Analog Power M 38 P 3.3V nternal RAM Power 3,53,62 P 3.3V Digital Power 70,87,00 06, R,0,7 P Analog Ground 26,33 T 2,9,8 P Analog Ground 25,3 A 23 P Analog M 6 P nternal RAM 39,50,65 79,9,02 2,22 P Digital 5.6 Miscellaneous Pins Pin Name Pin No. Type Description Default X 25MHz crystal or oscillator clock input X2 5 To crystal input. When using an oscillator this pin should be kept floating. CK25MUT 7 25MHz clock output RESET# 0 Active low reset signal. To complete the reset function, this pin must be asserted for at least 0ms. After reset, about 30ms is needed for the to complete the internal test function and initialization. BREF 2 A Control transmit output waveform Vpp. This pin should be grounded through a.96kω resistor. TESTCLK Test clock TESTDATA 2 / Test data 5.7 Reserved Pins Pin Name Pin No. Type Description Default RESERVED 69 This pin is reserved for internal use and should be left floating. 2002/02/9 8

9 6. Functional Description 6. ntroduction Providing five 0/00 Mbps Ethernet channels and one M port, the can be configured for either a five port 0/00 Ethernet application or a four 0/00 port Ethernet with an etra M/SN port. The M/SN port can be connected to an eternal processor for routing purposes as public area network devices do, referred to as M/SN PHY mode, or connected to a HomePNA physical chip or 00Base-FX PHYceiver, referred to as M MAC mode. n M/SN PHY mode, pins RXC, RXDV, and RXD correspond to TXC, TXEN, and TXD. n M MAC mode, TXC, TXEN and TXD correspond to RXC, RXDV and RXD. The frame buffer is composed of M bits of built-in memory. The address look-up table for MAC addresses learning/searching consists of K direct-mapping entries. The uses Nway auto-negotiation to complete the UTP port connections of physical links which conform to EEE 802.3u specifications. EEE full duple flow control is supported. When operating in half duple mode, a proprietary back-pressure algorithm is implemented to prevent traditional hub devices from partitioning due to ecessive collisions. The supports non-blocking wire speed forwarding rates and special designs to resolve head-of-line blocking problems and channel-capture problems. A broadcast storm filtering function is also provided for abnormal broadcast traffic issues. 6.2 Switch Core Functional verview 6.2. Address Search, Learning and Aging The contains a full K of look-up table entries and uses a direct-mapping scheme to achieve address search and learning. By etracting the least 0 bits of a destination MAC address to inde the K-entry look-up table, the can decide where the packet goes. f the searching result indees to an empty entry, the packet is broadcast to all other ports. n the other hand, the etracts the least 0 bits of a source MAC address to inde the K-entry look-up table. f the result indees to an empty entry, it records the source MAC address and related switching information. f the result leads to an occupied entry with different switching information, it updates the entry with the new information. This is referred to as learning. The look-up engine will update time stamp information of an entry whenever the corresponding source MAC address appears. f the time information is not updated for a period of time, the entry will be removed, referred to as the aging process. The maimum aging time for the is approimately 300 seconds, and the minimum aging time is approimately 200 seconds. 2002/02/9 9

10 6.2.2 Buffer Management The M bit embedded memory buffer is divided into a packet buffer, which is used for data buffering, and a page pointer block (PPB), which is used by the buffer manager. The Packet buffer is constructed of approimately byte pages. Each page includes 8-bytes of header information, which consists of net page pointer, packet byte count, and 28 bytes of data. The linked pages construct a whole received packet which will be forwarded later according to its destination. The buffer manager gets free page pointers from PPB and releases to each port to provide space for incoming packet buffering. When the buffer manager can not support free page pointers any more, it indicates a buffer full condition and flow control or back pressure congestion control is implemented. f no flow control algorithms are activated, packets are dropped. Buffer Manager Page77 Page80 Page77 PTR Free Page Pointers Page80 PTR Page93 PTR Page89 PTR Page89 Free Page Pointer FF Page93 Frame Buffer Data Reception Each port contains a Receive FF for incoming packets, which are from physical medium, and a Free Page Pointer FF for packet buffering indees. Free Page Pointers are obtained from the Buffer Manager. nce a packet is received, it is segmented into 28-byte pieces (as is fit into pages) and then moved into a packet buffer by the Receive DMA Engine with an 8-byte header in every page Data Forwarding Each port contains a Transmit FF, a Transmit Free Page Pointer FF and a Transmit Start Address Queue. The Transmit Free Page Pointer FF stores Free Pages Pointers which have just been released from transmitted packets, and will return these Free Pages to the Buffer Manager for buffering indees of the net incoming packets. The Transmit Start Address Queue keeps the first page pointer of every egress packet, which is from the transmit command issued by the reception port (source port). The destination ports identify every transmit command on the global bus and receive it if they are the outlets. Finally, the Transmit DMA engine of each port starts the DMA to move the pages (which construct a whole packet) to Transmit FF and then to the physical medium. For broadcast packets, it s the duty of the last port which finishes the transmission action last to return the Transmit Free Page Pointers to the Buffer Manager. 2002/02/9 0

11 6.2.5 Flow Control The supports EEE full duple flow control and half duple back-pressure congestion control. nce the full duple flow control ability is enabled via ENFCTRL, the Nway ability with full duple flow control will be negotiated during the auto-negotiation process. When operating in half duple mode, a proprietary back-pressure algorithm is enabled via the ENBKPRS pin, which can prevent traditional hub devices from partition due to ecessive collisions. For M port applications, the same functions will be applied to port depending on the state of PFLCTRL# and PDUPSTA#. f port is not configured to M port application, it acts as a UTP port and behaves according to the configuration of the ENFCTRL and ENBKPRS pins Back-off Algorithm The implements the truncated eponential back-off algorithm compliant to the standard. The collision counter will be reset after 6 consecutive collisions, which leads to a smaller back-off time nter-frame Gap The nter-frame Gap is 9.6us for 0Mbps Ethernet and 960ns for 00Mbps Fast Ethernet llegal Frame llegal frames such as CRC error packets, runt packets ( packet length less than 6 bytes) and oversize packets (packet length greater than 536 bytes) will be discarded Broadcast Storm Control The processes broadcast storm control via the latched value of the EnBrdCtrl pin upon reset. nce enabled, the incoming consecutive broadcast packets will be discarded after consecutive 6 broadcast packets are received during an 800ms time window. Any non-broadcast packets can reset the time window and broadcast counter such that the scheme restarts. 6.3 Physical Layer Functional verview 6.3. Auto-negotiation The obtains the states of duple, speed and flow control ability through the auto-negotiation mechanism, defined in EEE802.3u specifications, for each UTP port. During auto-negotiation, each port advertises its ability to its link partner and compares ability with those received from its link partner. By default, the advertises full capabilities (00Full, 00Half, 0Full, 0Half) together with flow control ability. Asserting NWAYHALF# sets the Nway ability of the to half duple only (00Half, 0Half). Deasserting ENFCTRL sets the Nway ability without the flow control function. ENBKPRS is a pin to enable the half duple flow control scheme, which is defined in auto-negotiation. The M port obtains its duple, speed, flow control and link states from pins as described in section Base-T Transmit Function The output 0Base-T waveform is Manchester-encoded and driven into the network medium. The internal filter shapes the driven signals to reduce EM emission, eliminating the need for an eternal filter Base-T Receive Function The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects that the signal level has eceeded the configured squelch level Link Monitor The 0Base-T link pulse detection circuit always monitors the RXP/RXN pins for the presence of valid link pulses. Auto-polarity is implemented to correct the detected reverse polarity of RXP/RXN signal pairs. 2002/02/9

12 Base-TX Transmit Function The 00Base-TX transmit function performs parallel to serial conversion, B/5B coding, scrambling, NRZ/NRZ conversion, and MLT3 encoding. After B/5B coding, the 5-bit serial data stream is scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such that EM effects can be significantly reduced. The scrambled seed is unique for each port, based on PHY addresses. After scrambling, the bit stream is driven into the network medium in the form of MLT-3 signaling. Multi-level signaling technology moves the power spectrum energy from high frequency to low frequency, which also benefits EM emission issues Base-TX Receive Function The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits, to compensate for the incoming distortion of the MLT-3 signal, MLT-3 to NRZ, NRZ to NRZ converter to convert analog signaling to a digital bit-stream, and a PLL circuit to clock data bits precisely with minimum bit error rate. The de-scrambler, 5B/B decoder and serial-to-parallel conversion circuits follow. Finally, the converted parallel data is fed into the MAC Power Saving Mode The implements power saving mode on per port basis. A port automatically enters power saving mode 0 seconds after the cable is disconnected from it. nce a port enters power saving mode, it transmits normal link pulses only on its TXP/TXN pins and keeps monitoring RXP/RXN to try to detect any incoming signals, which might be a 00Base-TX MLT-3 idle pattern, 0Base-T link pulses or Nway s FLP (Fast Link Pulses). After it detects any incoming signals, it wakes up from the power saving mode and operates in the normal mode according to the result of the connection. 6. LED The supports three parallel LEDs for each port. LED_ACT indicates activity and link status, LED_DPX indicates collision and duple status, and LED_SPD indicates operating speed with state 0 equal to 00Mbps. All LED pins are active low, and blink when presenting activity and collision states. During power-on reset, the supports diagnostics of chip reset and LED functions by blinking all parallel LEDs once. This function can be disabled by asserting DS_RST_BLNK# to 0. LED_BLNK_TME determines LED blinking period for activity and collision, with = 3ms and 0 = 20ms. LEDs corresponding to port can be tri-stated (disable LED functions) for M port applications by pulling ENPLED low. 2002/02/9 2

13 6.5 M Port 6.5. General Description PW ER-N RESET PH Y mode 0 PM D E[] MAC mode SN 0 PM D E[0] UTP M M N UTP LNK N? YES PSPD STA # 0 PLNKSTA# 0 SN PH Y 0M bps (0M Hz) MPH Y 0M bps (2.5M Hz) MPH Y 00M bps (25M Hz) M MAC HomeLAN/00FX (M/2.5M/25MHz) SEL_MMAC#=0 UTP Port 0/00Base-T SEL_MMAC#= The supports an etra M interface for eternal devices. Two modes are implemented on the M port, M/SN PHY mode, and M MAC mode. n M/SN PHY mode, a routing engine can connect ADSL or a cable modem to a LAN through the M port of the. n M MAC mode, other types of LAN medium can be supported such as HomePNA or 00Base-FX via the underlying physical devices through the M port of the. The M signals do not include MTXER,MRXER and MCRS for. MDC/MD signals are also not supplied. Additional pins are used to complete link, speed, duple and flow-control settings described as follows. When port is configured to something other than a UTP port, i.e. M port is activated, four input pins, PLNKSTSA#, PDPXSTA#, PSPDSTA# and PFLCTRL# are provided to determine link, duple, and speed statuses as well as flow control ability similar to force mode. These four pins are active low. f PLNKSTA#=0, the takes the M port as link on, and will forward/receive packets to/from the M port. f PDPXSTA#=0, the takes the M port as full duple, allowing simultaneous T/R. f PSPDSTA#=0, the takes the M port as 00Base-TX, and outputs a 25MHz clock signal from the MTXC and MRXC pins while in M PHY mode. f PSPDSTA#=, it outputs a 2.5MHz clock signal instead. For SN PHY mode (PMDE[]=0, PMDE[0]=0), both MTXC and MRXC are 0MHz clock output signals and PSPDSTA# should be floating. For M MAC mode (PMDE[]=), MTXC and MRXC are clock inputs from the underlying physical device. t is suggested to keep PSPDSTA# floating for SN PHY mode and M MAC mode for HomePNA applications, due to the dedicated speed of these two applications. 2002/02/9 3

14 The other active-low input pin is PFLCTRL#, which determines if flow control algorithm is enabled through the M port. (default PFLCTRL#= ) f PFLCTRL#=0 and PDPXSTA#=0, flow control packets will flow through the M port. f PFLCTRL#=0 and PDPXSTA#=, a back-pressure algorithm will be implemented through the M port. f PFLCTRL#=, no flow control algorithm is performed on the M port. All three input pins, PDPXSTA#, PSPDSTA#, and PFLCTRL#, have no effect when PLNKSTA#=. t is important to note that the MRXD[3:0] pins in M/SN PHY mode are MTXD[3:0] for M MAC mode, and vice versa. Also the same for pin MRXDV vs. MTXEN, and pin MRXC vs. MTXC. NTE: There are no MRXER, MTXER, MCRS and SM (MDC/MD) pins for M signaling. Because of the absence of MCRS, system designers can wire MRXDV directly to CRS and RXDV of the opposite chip. R TL8305S Not Used PMode[] PMode[0] PLnkSta# PSpdSta# PDupSta# PFlCtrl# EnPLed SelMiiMac# 59 MRXC/MTXC 60 MRXDV/MTXEN 67~6 MRXD[3:0]/MTXD[3:0] 5 MTXC/MRXC 52 MTXEN/MRXDV 57-5 MTXD[3:0]/MRXD[3:0] 58 CL Allshould be floating 5 UTP Mode (Default five port switch application) For general cases, most of the option pins should be floating (=High=Enable), ecept EnBrdCtrl. This means that EnBrdCtrl should be pulled down (=Low=Disable) for normal applications. 2002/02/9

15 The illustrations below show a summary of M/SN application circuits for port of the. Note that, as described above, the pins MRXC, MRXDV and MRXD in M/SN PHY mode are pins MTXC, MTXEN and MTXD in M MAC mode, and vice versa. Pull-down=Link n Note Note Note Not used PMode[] PMode[0] PLnkSta# PSpdSta# PDupSta# PFlCtrl# EnPLed SelMiiMac# 5 MTXC/MRXC 52 MTXEN/MRXDV 57-5 MTXD[3:0] /MRXD[3:0] 59 MRXC/MTXC 60 MRXDV/MTXEN 67~6 MRXD[3:0]/MTXD[3:0] 58 CL 25M/2.5MHz M PHY mode RXC CRS RXDV RXD[3:0] TXC TXEN TXD[3:0] CL Routing Engine Pull-down=Link n Floating=0M Note Note Not used PMode[] PMode[0] PLnkSta# PSpdSta# PDupSta# PFlCtrl# EnPLed SelMiiMac# 5 MTXC/MRXC 52 MTXEN/MRXDV 5 MTXD[0]/MRXD[0] 59 MRXC/MTXC 60 MRXDV/MTXEN 6 MRXD[0]/MTXD[0] 58 CL 0MHz RXC CRS RXDV RXD TXC TXEN TXD CL Routing Engine SN PHY mode Pull-down=Link n Used PMode[] PMode[0] PLnkSta# PSpdSta# PDupSta# PFlCtrl# EnPLed SelMiiMac# 59 MRXC/MTXC 60 MRXDV/MTXEN 67~6 MRXD[3:0]/ MTXD[3:0] 5 MTXC/MRXC 52 MTXEN/MRXDV 57-5 MTXD[3:0]/ MRXD[3:0] 58 CL MHz RXC CRS RXDV RXD[3:0] TXC TXEN TXD[3:0] CL HomePHY A M 79C 90A D P8385 M MAC mode (HomePNA Application) Pull-down=Link n Pull-down=00M Note Note Used PMode[] PMode[0] PLnkSta# PSpdSta# PDupSta# PFlCtrl# EnPLed SelMiiMac# 59 MRXC/MTXC 60 MRXDV/MTXEN 67~6 MRXD[3:0]/ MTXD[3:0] 5 MTXC/MRXC 52 MTXEN/MRXDV 57-5 MTXD[3:0]/ MRXD[3:0] 58 CL 25MHz Single PH Y RXC CRS RXDV RXD[3:0] TXC TXEN TXD[3:0] CL Fiber T ransceiber M MAC mode (00Base-FX Application) Note : Floating or Pull-down states depend on application. Note 2: For general cases, most of the option pins should be floating (=High=Enable), ecept for EnBrdCtrl. This means that EnBrdCtrl should be pulled down (=Low=Disable) for normal applications. 2002/02/9 5

16 6.5.2 M/SN PHY Mode n routing applications, the cooperates with a routing engine to communicate with a WAN (Wide Area Network) through M/SN. n such applications, PLNKSTA# =0 and PMDE[] are pulled low upon power-on reset. PMDE[0] determines whether M or SN mode is selected. n M (nibble) mode (PMDE[0]=), PSPDSTA# =0 results in M operating at 00Mbps with MTXC and MRXC running at 25MHz; however, PSPDSTA#= leads to M operating at 0Mbps with MTXC and MRXC running at 2.5MHz. n SN (serial) mode (PMDE[0]=0), PSPDSTA# has no effect and must be floating. SN mode operates at 0Mbps only, with MTXC and MRXC running at 0MHz. n SN mode, does not loopback RXDV signals as a response to TXEN and does not support heart-beat functions (asserting the CL signal for each complete TXEN signal). By pulling-up ENPLED (internal default =), the displays the M/SN status through LEDs of port, such as activity/link, collision/duple, and speed M MAC Mode n HomePNA/00Base-FX applications, the provides the M interface to the underlying HomePNA or 00Base-FX related physical devices to communicate with other types of LAN medium. n such applications, PMDE[] is pulled high upon power-on reset and the supports the UTP/M auto-detection function. When both UTP and M are active (link on), the UTP port has a higher priority over the M port. n HomePNA applications, PSPDSTA# must be floating and, since HomePNA is half-duple only, PDPXSTA# should be floating as well. t is recommend to pull PLNKSTA# low instead of being wired to the LNK LED pin of the HomePHY because of the unstable link state of the HomePHY configuration, which is a characteristic based on the HomePNA.0 standard. For 00Base-FX applications, PLNKSTA# =0, PSPDSTA# =0 and PDPXSTA# depends on the application. By pulling-up ENPLED (internal default =), the displays the M status through the LEDs of port, such as activity/link, collision/duple, and speed. Pin SEL_MMAC# can be used to indicate that the M MAC port is active by a LED for the sake of UTP/M auto-detection. Finally, a 25MHz clock output (CK25MUT) can be used as a clock source for the underlying HomePHY/00Base-FX physical devices. 2002/02/9 6

17 A brief application for HomePNA and 00Base-FX is depicted below. 3.3V 3.3V 3.3V PMDE[] PMDE[0] LEDACT[] LEDDPX[] LEDSPD[] 3.3V CK25MUT PLNKSTA# PSPDSTA# PDPXSTA# PFLCTRA# SEL_MMAC# ENPLED M HomePHY LED_LNK# LED_ACT# LED_CL# LED_SPD# Common LEDs ( driving) M MAC mode (UTP / HomeLAN auto-detect) 3.3V 3.3V 3.3V PMDE[] PMDE[0] LEDACT[] LEDDPX[] LEDSPD[] 3.3V CK25MUT PLNKSTA# PSPDSTA# PDPXSTA# PFLCTRA# SEL_MMAC# ENPLED M Single PHY LED_LNK# LED_ACT# LED_CL# LED_SPD# TD+/- SD+/- RD+/- Fiber Transceiver Common LEDs ( driving) M MAC mode (UTP / 00Base-FX auto-detect) As illustrated above, PLNKSTA# needs to be pulled low to enable the M MAC port, accompanied with PMDE[] pulled high. An LED connected to SEL_MMAC# pin can indicate whether the UTP or M port is selected. For 00Base-FX applications, the Link LED status pin can even be wired to PLNKSTA# to implement the UTP/M auto-detection feature with no need to permanently disable port UTP capabilities. For the, UTP priority takes over the M port if both are link on. 2002/02/9 7

18 7. Electrical Characteristics 7. Absolute Maimum Ratings WARNNG: Absolute maimum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. All voltages are specified reference to unless otherwise specified. Parameter Min Ma Units Storage Temperature C Vcc Supply Referenced to V Digital nput Voltage -0.5 Vcc V DC utput Voltage -0.5 Vcc V 7.2 perating Range Parameter Min Ma Units Ambient perating Temperature(Ta) C Vcc Supply Voltage Range(Vcc) V 7.3 DC Characteristics (0 C<Ta<60 C, 3.5V<Vcc<3.5V) Parameter SYM Conditions Min Typical Ma Units Power Supply Current cc 0 Base-T, idle 0 Base-T, Peak continuous 00% utilization 00 Base-TX, idle 00 Base-TX, Peak continuous 00% utilization 0/00 Base-TX, low power without cable ma Power Consumption PS 0 Base-T, idle 0 Base-T, Peak continuous 00% utilization 00 Base-TX, idle 00 Base-TX, Peak continuous 00% utilization 0/00 Base-TX, low power without cable TTL nput High Voltage V ih 2.0 V TTL nput Low Voltage V il 0.8 V TTL nput Current in µa TTL nput Capacitance C in 5 pf utput High Voltage V oh Vcc-0. V utput Low voltage V ol 0. V LED utput Current oh 33 ma W 2002/02/9 8

19 Parameter Symbol Conditions Min Typical Ma Units utput Tristate Leakage Current Z 0 µa Transmitter, 00Base-TX (: Transformer Ratio) TX+/- utput Current High H 0 ma TX+/- utput Current Low L 0 ua Transmitter, 0Base-T (: Transformer Ratio) TX+/- utput Current High H 00 ma TX+/- utput Current Low L 0 µa Transmitter, 00Base-TX (.25: Transformer Ratio) TX+/- utput Current High H 32 ma TX+/- utput Current Low L 0 µa Transmitter, 0Base-T (.25: Transformer Ratio) TX+/- utput Current High H 80 ma TX+/- utput Current Low L 0 µa Receiver, 00Base-TX RX+/- Common-mode input voltage.32 V RX+/- Differential input resistance 20 KΩ Receiver, 0BaseT Differential nput Resistance 20 kω nput Squelch Threshold 30 mv 7. AC Characteristics (0 C<Ta<60 C, 3.5V<Vcc<3.5V) Parameter Symbol Conditions Min Typical Ma Units Transmitter, 00Base-TX Differential utput Voltage, V D 50Ω from each output to Vcc, Best-fit over.968 V peak-to-peak bit times Differential utput Voltage V S 50Ω from each output to Vcc, Vp+ / Vp- % Symmetry Differential utput vershoot V Percent of Vp+ or Vp % Rise/Fall time t r,t f 0-90% of Vp+ or Vp ns Rise/Fall time imbalance t r - t f ps Duty Cycle Distortion Deviation from best-fit time-grid, ±75 ±200 ps Sequence Timing jitter dle pattern ns Transmitter, 0Base-T Differential utput Voltage, V D 50Ω from each output to Vcc, all pattern V peak-to-peak TP_DL Silence Duration Period of time from start of TP_DL to link ms pulses or period of time between link pulses TD Short Circuit Fault Peak output current on TD short circuit for 52 ma Tolerance 0 seconds TD Differential utput Return loss from 5MHz to 0MHz for 26 0 db mpedance (return loss) reference resistance of 00 Ω TD Common-Mode utput Voltage Ecm Terminate each end with 50Ω resistive load mv Transmitter utput Jitter.5 ns RD Differential utput Return loss from 5MHz to 0MHz for 35 db mpedance (return loss) reference resistance of 00 Ω Harmonic Content db below fundamental, 20 cycles of all db ones data Start-of-idle Pulse width TP_DL width ns 2002/02/9 9

20 7.5 Digital Timing Characteristics Parameter Symbol Conditions Min Typical Ma Units 00Base-TX Transmit System Timing Active TX_EN Sampled to first Bits bit of J on MD output nactive TX_EN Sampled to Bits first bit of T on MD output TX Propagation Delay t TXpd From TXD[:0] to TXP/N Bits 00Base-TX Receive System Timing First bit of J on MD input to From RXP/N to CRS_DV 6 8 Bits CRS_DV assert First bit of T on MD input to From RXP/N to CRS_DV 6 8 Bits CRS_DV de-assert RX Propagation Delay t RXpd From RXP/N to RXD[:0] 5 7 Bits 0Base-T Transmit System Timing TX Propagation Delay t TXpd From TXD[:0] to TXP/N 5 6 Bits TXEN to MD output From TXEN assert to TXP/N 5 6 Bits 0Base-T Receive System Timing Carrier Sense Turn-on delay t CSN Preamble on RXP/N to CRS_DV asserted 2 Bits Carrier Sense Turn-off Delay t CSFF TP_DL to CRS_DV de-asserted 8 9 Bits RX Propagation Delay t RXpd From RXP/N to RXD[:0] 9 2 Bits LED Timing LED n Time t LEDon While LED blinking 3 ms LED ff Time t LEDoff While LED blinking 3 ms Jabber Timing (0Base-T only) Jabber Active From TXEN= to Jabber asserted ms Jabber de-assert From TXEN=0 to Jabber de-asserted ms 7.6 Thermal Data Parameter Symbol Conditions Min Typical Ma Units Thermal resistance: junction to θja layers PCB, ambient temperature 25 C 2 C/W ambient, 0 ft/s airflow Thermal resistance: junction to case, 0 ft/s airflow θjc layers PCB, ambient temperature 25 C 3.9 C/W 2002/02/9 20

21 8. Application nformation UTP (0Base-T/00Base-TX) Application RXP 50Ω % Pulse H053 Transformer : RJ5 RXN 50Ω % 0.uF A V 3.3V 5 TXP 50Ω % : 6 7 TXN 50Ω % 8 0.uF BREF A 75Ω 3.96ΚΩ, % A 0.uF/3KV UTP Application Chasis 2002/02/9 2

22 9. System Application Diagram 5X Transformer X Transformer Fiber interface 0/00Mbps 5 UTP 0/00Mbps UTP 00Base-FX Routing Engine X Transformer HomePNA device X Transformer ADSL/ Cable modem 0/00Mbps UTP HomeLAN 0/00Mbps UTP WAN 2002/02/9 22

23 0. Mechanical Dimensions Symbol Dimension in inch Dimension in mm. Dimension D & E do not include interlead flash. Min Typical Ma Min Typical Ma 2. Dimension b does not include dambar protrusion/ A intrusion. A Controlling dimension : Millimeter A General appearance spec. should be based on final b visual inspection spec. c D TTLE : 28 QFP (20 mm ) PACKAGE UTLNE E CU L/F, FTPRNT 3.2 mm e LEADFRAME MATERAL : HD APPRVE DC. N. 530-ASS-P00 HE VERSN L PAGE F L CHECK DWG N. Q28 - y DATE ct θ REALTEK SEMCNDUCTR C., LTD 2002/02/9 23

24 Document Revision nformation Revision Date Change.00 0/0/2000 riginal document..0 0/05/2000 Add system application diagram. P /06/2000 Add power consumption. P /5/2000 Rename TX+/- to TXP/N and RX+/- to RXP/N. P.5 Add pull-up 3.3V on resistors of TXP/N. P.9.0 /20/2000 Update power consumption, Power Supply Current P.20 Update AC characteristics.05 /29/2000 Clarify Port diagram and function. P., P /05/2000 Clarify Pin assignment, Port diagram and function. P.5, P /06/2000 Update Maimum legal frame size 728 as 536. Update Port diagram and function. P.2, P.6, P /08/2000 Update Thermal Theta JA & Theta JC. P /8/2000 Add figure. Update figure note. P.5, P.6.0 2/22/2000 Revise 8k as k. P.0. 0//200 Revise pin name as TEST# on P.5, P.6, P.7 Revise range of Storage Temperature on P.2. Revise Ta from 70 degree C to 60 degree C on P.2 and P /9/200 Revise aging time 300sec as Ma 300 sec, Min 200 sec on P.0.3 0/29/200 t is no recommended to use internal power on auto reset on P. P.8. 02/3/200 Clarify NwayHalf# pin description on P /6/200 Clarify PLNKSTA# pin description on P.7 Clarify SEL_MMAC# pin description on P /9/200 Clarify Features description on P..7 05//200 Clarify general description on P. Change Picture tem color on P /9/2002 General English adjustment. Realtek Semiconductor Corp. Headquarters F, No. 2, ndustry East Road X, Science-based ndustrial Park, Hsinchu, 300, Taiwan, R..C. Tel: Fa: WWW: /02/9 2