Am79C875. NetPHY -4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION

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1 PRELIMINARY Am79C875 NetPHY -4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver DISTINCTIVE CHARACTERISTICS Four 10/100BASE-TX Ethernet PHY transceivers Supports RMII (Reduced MII) interface 125 meter (m) MLT-3 and Baseline Wander operation Low power consumption 1.3 Watt (W) typical (1:1 magnetics) 1.2 W typical (1.25:1 magnetics) Power management modes: Selectable 1:1 or 1.25:1 transmit transformer Unplugged - approximately 100 mw per port Power Down - approximately 3 mw per port Single 3.3 V power supply with 5 V I/O tolerance Patent-pending DC restoration technique reduces baseline wander susceptibility Full and half-duplex operation with full-featured Auto-Negotiation function Next Page register support Automatic Polarity Detection during Auto- Negotiation and 10BASE-T signal reception Unique scramble seed per port reduces EMI in switch and repeater applications One port supports 100BASE-FX function Supports Inter Packet Gap as low as 40 ns for high throughput applications No external filters or chokes required Compliant with IEEE standards for 100BASE-TX, 100BASE-FX, and 10BASE-T Built-in loopback and test modes Small 14 x 20 mm 100-pin PQR package Small package allows side-by-side PHY layout Fits neatly behind quad magnetics Saves board space over larger 208 PQFP packages Support for Industrial Temperature (-40 C to +85 C) GENERAL DESCRIPTION The NetPHY-4LP device is a highly integrated, low power 10BASE-T/100BASE-TX/FX Quad Ethernet transceiver. The NetPHY-4LP device includes integrated RMII, ENDECs, Scrambler/Descrambler, and full-featured Auto-Negotiation with support for Parallel Detection and Next Page. Port 3 can be configured as a 100BASE-FX transmitter to output an NRZI PECL level signal. Each receiver has an adaptive equalizer/ DC restoration circuit for accurate clock/data recovery on the 100BASE-TX signal at different cable lengths and can perform to 125 m and beyond. The NetPHY-4LP device operates on a 3.3 V supply and offers 5 V I/O tolerance for mixed signal designs. Power consumption is 1.3 W typical for the device, or 0.3 W per port using 1:1 magnetics. The NetPHY-4LP device can use 1.25:1 magnetics, which decreases transmit power consumption and reduces device power consumption to 1.2 W typical. The NetPHY-4LP device offers an optimized pinout for network applications. RMII pins can be routed directly to the MAC and TX/RX media pins are routed directly to the magnetics. Direct routing of high speed traces is imperative for project system design and EMI noise reduction. The NetPHY-4LP device s on-chip input filtering and output waveshaping eliminates the need of external hybrid filters for media connection. Integrated LED logic allows three LEDs per port to be driven directly. These features greatly simplify the design of a 100BASE-X repeater/switch board, thus requiring minimum external components. For ease of system and chip setup and testing, the Net- PHY-4LP device offers loopback and various advanced testing and monitoring capabilities. The NetPHY-4LP device is available in the Commercial (0 C to 70 C) or Industrial (-40 C to +85 C) temperature ranges. The Industrial temperature range is well suited to environment such as enclosures with restricted air flow or outdoor equipment. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# Rev: G Amendment/0 Issue Date: April 2001 Refer to AMD s Website ( for the latest information.

2 BLOCK DIAGRAM (PER PORT) RMII Data Interface Interface PCS Framer Carrier Detect 4B/5B PMA Clock Recovery Link Monitor Signal Detect 25 MHz TP_PMD MLT-3 BLW Stream Cipher 10TX 100TX 100RX Mux TX+ TX- MAC 10BASE-T 10RX RX+ Transformer MDC/MDIO Control/Status 20 MHz RX- RX FLP MII Serial Management Interface and Registers PLL Clk Generator Test LED Control 25 MHz Auto- Negotiation PHYAD[4:0] REFCLK TEST [3:0] LED Drivers 22236G-1 2 Am79C875

3 Am79C875 3 P R E L I M I N A R Y CONNECTION DIAGRAM RX[0]- RX[0]+ AGND AGND TX[0]+ TX[0]- AVDD AVDD TX[1]- TX[1]+ AGND AGND RX[1]+ RX[1]- AVDD AVDD RX[2]- RX[2]+ AGND AGND TX[2]+ TX[2]- AVDD AVDD TX[3]- TX[3]+ AGND AGND RX[3]+ RX[3] OVDD RXD[0]_[0] RXD[0]_[1] CVDD TX_EN[1] TXD[1]_[0] TXD[1]_[1] CGND OGND CRS_DV[1] RX_ER[1] RXD[1]_[0] RXD[1]_[1] CVDD REFCLK MDC MDIO TX_EN[2] OVDD TXD[2]_[0] TXD[2]_[1] CGND CRS_DV[2] RX_ER[2] RXD[2]_[0] RXD[2]_[1] CVDD TX_EN[3] OGND TXD[3]_[0] AVDD GAVDD GAVDD IBREF GAGND RST INTR LEDSPD[0]/TP1_1 LEDACT_LINK[0] LEDDPX[0]/FX_DIS LEDSPD[1]/PHYAD[2] LEDACT_LINK[1]/PHYAD[3] LEDDPX[1]/PHYAD[4] OGND TX_EN[0]/MII_CRS[0] TXD[0]_[0] TXD[0]_[1] CGND CRS_DV[0] RX_ER[0] AVDD SDI+/TEST[0] SDI-/TEST[1] FXR+/TEST[2] FXR-/TEST[3] FXT+ FXT- LEDDPX[3]/SCRAM_EN LEDACT_LINK[3]/ANEGA LEDSPD[3]/BURN_IN LEDDPX[2]/DPLX LEDACT_LINK[2] LEDSPD[2]/FORCE100 OVDD RXD[3]_[1] RXD[3]_[0] RX_ER[3]/PHYAD_ST CRS_DV[3] CGND TXD[3]_[1] AM79C875 NetPHY-4LP 22236G-2

4 LOGIC SYMBOL OVDD CVDD AVDD GAVDD PHY Control and LEDs REFCLK RST INTR LEDDPX[0]/FX_DIS LEDACT_LINK[0]/CIM_DIS LEDSPD[0]/TP1_1 LEDDPX[1]/PHYAD[4] LEDACT_LINK[1]/PHYAD[3] LEDSPD[1]PHYAD[2] LEDDPX[2]/DPLX LEDACT_LINK[2] LEDSPD[2]/FORCE100 LEDDPX[3]/SCRAM_EN LEDACT_LINK[3]/ANEGA LEDSPD[3]/BURN_IN IBREF Am79C875 NetPHY-4LP TXD[0]_[1:0] TXD[1]_[1:0] TXD[2]_[1] TXD[2]_[0] TXD[3]_[1] TXD[3]_[0] TX_EN[3:0] RXD[0]_[1:0] RXD[1]_[1:0] RXD[2]_[1:0] RXD[3]_[1:0] RX_ER[0] RX_ER[2:1] RX_ER[3]/PHYAD_ST CRS_DV[3:0] MDC MDIO TX+/-[3:0] RX+/-[3:0] SDI+/TEST[0] SDI-/TEST[1] FXT+/- FXR+/TEST[2] FXR-/TEST[3] RMII Ports Management Port Physical Data Transceiver 22236G-3 OGND CGND AGND GAGND 4 Am79C875

5 ORDERING INFORMATION Standard Products P R E L I M I N A R Y AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. AM79C875 K C/I ALTERNATE PACKAGING OPTION TEMPERATURE RANGE C = Commercial (0 C to +70 C) I = Industrial (-40 C to +85 C) PACKAGE TYPE K = 100-Pin Plastic Quad Flat Pack (PQR100) SPEED OPTION Not Applicable DEVICE NUMBER/DESCRIPTION AM79C875 NetPHY-4LP Low Power Quad 10/100-TX/FX Ethernet Transceiver Valid Combinations AM79C875 KC AM79C875 KI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am79C875 5

6 RELATED AMD PRODUCTS Part No. Description Controllers Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE ) Integrated Controllers Am79C940 Media Access Controller for Ethernet (MACE ) Am79C961A PCnet-ISA II Full Duplex Single-Chip Ethernet Controller for ISA Bus Am79C965 PCnet-32 Single-Chip 32-Bit Ethernet Controller for 486 and VL Buses Am79C970A PCnet-PCI II Full Duplex Single-Chip Ethernet Controller for PCI Local Bus Am97C973/975 PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY Am79C976 PCnet-PRO PCnet-PRO 10/100 Mbps PCI Ethernet Controller Am79C978 PCnet -Home Single-Chip 1/10 Mbps PCI Home Networking Controller Physical Layer Devices (Single-Port) Am79C874 NetPHY -1LP Low Power 10/100-TX/FX Ethernet Transceiver Am79C901 HomePHY Single-Chip 1/10 Mbps Home Networking PHY Integrated Repeater/Hub Devices Am79C984A Enhanced Integrated Multiport Repeater (eimr ) Am79C985 Enhanced Integrated Multiport Repeater Plus (eimr+ ) 6 Am79C875

7 TABLE OF CONTENTS P R E L I M I N A R Y DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM (PER PORT) CONNECTION DIAGRAM LOGIC SYMBOL ORDERING INFORMATION Standard Products (/$7('$0'352'8&76 PIN DESIGNATIONS PIN DESCRIPTIONS Media Connections BASE-FX Function/Test Clock RMII Signals LED Port Bias Power and Ground FUNCTIONAL DESCRIPTION Overview Modes of Operation BASE-X Block BASE-T Block Auto-Negotiation and Miscellaneous Functions Loopback Operation Power Savings Mechanisms LED Port Configuration PHY Control and Management Block (PCM Block) ABSOLUTE MAXIMUM RATINGS Operating Ranges DC CHARACTERISTICS Power Supply Current Consumption :,7&+,1*:$9()2506 Key to Switching Waveforms SWITCHING CHARACTERISTICS System Clock Signal MLT-3 Signals MII Management Signals Independent RMII Mode Signals PHYSICAL DIMENSIONS PQR100 (measured in millimeters) (9,6,216800$5< Revision C to D Revision D to E Revision E to F Revision F to G Am79C875 7

8 LIST OF FIGURES Figure Mbps Reception with No Errors Figure Mbps Reception with False Carrier Figure Mbps Transmission Figure 4. Bit Ordering Figure 5. 10BASE-T Transmit/Receive Data Paths Figure 6. MLT-3 Waveform Figure 7. TX± and RX± Termination for 100BASE-TX and 10BASE-T Figure 8. LED Port Configuration Figure 9. PHY Management Read and Write Operations Figure 10. MLT-3 Receive Input Figure 11. MLT-3 and 10BASE-T Test Load with 1:1 Transformer Ratio Figure 12. MLT-3 and 10BASE-T Test Load with 1.25:1 Transformer Ratio Figure 13. Near-End 100BASE-TX Waveform Figure 14. Near-End 10BASE-T Waveform Figure 15. Recommended PECL Test Loads Figure 16. Clock Signal Figure 17. MLT-3 Test Waveform Figure 18. Management Bus Transmit Timing Figure 19. Management Bus Receive Timing Figure 20. RMII 100 Mbps Transmit Start of Packet Figure 21. RMII 100 Mbps Transmit End of Packet Timing Figure Mbps RMII Receive Start of Packet Timing Figure Mbps RMII Receive End of Packet Timing Figure 24. RMII 10 Mbps Transmit Start of Packet Figure 25. RMII 10 Mbps Transmit End of Packet Timing Figure Mbps RMII Receive Start of Packet Timing Figure Mbps RMII Receive End of Packet Timing LIST OF TABLES Table 1. Code-Group Mapping Table 2. LED Display Configuration Table 3. Clause 22 Management Frame Format Table 4. PHY Address Setting Frame Structure Table 5. NetPHY-4LP MII Management Register Set Table 6. Legend for Register Tables Table 7. MII Management Control Register (Register 0) Table 8. MII Management Status Register (Register 1) Table 9. PHY Identifier 1 Register (Register 2) Table 10. PHY Identifier 2 Register (Register 3) Table 11. Auto-Negotiation Advertisement Register (Register 4) Table 12. Auto-Negotiation Link Partner Ability Register in Base Page Format (Register 5)..29 Table 13. Auto-Negotiation LInk Partner Ability Register in Next Page Format (Register 5)...29 Table 14. Auto-Negotiation Expansion Register (Register 6) Table 15. Auto-Negotiation Next page Advertisement Register (Register 7) Table 16. Miscellaneous Features Register (Register 16) Table 17. Interrupt Control/Status Register (Register 17) Table 18. Diagnostic Register (Register 18) Table 19. Test Register (Register 19) Table 20. Miscellaneous Features 2 Register (Register 20) Table 21. Receive Error Counter (Register 21) Table 22. Mode Control Register (Register 24) Am79C875

9 PIN DESIGNATIONS Listed by Pin Number Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 RX[0]- 26 TX[3]+ 51 TXD[3]_[0] 76 TX_EN[1] 2 RX[0]+ 27 AGND 52 OGND 77 CVDD 3 AGND 28 AGND 53 TX_EN[3] 78 RXD[0]_[1] 4 AGND 29 RX[3]+ 54 CVDD 79 RXD[0]_[0] 5 TX[0]+ 30 RX[3]- 55 RXD[2]_[1] 80 OVDD 6 TX[0]- 31 AVDD 56 RXD[2]_[0] 81 RX_ER[0] 7 AVDD 32 SDI+/TEST[0] 57 RX_ER[2] 82 CRS_DV[0]/ 8 AVDD 33 SDI-/TEST[1] 58 CRS_DV[2] 83 CGND 9 TX[1]- 34 FXR+/TEST[2] 59 CGND 84 TXD[0]_[1] 10 TX[1]+ 35 FXR-/TEST[3] 60 TXD[2]_[1] 85 TXD[0]_[0] 11 AGND 36 FXT+ 61 TXD[2]_[0] 86 TX_EN[0] 12 AGND 37 FXT- 62 OVDD 87 OGND 13 RX[1] RX[1] AVDD 40 LEDDPX[3]/ SCRAM_EN LEDACT_LINK[3]/ ANEGA LEDSPD[3]/ BURN_IN 63 TX_EN[2] MDIO MDC 90 LEDDPX[1]/ PHYAD[4] LEDACT_LINK[1]/ PHYAD[3] LEDSPD[1]/ PHYAD[2] 16 AVDD 41 LEDDPX[2]/DPLX 66 REFCLK 91 LEDDPX[0]/FX_DIS 17 RX[2]- 42 LEDACT_LINK[2] 67 CVDD 92 LEDACT_LINK[0] 18 RX[2]+ 43 LEDSPD[2]/ FORCE RXD[1]_[1] 93 LEDSPD[0]/TP1_1 19 AGND 44 OVDD 69 RXD[1]_[0] 94 INTR 20 AGND 45 RXD[3]_[1] 70 RX_ER[1] 95 RST 21 TX[2]+ 46 RXD[3]_[0] 71 CRS_DV[1] 96 GAGND 22 TX[2]- 47 RX_ER[3]/ PHYAD_ST 72 OGND 97 IBREF 23 AVDD 48 CRS_DV[3] 73 CGND 98 GAVDD 24 AVDD 49 CGND 74 TXD[1]_[1] 99 GAVDD 25 TX[3]- 50 TXD[3]_[1] 75 TXD[1]_[0] 100 AVDD Am79C875 9

10 PIN DESCRIPTIONS Media Connections TX[3:0] Transmit Output Output The TX[3:0] pins are the differential transmit output pairs. The TX[3:0] pins transmit 10BASE-T or MLT-3 signals depending on the state of the link of the port. RX[3:0] Receive Input Input The RX[3:0] pins are the differential receive input pairs. The RX[3:0] pins can receive 10BASE-T or MLT-3 signals depending on the state of the link of the port. 100BASE-FX Function/Test SDI+/TEST[0] Signal Detect Input+ (For Port 3 only) Analog Input/Output This pin indicates signal quality status on the fiber-optic link in 100BASE-FX mode. When the signal quality is good, the SDI+ pin should be driven high relative to the SDI- pin. 100BASE-FX is disabled when both pins are simultaneously pulled low. SDI- can also be used for Signal Detect Common Mode Voltage input. When in test mode, SDI+, SDI-, FXR+, and FXR- pins are used as TEST[3:0]. SDI-/TEST[1] Signal Detect Input- (For Port 3 only) Analog Input/Output This pin indicates signal quality status on the fiber-optic link in 100BASE-FX mode. When the signal quality is good, the SDI+ pin should be driven high relative to the SDI- pin. 100BASE-FX is disabled when both pins are simultaneously pulled low. SDI- can also be used for Signal Detect Common Mode Voltage input. When in test mode, SDI+, SDI-, FXR+, and FXR- pins are used as TEST[3:0]. FXR+/TEST[2] Fiber Receive Input (For Port 3 only) Analog Input/Output When Port 3 is configured as FX Channel, FXR± are ECL level FX receive pins. When in test mode, SDI±, and FXR± pins are used as TEST[3:0]. FXR-/TEST[3] Fiber Receive Input (For Port 3 only) Analog Input/Output When Port 3 is configured as FX Channel, FXR± are ECL level FX receive pins. When in test mode, SDI+, SDI-, FXR+, FXR- pins are used as TEST[3:0]. FXT± Fiber Transmit Output (For Port 3 only) Analog Output When Port 3 is configured as FX Channel, FXT± are ECL level FX transmit pins. Clock REFCLK Reference Clock Input Signal Input The REFCLK pin is the reference clock input. The REF- CLK signal must be a 50-MHz signal. RMII Signals TXD[3:0]_[1:0] RMII TXD for Ports 0 to 3 Input These pins are the transmit data input to the RMII of Ports 0:3. TX_EN[3:0] RMII Transmit Enable Input These pins are the transmit enable inputs to the RMII. RXD[3:0]_[1:0] RMII Receive Data for Ports 0 to 3 Output These pins are the receive data for Port 0:3. RX_ER[2:0] RMII Receive Error for Ports 0 to 2 Output These pins indicate receive errors for the corresponding port. The pin goes HIGH whenever the corresponding receiver detects a symbol error. RX_ER[3]/PHYAD_ST RMII Receive Error for Port 3 Input/Output PHY Address Shift This pin indicates receive errors for Port 3. It goes HIGH when the corresponding receiver detects a symbol error. At power up, this pin is used to set the PHY address by increasing it by 1. If it is HIGH at power up, the PHYAD of each port is the upper-3 bits and the port number for the lower-2 bits. If it is LOW, the PHYAD is incremented by 1. For example, if the pin is HIGH at power-up and the upper-3 bits are set to 000, the PHYAD of each port (in binary notation) is 00000, 00001, 00010, respectively. If the pin is LOW at power-up and the upper- 3 bits are set to 000, the PHYAD of each port is 00001, 00010, 00011, and 00100, respectively. This allows a method of avoiding setting an address to 00000, which could cause problems with some MACs. CRS_DV[3:0] Carrier Sense/Data Valid Input/Output, Pull-Down The CRS_DV pin is asserted high when media is non-idle. 10 Am79C875

11 MDIO Management Data I/O Input/Output, Pull-Down This pin is a bidirectional data interface used by the MAC to access management register within the Net- PHY-4LP device. This pin has an internal pull-down, therefore, it requires an external pull-up resistor (1.5 kw) as specified in IEEE section 22. MDC Management Data Clock Input, Pull-Down This pin is the serial management clock which is used to clock MDIO data to the MAC. RST Reset Input, Pull-Up An active low input will force the NetPHY-4LP device to a known reset state. Reset also can be done through the internal power-on-reset or MII Register 0, bit 15. INTR Interrupt Tri-State This pin is true whenever the NetPHY-4LP device detects an event flagged as an interrupt. Events to be flagged are programmed in Register 17. Interrupts are cleared on Read. The polarity of INTR (active HIGH or active LOW) is set by Register 16, bit 14. The default is active LOW, which requires a 10 kw pull-up resistor. LED Port Note: Consult the LED Port Configuration section for appropriate pull-up and pull-down resistors. LEDDPX[0]/FX_DIS Port [0] Duplex LED Input/Output, Pull-Up Low LED indicates full-duplex and high indicates halfduplex. FX Mode: Pulled low at reset will put Port 3 in 100BASE-FX mode. LEDACT_LINK[0] Port [0] Transmit/Receive Activity LED Output, Pull-Up LED is output low for approximately 30 ms each time there is activity. LINK is an active low signal. If not used, this signal should have a kw pull-up resistor. LEDSPD[0]/TP1_1 Port [0] Speed LED Input/Output, Pull-Up LED is output low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. TP1_1: Pulled low at reset will select transmit transformer ratio to be 1.25:1. Default is 1:1 transformer. LEDDPX[1]/PHYAD[4] Port [1] Duplex LED Input/Output, Pull-Up LED low indicates full-duplex and high indicates halfduplex. PHY Address[4]. This is the first address bit received in the management frame, and one of three MSBs for MII management PHY address. The two LSBs, PHYAD [1:0] are internally wired to four ports: PHYAD [11]=Port3,..., PHYAD [00] = Port0. The PHYAD will also determine the scramble seed, this will help to reduce EMI when there are multiple ports switching at the same time. To set this pin, use pull-up or pull-down resistors in the range of 1 KW to 4.7 KW. LEDACT_LINK[1]/PHYAD[3] Port [1] Transmit/Receive Activity LED Input/Output, Pull-Up LED is output low for approximately 30 ms each time there is activity. LINK is an active low signal. PHY Address[3]. This is the second MSB and one of three MSB s for MII management PHY address. To set this pin, use pull-up or pull-down resistors in the range of 1 KW to 4.7 KW. LEDSPD[1]/PHYAD[2] Port [1] Speed LED Input/Output, Pull-Up LED is output low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. PHY Address[2]. This is the third MSB and one of three MSB s for MII management PHY address. To set this pin, use pull-up or pull-down resistors in the range of 1 KW to 4.7 KW. LEDDPX[2]/DPLX Port [2] Duplex LED Input/Output, Pull-Up LED low indicates full-duplex and high indicates halfduplex. DPLX: Full Duplex Mode Enable. This pin is logically OR ed with a full-duplex enable MII control bit to generate an internal full-duplex enable signal. When asserted high, the NetPHY-4LP device operates in fullduplex mode as determined through Auto-Negotiation or software setting. When asserted low, the internal control bit (Register 0, bit 8) will determine the full-duplex operating mode. LEDACT_LINK[2] Port [2] Transmit/Receive Activity LED Output, Pull-Up LED is output low for approximately 30 ms each time there is activity. LINK is an active low signal. If not used, this signal should have a 10-kW pull-up. LEDSPD[2]/FORCE100 Port [2] Speed LED Input/Output, Pull-Up LED is output low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. FORCE100: Force 100BASE-X Operation. When this signal is pulled high and ANEGA is low at reset, all ports will be forced to 100BASE-TX operation. When asserted low and ANEGA is low, all ports are forced to Am79C875 11

12 10BASE-T operation. When ANEGA is high, FORCE100 has no effect on operation. LEDDPX[3]/SCRAM_EN Port [3] Duplex LED Input/Output, Pull-Up LED low indicates full-duplex and high indicates halfduplex. SCRAM_EN. Scrambler Enable. Pulled low at reset will bypass the scrambler. Default is scrambler enabled. If not used, this signal should have a kw pull-up resistor LEDACT_LINK[3]/ANEGA Port [3] Transmit/Receive Activity LED Input/Output, Pull-Up LED is low for approximately 30 ms each time there is activity. LINK is an active low signal. ANEGA: Auto-Negotiation Ability. Asserted high means Auto-Negotiation enable while low means manual selection through DPLX, FORCE100. This pin also is reflected as ANEGA bit, MII Status Register 1, bit 3. LEDSPD[3]/BURN_IN Port [3] Speed LED Input/Output, Pull-Up LED is low when operating in 100BASE-X modes and high when operating in 10BASE-T modes. BURN_IN: Burn-In mode. Burn-in mode for reliability assurance control. Leave unconnected. Bias IBREF Reference Bias Resistor Analog To be tied to an external 10-kW (1%) resistor which should be connected to the analog ground at the other end. Power and Ground OVDD Power Digital These pins are the digital +3.3 V power supply for I/O. OGND Ground Digital These pins are the digital ground for I/O. CVDD Power Digital These pins are the digital +3.3 V power supply for the Core logic. CGND Ground Digital These pins are the digital ground for Core logic. AVDD Power Analog These pins are the +3.3V power supply for analog circuit. AGND Ground Analog These pins are the ground for analog circuit. GAVDD Power Analog These pins are the +3.3 V power supply for common analog circuits. GAGND Ground Analog This pin is the ground for common analog circuits. 12 Am79C875

13 FUNCTIONAL DESCRIPTION Overview The NetPHY-4LP transceiver is a four-port CMOS device that implements the complete physical layer for 10BASE-T and the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) functionality for 100BASE-TX. The NetPHY-4LP transceiver implements Auto-Negotiation allowing two devices connected across a link segment to take maximum advantage of their capabilities. Auto-Negotiation is performed as defined in the IEEE 802.3u specification. The NetPHY-4LP device communicates with a switch or MAC device through the Reduced Media Independent Interface (RMII). The NetPHY-4LP device consists of the following functional blocks: RMII Functional Blocks 100BASE-X Block including: Transmit and Receive State Machines 4B/5B Encoder and Decoder Stream Cipher Scrambler and Descrambler Link Monitor State Machine Far End Fault Indication (FEFI) State Machine MLT-3 Encoder MLT-3 Decoder with adaptive equalization 10BASE-T Block including: Manchester Encoder/Decoder Jabber Receive Polarity Detect Waveshaping and Filtering Carrier Integrity Monitor Auto-Negotiation Status LEDs PHY Control and Management Modes of Operation The RMII interface provides the data path connection between the NetPHY-4LP transceivers and the Media Access Controller (MAC), repeater, or switch devices. The MDC and MDIO pins are responsible for communication between the NetPHY-4LP transceiver and the station management entity (STA). The RMII standard reduces the pin count by halving the number of data pins, eliminating pins not used in switch applications, and using a single global clock. Each port has an independent RMII. RMII uses seven pins per port. They are as follows: Receive Data RXD[X]_[1:0] Carrier Sense CRS_DV[X] Receive Error RX_ER[X] Transmit Data TXD[X]_[1:0] Transmit Enable TX_EN[X] Note: [X] refers to the port. In RMII mode, REF_CLK must be sourced by a 50-MHz clock signal. RMII Pin Descriptions CRS_DV Carrier Sense/Receive Data Valid CRS_DV is asserted by the PHY when the receive medium is non-idle. Loss of carrier results in the deassertion of CRS_DV synchronous to the cycle of REF_CLK, which presents the first di-bit of a nibble onto RXD[1:0] (i.e., CRS_DV is deasserted only on nibble boundaries). If the PHY has additional bits to be presented on RXD[1:0] following the initial deassertion of CRS_DV, the PHY asserts CRS_DV on cycles of REF_CLK which present the second di-bit of each nibble. The PHY deasserts CRS_DV on cycles of REF_CLK which present the first di-bit of the nibble. As a result, starting on the byte boundaries, CRS_DV toggles at 25 MHz in 100 Mbps mode and 2.5 MHz in 10 Mbps mode when CRS ends before RX_DV (i.e., the FIFO still has bits to transfer when the carrier event ends). Therefore, the MAC can accurately recover RX_DV and CRS. Refer to Figure 1. During a false carrier event, CRS_DV remains asserted for the duration of carrier activity. Refer to Figure 2. The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous relative to REF_CLK, the data on RXD[1:0] is 00 until proper receive signal decoding takes place. Note: CRS_DV is asserted asynchronously in order to minimize latency of control signals through the PHY. Am79C875 13

14 REF_CLK CRS_DV RXD[1] A B C D E F 0 RXD[0] A B C D E F 0 /J/ /K/ Preamble SFD Data 22236G-4 Note: CRS_DV may toggle at 25 MHz starting on a nibble boundary if bits accumulate due to the difference between CRS and RX_DV. The example waveform shows a single nibble accumulated in the FIFO. Figure Mbps Reception with No Errors REF_CLK CRS_DV RXD[1] RXD[0] False Carrier detected 22236G-5 Figure Mbps Reception with False Carrier RXD[1:0] Receive Data [1:0] RXD[1:0] transitions synchronously to REF_CLK. Upon assertion of CRS_DV, the PHY will ensure that RXD[1:0] = 00 until proper receive decoding takes place. Then for each clock period in which CRS_DV is asserted, RXD[1:0] transfers two bits of recovered data from the PHY. RXD[1:0] in 100 Mbps Mode For normal reception following assertion of CRS_DV, RXD[1:0] is 00 until the receiver has determined that the receive event has a proper Start of Stream Delimiter (SSD), which is a /J/K/ pair. Thereafter, preamble will appear (RXD[1:0] = 01). Data capture by MACs occur following detection of SFD. If False Carrier is detected (an event starting with anything other than /J/K/), then RXD[1:0] is 10 until the end of the receive event. This is a unique pattern since False Carrier can only occur at the beginning of a packet where a preamble will be decoded (i.e., RXD[1:0]=01). RXD[1:0] in 10 Mbps Mode Following assertion of CRS_DV, RXD[1:0] shall be 00 until the 10BASE-T PHY has recovered clock and is able to decode the receive data. Once valid receive data is available from the 10BASE-T PHY, RXD[1:0] takes on the recovered data values (i.e., starting with 01 for preamble). At a REF_CLK frequency of 50 MHz, the value on RXD[1:0] is valid such that RXD[1:0] may be sampled every tenth cycle, regardless of the starting cycle within the group and yield the correct frame data. 14 Am79C875

15 TXD[1:0] Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] is accepted for transmission by the PHY. TXD[1:0] is ignored by the PHY while TX_EN is deasserted. TXD[1:0] in 100 Mbps Mode TXD[1:0] provides valid data for each REF_CLK period while TX_EN is asserted. Refer to Figure 3. TXD[1:0] in 10 Mbps Mode As the REF_CLK frequency is ten times the data rate in 10 Mbps mode, the value on TXD[1:0] is valid such that TXD[1:0] may be sampled every tenth cycle, regardless of the starting cycle within the group and yield the correct frame data. Bit Ordering Transmission and reception of each octet is done a dibit at a time with the order of di-bit transmission and reception as shown in Figure 4. REF_CLK TX_EN TXD[1] A B C D E F 0 TXD[0] A B C D E F 0 Preamble SFD Data 22236G-6 Figure Mbps Transmission First Bit First Nibble MAC's Serial Bit Stream D0 D1 D2 D3 D4 D5 D6 D7 Second Nibble Di-Bit Stream TXD[0]/RXD[0] TXD[1]/RXD[1] LSB MSB D0 D G-7 Figure 4. Bit Ordering 100BASE-X Block The functions performed by the device include encoding of MII 4-bit data (4B/5B), decoding of received code groups (5B/4B), generating carrier sense and collision detect indications, serialization of code groups for transmission, de-serialization of serial data from reception, mapping of transmit, receive, and carrier sense at the RMII interface, and recovery of clock from the incoming data stream. It offers stream cipher scrambling and descrambling capability for 100BASE-TX applications. In the transmit data path for 100 Mbps, the NetPHY-4LP transceiver receives 2-bit wide data across the RMII at 50 million di-bits per second. For 100BASE-TX applications, it encodes and scrambles the data, serializes it, and transmits an MLT-3 data stream to the media via an isolation transformer. For 100BASE-FX applications, it encodes and serializes the data and transmits a Pseudo-ECL (PECL) data stream to the fiber optic transmitter. The NetPHY-4LP transceiver receives an MLT-3 data stream from the network for 100BASE-TX. It then recovers the clock from the data stream, de-serializes the data stream, and descrambles/decodes the data stream (5B/4B) before presenting it at the RMII interface. For 100BASE-FX operation, the NetPHY-4LP receives a PECL data stream from the fiber optic transceiver and decodes that data stream. 100BASE-FX operation is possible only on Port 3. Am79C875 15

16 Within the NetPHY-4LP device, this block is replicated for each port. The RMII signals should be taken in context with the port being referred. The 100BASE-X block consists of the following sub-blocks: Transmit Process Receive Process Internal Loopback Paths 4B/5B Encoder and Decoder Scrambler/Descrambler Link Monitor Far End Fault Generation and Detection & Code-Group Generator MLT-3 encoder/decoder with Adaptive Equalization Serializer/Deserializer and Clock Recovery Baseline Restoration Transmit Process The transmit process generates code-groups based on the transmit control and data signals on the RMII. This process is also responsible for frame encapsulation into a Physical Layer Stream, generating the collision signal based on whether a carrier is received simultaneously with transmission and generating the Carrier Sense CRS signal at the RMII. The transmit process is implemented in compliance with the transmit state diagram as defined in Clause 24 of the IEEE 802.3u specification. Receive Process The receive process passes to the RMII a sequence of data derived from the incoming code-groups. Each code-group is comprised of five code-bits. This process detects channel activity and then aligns the incoming code bits in code-group boundaries for subsequent data decoding. The receive process is responsible for code-group alignment and also generates the Carrier Sense (CRS) signal at the RMII. The receive process is implemented in compliance with the receive state diagram as defined in Clause 24 of the IEEE 802.3u specification. The False Carrier Indication as specified in the standard is also generated by this block, and communicated to the Reconciliation layer through RXD and RX_ER. Encoder/Decoder The 100 Mbps process in the NetPHY-4LP device uses the 4B/5B encoding scheme as defined in IEEE 802.3, Section 24. This scheme converts between raw data on the RMII and encoded data on the media pins. The encoder converts raw data to the 4B/5B code. It also inserts the stream boundary delimiters (/J/K/ and /T/R/) at the beginning and end of the data stream as appropriate. The decoder converts between encoded data on the media pins and raw data on the RMII. It also detects the stream boundary delimiters to help determine the start and end of packets. The code-group mapping is defined in Table 1. Scrambler/Descrambler The 4B/5B encoded data has repetitive patterns which result in peaks in the RF spectrum large enough to keep the system from meeting the standards set by regulatory agencies such as the FCC. The peaks in the radiated signal are reduced significantly by scrambling the transmitted signal. Scramblers add the output of a random generator to the data signal. The resulting signal has fewer repetitive data patterns. After reset, the scrambler seed in each port will be set to the PHY address value to help improve the EMI performance of the device. The scrambled data stream is descrambled, at the receiver, by adding it to the output of another random generator. The receiver s random generator has the same function as the transmitter s random generator. The scrambler/descrambler configuration is set by the SCRAM_EN pin and the EN_SCRM bit (Register 24, bit 2). The SCRAM_EN pin is latched at the rising edge of the RST signal. The scrambler/descrambler can be enabled if SCRAM_EN latches above 2.0 V. Otherwise, they are all disabled. The EN_SCRM bit sets the scrambler/descrambler configuration for the corresponding port. The bit defaults to 1 at reset. The scrambler/descrambler can only be enabled when the port is in the 100-Mbps MLT-3 mode. The scrambler is disabled on any port that has a link at 10 Mbps or any port that is forced to 10 Mbps. Link Monitor Signal levels are qualified using squelch detect circuits. A signal detect (SD) circuit following the equalizer is asserted high whenever the peak detector detects a postequalized signal with peak-to-ground voltage level larger than 400 mv, which is about 40% of the normal signal voltage level, and the energy level is sustained longer than 2 ~ 3 ms. It is deasserted approximately 1 ms to 2 ms after the energy level detected in the receiving lines is consistently less than 300 mv peak. The signal is forced to low during a local loopback operation (Register 0, bit 14 Loopback is asserted) and forced to high when a remote Loopback is taking place (Register 24, bit 3 EN_RPBK is set). In 100BASE-TX mode, when no signal or invalid signals are detected on the receive pair, the link monitor will enter in the link fail state where only link pulses will be transmitted. Otherwise, when a valid signal is detected for a minimum period of time, the link monitor will then enter link pass state which transmit and receive functions will be entered. 16 Am79C875

17 Table 1. In 100BASE-FX mode, the external fiber-optic receiver performs the signal energy detection function and communicates this information directly to the NetPHY-4LP device through SDI± pins. In 10BASE-T mode, a link-pulse detection circuit will constantly monitor the RX± pins for the presence of valid link pulses. Code-Group Mapping MII (TXD[3:0]) Name PCS Code-Group Interpretation Data Data Data Data Data Data Data Data Data Data A Data A B Data B C Data C D Data D E Data E F Data F Undefined I IDLE; used as inter-stream fill code J K Undefined T Start-of-Stream Delimiter, Part 1 of 2; always used in pairs with K Start-of-Stream Delimiter, Part 2 of 2; always used in pairs with J End-of-Stream Delimiter, Part 1 of 2; always used in pairs with R Undefined R End-of-Stream Delimiter, Part 2 of 2; always used in pairs with T Undefined H Transmit Error; used to force signaling errors Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code Undefined V Invalid Code 10BASE-T Block The NetPHY-4LP transceiver incorporates four fully independent 10BASE-T physical layer functions, including clock recovery (ENDEC), MAUs, and transceiver functions. The NetPHY-4LP transceiver receives 10- Mbps data from the MAC, switch, or repeater across the RMII at 5 million di-bits per second. It then Manchester encodes the data before transmission to the network. Am79C875 17

18 The 10BASE-T block consists of the following sub-blocks: Transmit Function Receive Function Interface Status Jabber Function Reverse Polarity Detect Refer to Figure 5 for the 10BASE-T transmit and receive data paths. Figure 5. Clock Data Manchester Encoder TX Driver TX± Loopback (Register 0) Clock Data Manchester Decoder Squelch Circuit RX Driver RX± 22236G-8 10BASE-T Transmit/Receive Data Paths Twisted Pair Transmit Function Data transmission over the 10BASE-T medium requires use of the integrated 10BASE-T MAU and uses the differential driver circuitry on the TX± pins. TX± is a differential twisted-pair driver. When properly terminated, TX± meets the transmitter electrical requirements for 10BASE-T transmitters as specified in IEEE 802.3, Section The load is a twisted pair cable that meets IEEE 802.3, Section The TX± signal is filtered on the chip to reduce harmonic content per Section (10BASE-T). Since filtering is performed in silicon, TX± can be connected directly to a standard transformer. External filtering modules are not needed. Twisted Pair Receive Function RX+ ports are differential twisted-pair receivers. When properly terminated, each RX+ port meets the electrical requirements for 10BASE-T receivers as specified in IEEE 802.3, Section Each receiver has internal filtering and does not require external filter modules or common mode chokes. Signals appearing at the RX± differential input pair are routed to the internal decoder. The receiver function meets the propagation delays and jitter requirements specified by the 10BASE-T Standard. The receiver squelch level drops to half its threshold value after unsquelch to allow reception of minimum amplitude signals and to mitigate carrier fade in the event of worst case signal attenuation and crosstalk noise conditions. Twisted Pair Interface Status The NetPHY-4LP transceiver will power up in the Link Fail state. The Auto-Negotiation algorithm will apply to allow it to enter the Link Pass state. In the Link Pass state, receive activity which passes the pulse width/amplitude requirements of the RX± inputs cause the PCS Control block to assert Carrier Sense (CRS) signal at the MII interface. Jabber Function The Jabber function inhibits the 10BASE-T twisted pair transmit function of the NetPHY-4LP transceiver device if the TX± circuits are active for an excessive period ( ms). This prevents one port from disrupting the network due to a stuck-on or faulty transmitter condition. If the maximum transmit time is exceeded, the data path through the 10BASE-T transmitter circuitry is disabled (although Link Test pulses will continue to be sent). The PCS Control block also sets the Jabber Detect bit in Register 1. Once the internal transmit data stream from the MENDEC stops, an unjab time of ms will elapse before this block causes the PCS Control block to re-enable the transmit circuitry. When jabber is detected, this block allows the PCS Control block to assert or de-assert the CRS pin to indicate the current state of the RX± pair. If there is RX± activity, this block causes the PCS Control block to assert CRS at the RMII. The Jabber function can be disabled by setting Register 24, bit 12. Reverse Polarity Detect and Correction Proper 10BASE-T receiver operation requires that the differential input signal be the correct polarity. That is, the RX+ line is connected to the RX+ input pin, and the RX- line is connected to the RX- input pin. Improper setup of the external wiring can cause the polarity to be reversed. The NetPHY-4LP receivers have the ability to detect the polarity of the incoming signal and compensate for it. Thus, the proper signal will appear on the MDI regardless of the polarity of the input signals. The internal polarity detection and correction circuitry is set during the reception of the normal link pulses (NLP) or packets. The receiver detects the polarity of the input signal on the first NLP. It locks the polarity cor- 18 Am79C875

19 rection circuitry after the reception of two consecutive packets. The state of the polarity correction circuitry is locked as long as link is established. This function is only available in 10BASE-T mode. Far-End Fault Indication (FEFI) Auto-Negotiation provides a remote fault capability for detecting an asymmetric link failure. Since 100BASE-FX systems do not use Auto-Negotiation, an alternative, in-band signaling scheme is used to signal remote fault conditions. This scheme, Far End Fault Indication, relies on the characteristics of the quiescent state, a continuous IDLE stream. The IDLE stream is a continuous stream of logic ones followed by one logic zero, with the pattern repeated at least 3 times. A Far-End Fault will be signaled under the following three conditions: (1) When no activity is received from the link partner, since this can indicate a broken receive wire, (2) When the clock recovery circuit detects a receive signal error or PLL lock error, (3) When management entity sets the transmit Far-end fault bit (Register 24, bit 7). The Far-End fault mechanism defaults to enabled in 100BASE-FX mode and disabled in 100BASE-TX and 10BASE-T modes, and may be controlled by software after reset. MLT-3 This block is responsible for converting the NRZI data stream from the PDX block to the MLT-3 encoded data stream. The effect of MLT-3 is the reduction of energy on the copper media (TX or FX cable) in the critical frequency range of 1 MHz to 100 MHz. The receive section of this block is responsible for equalizing and amplifying the received data stream and link detection. The adaptive equalizer compensates for the amplitude and phase distortion due to the cable. MLT-3 is a tri-level signal. All transitions are between 0 V and +1 V or 0 V and -1 V. A transition has a logical value of 1 and a lack of a transition has a logical value of 0. The benefit of MLT-3 is that it reduces the maximum frequency over the data line. The bit rate of TX data is 125 Mbps. The maximum frequency (using NRZI) is half of 62.5 MHz. MLT-3 reduces the maximum frequency to MHz. A data signal stream following MLT-3 rules is illustrated in Figure 6. The data stream is MLT ns Figure 6. MLT-3 Waveform 22236G-9 The TX± drivers convert the NRZI serial output to MLT-3 format. The RX± receivers convert the received MLT-3 signals to NRZI. The transmit and receive signals will be compliant with IEEE 802.3u, Section 25. The required signals (MLT-3) are described in detail in ANSI X3.263:1995 TP-PMD Revision 2.2 (1995). The NetPHY-4LP device provides on-chip filtering. External filters are not required for either the transmit or receive signals. The TX pins can be connected to the media via either a 1:1 transformer or a 1.25:1 transformer. The 1.25:1 ratio provides a 20% transmit power savings over the 1:1 ratio. Refer to Figure 7. Adaptive Equalizer The NetPHY-4LP device is designed for the maximum of 140 meter UTP-5 cable. A 140-meter UTP-5 cable attenuates the signal by 32 db at 100 MHz which far exceed the cable plant attenuation (24-26 db) defined by TP-PMD. The amplitude and phase distortion from cable causes inter-symbol interference (ISI) which makes clock and data recovery impossible. Adaptive equalization is done by closely matching the characteristics of the twisted-pair cable. This is a variable equalizer which changes equalizer frequency response in accordance with cable length. The cable length is estimated based on comparisons of incoming signal strength against some known cable characteristics. The equalizer tunes itself automatically to the any cable length to compensate for the amplitude and phase distortion incurred from the cable. Baseline Wander Compensation The 100BASE-TX data stream is not always DC balanced. The media, with transformer and common Am79C875 19

20 mode filtering blocks the DC component of the code and the DC offset of the differential receive input can wander. The shift in the signal levels causes increase in error rates. A DC restoration circuit is needed to compensate for the attenuation of DC components. The NetPHY-4LP device implemented a patent-pending DC restoration circuit which, unlike the traditional implementation, does not need the feedback information from the slicer and clock recovery. The baseline wander correction circuit is not required and, therefore, is bypassed when the port is 10BASE-T. Clock/Data Recovery The equalized MLT-3 signal is converted into NRZI format. The NetPHY-4LP device uses an analog phase locked loop (APLL) to extract clock information of the incoming NRZI data which is used to re-time the data stream and set data boundaries. The receive clocks are locked to the incoming data streams. PPM should be between 50 and 100. When initial lock is achieved, the APLL switches to lock-to-data stream, extracts a 125-MHz clock. The recovered 125 MHz clock is also used to generate the 25- MHz RX_CLK. The APLL requires no external components for its operation and has high noise immunity and low jitter. It provides fast phase align (lock) to data in one transition and its data/clock acquisition time after power-on is less than 60 transitions. The APLL can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. When no valid data is present, the APLL switches back to lock with the TX_CLK, providing a continuously running RX_CLK. The recovered data is converted from NRZI-to-NRZ and then to a 5-bit parallel format. The 5-bit parallel data is not necessarily aligned to 4B/5B code-group s symbol boundary. The data is presented to PCS at receive data register output, gated by the 25-MHz RX_CLK. TX+ (Note 3) (Note 3) V DD Isolation Transformer with common-mode chokes * 1:1 or 1.25:1 * RJ45 Connector (8) (7) TX+ (1) (5) (4) TX SDI/MLT3EN 1 kω 0.1 µf 75 Ω 75 Ω 75 Ω TX (2) RX+ 50 Ω (Note 4) * 1:1 * RX+ (3) RX 50 Ω (Note 4) RX (6) 0.1 µf 75 Ω 470 pf 0.1 µf 470 pf (chassis ground) (chassis ground) Notes: 1. The isolation transformers include common-mode chokes. 2. Consult magnetics vendors for appropriate termination schemes W if a 1:1 isolation transformer is used or 78 W if a 1.25:1 isolation transformer is used (49.9) W is normal, but 54.9 W can be used for extended cable length operation G-10 Figure 7. TX± and RX± Termination for 100BASE-TX and 10BASE-T 20 Am79C875