Automotive EMI System

Transcription

1 Automotive EMI System Page 1 Model Types Body Variants Car Geometry Board Net, Wire Path, ECU Configuration, Antenna Configurations... Parameters Affecting EMC Car Supply Net Voltage Regulator Signals Line Driver Micro- Controller Application PCB IC Types PCB Types Shielding, Noise Filters Signals Leaving PCB...

2 EMC ElectroMagnetic Compatibility Interference of Cockpit Electronic via Cabling Page 2

3 EMI System: Quality and Reliability The overall electrical system has to perform good EMC is as bad as its worst component Every system part has to contribute to low EMI EMI optimization must not impact other quality issues performance, ESD, latchup, life cycle Design weaknesses cause costs cause time-to-market delay can be avoided if early simulations are done Electromagnetic Reliability is Given if an Electrical System Page 3 Functions Satisfactorily in its Electromagnetic Environment without Having an Impermissible Effect on its Environment.

4 Trends of Important Parameters of Nano IC Fast Nano IC => Threshold Approaches 150 mv Transistor Switching by Noise Amplitude < 200 mv ECU => Noise Amplitude from 200mV to 300 mv Page 4

5 IC Technology Nodes of Automotive Electronic Control Units Page 5 ECU Transistors < 100 nm Nano IC Susceptible Against RF and Pulse Noise Margin between Noise Level and Transitor Switching Threshold Lesser

6 Electromagnetic Reliability (EMR) EME Noise Emission Störemission vs. Number vs. Transistorzahl of Transistors EMS Noise Störamplituden Amplitudes vs. vs. Switching Schaltschwellen Threshold [dbµv] [Mio] Jahr EME-Grenzwert Limit [dbµv] Mikrocontroller-Emission Micro Controler Emission [dbµv] [dbµv] Anzahl Number Transistoren of Transistors [Mio] [Mio] [V] 0,3 0,25 0,2 0,15 0,1 0, Jahr Störpegel Noise Level [V] [V] Schwellspannung Threshold Voltage Vt [V] V t [V] Page 6 DesignToNoise Margin Challenge Design-to-Noise -Herausforderungen in PARACHUTE

7 Roadmap Electromagnetic Reliability (EMC/EMR) Modelling and Analysis of EMR Effects on System Level Application Challenges Parasitic Effects OnChip/OffChip (Emission/Susceptibility) Smart Modells (Emission/Susceptibility) Noise Path Tracing Power Ground Synthesis Research Challenges Parameterized Models for OnChip/OffChip Package Co-Design (22 nm) EMR Models for OnChip/OffChip Characterization (22 nm) Parasitic Effect Backanotation New Measurement Techniques Full Chip/System EMR Page /

8 Summary - 1 EMC/EMR of Systems in Harsh Environments Model Based Design Simulation on System/Subsystem/Component Level RF/EMC/EMR/SI Model with Modular Character Simulation Model System Input Nominal Function System Response + Technology independent Parasitic 1 first order efefcts transmission path of interconnect + Technology dependent Page 8 Symbolic Analysis Behavioral Language/Description Parasitic 2 first order efefcts coupling path of interconnect Technology dependent

9 Summary - 2 EMC/EMR of Systems in Harsh Environments Model Based Design Experiment/ Measurement Database Data Analyze Tool Simple Models Model Model Simulation Simple Models Real Objects Abstract System Design Real Objects Object Object Complex Models Model Model Complex Models Software Objects Software Objects SW SW Page 9 Training Training and and Knowledge Knowledge Organisation Organisation Presentation/Animation Visualization Visualization

10 Summary - 3 EMC/EMR of Systems in Harsh Environments Page 10 Support Simulation of Overall EMC/EMR Behaviour Throughout the Design Phases Early Design Stages Design to Noise Margin Modularisation and Transfer of EMC/EMR Models Between all Design Levels has Become a Necessity Model Based Development Interconnect Driven Design Improvement of Existing Design Flows Integration into Existing Design Flows Technology Assessment and Description (Cost/Material Data and Parameter) New Models for Education and Training Knowledge Organisation