ILI9335. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color. Datasheet

Transcription

1 a-si TFT LCD Single Chip Driver Datasheet Version: V19 Document No: DS_V19pdf ILI TECHNOLOGY CORP 8F, No38, Taiyuan St, Jhubei City, Hsinchu County 32, Taiwan, ROC Tel ; Fax

2 Table of Contents Section Page 1 Introduction 7 2 Features 8 3 Block Diagram 1 4 Pin Descriptions 11 5 Pad Arrangement and Coordination 15 6 Block Description 25 7 System Interface Interface Specifications Input Interfaces i8/18-bit System Interface i8/16-bit System Interface (DB[15:]) i8/16-bit System Interface (DB[17:1][8:1]) i8/9-bit System Interface (DB[17:9]) i8/8-bit System Interface (DB[17:1]) Serial Peripheral Interface (SPI) VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface Interface Timing 49 8 Register Descriptions 5 81 Registers Access 5 82 Instruction Descriptions Index (IR) ID code (Rh) Driver Output Control (R1h) LCD Driving Wave Control (R2h) Entry Mode (R3h) bits Data Format Selection (R5h) Display Control 1 (R7h) Display Control 2 (R8h) Display Control 3 (R9h) Display Control 4 (RAh) 64 Page 2 of 113 Version: 19

3 8211 RGB Display Interface Control 1 (RCh) Frame Marker Position (RDh) RGB Display Interface Control 2 (RFh) Power Control 1 (R1h) Power Control 2 (R11h) Power Control 3 (R12h) Power Control 4 (R13h) GRAM Horizontal/Vertical Address Set (R2h, R21h) Write Data to GRAM (R22h) Read Data from GRAM (R22h) Power Control 7 (R29h) Frame Rate and Color Control (R2Bh) Gamma Control (R3h ~ R3Dh) Horizontal and Vertical RAM Address Position (R5h, R51h, R52h, R53h) Gate Scan Control (R6h, R61h, R6Ah) Partial Image 1 Display Position (R8h) Partial Image 1 RAM Start/End Address (R81h, R82h) Partial Image 2 Display Position (R83h) Partial Image 2 RAM Start/End Address (R84h, R85h) Panel Interface Control 1 (R9h) Panel Interface Control 2 (R92h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) OTP VCM Programming Control (RA1h) OTP VCM Status and Enable (RA2h) OTP Programming ID Key (RA5h) Deep stand by control (RE6h) 82 9 OTP Programming Flow 84 1 GRAM Address Map & Read/Write Window Address Function 9 12 Gamma Correction Application Configuration of Power Supply Circuit Display ON/OFF Sequence Standby and Sleep Mode Power Supply Configuration Voltage Generation Applied Voltage to the TFT panel Partial Display Function 15 Page 3 of 113 Version: 19

4 14 Electrical Characteristics Absolute Maximum Ratings DC Characteristics Reset Timing Characteristics AC Characteristics i8-system Interface Timing Characteristics Serial Data Transfer Interface Timing Characteristics RGB Interface Timing Characteristics Vcom Driving Revision History 113 Page 4 of 113 Version: 19

5 Figures FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION 28 FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT 29 FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT 3 FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT 31 FIGURE 6 DATA FORMAT OF SPI INTERFACE 34 FIGURE7 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 35 FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= 1 AND DFM= 1 ) 36 FIGURE9 DATA TRANSMISSION THROUGH VSYNC INTERFACE) 37 FIGURE1 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE 37 FIGURE11 OPERATION THROUGH VSYNC INTERFACE 38 FIGURE13 RGB INTERFACE DATA FORMAT 41 FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE 42 FIGURE15 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE 43 FIGURE16 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE 44 FIGURE17 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE 45 FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING 48 FIGURE2 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL 49 FIGURE21 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 5 FIGURE22 REGISTER SETTING WITH I8 SYSTEM INTERFACE 51 FIGURE 23 REGISTER READ/WRITE TIMING OF I8 SYSTEM INTERFACE 52 FIGURE24 GRAM ACCESS DIRECTION SETTING 57 FIGURE26 8-BIT MPU SYSTEM INTERFACE DATA FORMAT 59 FIGURE 27 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE 71 FIGURE 28 GRAM DATA READ BACK FLOW CHART 72 FIGURE 29 GRAM ACCESS RANGE CONFIGURATION 75 FIGURE3 GRAM READ/WRITE TIMING OF I8-SYSTEM INTERFACE 85 FIGURE31 I8-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=, BGR= ) 87 FIGURE32 I8-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=, BGR= ) 88 FIGURE 33 I8-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS= 1, BGR= 1 ) 89 FIGURE 34 GRAM ACCESS WINDOW MAP 9 FIGURE 35 GRAYSCALE VOLTAGE GENERATION 91 FIGURE 36 GRAYSCALE VOLTAGE ADJUSTMENT 92 FIGURE 37 GAMMA CURVE ADJUSTMENT 93 FIGURE 38 EXAMPLE OF RMP(N)~5 DEFINITION 95 FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM 98 FIGURE 4 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL 98 FIGURE 41 POWER SUPPLY CIRCUIT BLOCK 99 FIGURE 42 DISPLAY ON/OFF REGISTER SETTING SEQUENCE 11 Page 5 of 113 Version: 19

6 FIGURE 43 STANDBY/SLEEP MODE REGISTER SETTING SEQUENCE 12 FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE 13 FIGURE 45 VOLTAGE CONFIGURATION DIAGRAM 14 FIGURE 46 VOLTAGE OUTPUT TO TFT LCD PANEL 15 FIGURE 47 PARTIAL DISPLAY EXAMPLE 16 FIGURE 48 I8-SYSTEM BUS TIMING 19 FIGURE5 RGB INTERFACE TIMING 111 Page 6 of 113 Version: 19

7 1 Introduction a-si TFT LCD Single Chip Driver is a 262,144-color one-chip SoC driver for a-tft liquid crystal display with resolution of 24RGBx32 dots, comprising a 72-channel source driver, a 32-channel gate driver, 172,8 bytes RAM for graphic data of 24RGBx32 dots, and power supply circuit has four kinds of system interfaces which are i8-system MPU interface (8-/9-/16-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, DB[17:]), serial data transfer interface (SPI), RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 165V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where long battery life is a major concern Page 7 of 113 Version: 19

8 2 Features a-si TFT LCD Single Chip Driver Single chip solution for a liquid crystal QVGA TFT LCD display 24RGBx32-dot resolution capable with real 262,144 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 72-channel source driver and 32-channel gate driver Internal 172,8 bytes graphic RAM System interfaces i8 system interface with 8-/ 9-/16-/18-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:]) VSYNC interface (System interface + VSYNC) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 262,144 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LCD panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode deep stand by mode Low -power consumption architecture Low operating power supplies: IOVcc = 165V ~ 36 V (interface I/O) VCI = 25V ~ 36 V (analog) LCD Voltage drive: Source/VCOM power supply voltage DDVDH - GND = 45V ~ 6 VCL GND = -2V ~ -3V VCI VCL 6V Gate driver output voltage VGH - GND = 1V ~ 2V VGL GND = -5V ~ -15V Page 8 of 113 Version: 19

9 VGH VGL 3V VCOM driver output voltage VCOMH = (VCI+2)V ~ (DDVDH-2)V VCOML = (VCL+2)V ~ V VCOMH-VCOML 6V a-tft LCD storage capacitor: Cst only Page 9 of 113 Version: 19

10 nwr/scl nreset IOVCC IM[3:] ncs MPU 18-bit 16-bit 9-bit I/F Register Index DB[17:] SDO nrd SDI RS DOTCLK VSYNC HSYNC RGB SPI 18-bit 16-bit 18 (IR) Register Control TEST1 I/F (CR) 7 Address Counter 18 TS[8:] TEST2 VSYNC I/F Operation Graphics 18 (AC) Source Driver LCD S[72:1] ENABLE TEST3 18 Latch Read Write Latch V63 18 VREG1OUT GND VCC Regulator Graphics (GRAM) RAM18 Grayscale Reference ~ Voltage VGS VDDD DUMMY2~27 DUMMY1~15 RC-OSC Controller Timing Driver LCD Gate G[32:1] VCI1 GND Charge-pump Power Circuit VCOM C1AC1BDVDHC12AC12B VCL C2AC2BVGHVGL Generator VCOM C13AC13B C21AC21B VCOMH VCOML 3 Block Diagram Page 1 of 113 Version: 19

11 4 Pin Descriptions Pin Name I/O Type Descriptions Input Interface Select the MPU system interface mode IM3 IM2 IM1 IM MPU-Interface Mode DB Pin in use Setting invalid 1 Setting invalid 1 i8-system 16-bit interface DB[17:1], DB[8:1] 1 1 i8-system 8-bit interface DB[17:1] IM3, IM2, IM1, IM/ID I IOVcc 1 ID Serial Peripheral Interface (SPI) SDI, SDO 1 1 * Setting invalid 1 Setting invalid 1 1 i8-system 16-bit interface DB[15:] 1 1 i8-system 18-bit interface DB[17:] i8-system 9-bit interface DB[17:9] 1 1 * * Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code ID setting A chip select signal ncs I MPU IOVcc Low: the is selected and accessible High: the is not selected and not accessible Fix to the GND level when not in use A register select signal RS I MPU IOVcc Low: select an index or status register High: select a control register Fix to either IOVcc or GND level when not in use A write strobe signal and enables an operation to write data when the signal is low nwr/scl I MPU IOVcc Fix to either IOVcc or GND level when not in use SPI Mode: Synchronizing clock signal in SPI mode nrd I MPU IOVcc A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GND level when not in use nreset I MPU IOVcc A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SDI I MPU IOVcc SPI interface input pin The data is latched on the rising edge of the SCL signal SDO O MPU IOVcc SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SDO as floating when not used An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: DB[17:1] is used 9-bit I/F: DB[17:9] is used 16-bit I/F: DB[17:1] and DB[8:1] is used DB[17:] I/O MPU IOVcc 18-bit I/F: DB[17:] is used 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: DB[17:12] are used 16-bit RGB I/F: DB[17:13] and DB[11:1] are used 18-bit RGB I/F: DB[17:] are used Unused pins must be fixed to GND level ENABLE I MPU IOVcc Data ENEABLE signal for RGB interface operation Low: Select (access enabled) Page 11 of 113 Version: 19

12 DOTCLK VSYNC HSYNC FMARK Pin Name I/O Type Descriptions I I I O MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc S72~S1 O LCD G32~G1 O LCD VCOM VCOMH VCOML VGS VCI VCC VCI1 DDVDH VGH VGL VCL O O O I I I O O O O O TFT common electrode Stabilizing capacitor Stabilizing capacitor GND or external resistor Power supply Power supply Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal Fix to either IOVcc or GND level when not in use Dot clock signal for RGB interface operation DPL = : Input data on the rising edge of DOTCLK DPL = 1 : Input data on the falling edge of DOTCLK Fix to the GND level when not in use Frame synchronizing signal for RGB interface operation VSPL = : Active low VSPL = 1 : Active high Fix to the GND level when not in use Line synchronizing signal for RGB interface operation HSPL = : Active low HSPL = 1 : Active high Fix to the GND level when not in use Output a frame head pulse signal The FMARK signal is used when writing RAM data in synchronization with frame Leave the pin open when not in use LCD Driving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S1 SS = 1, the data in the RAM address h is output from S72 S1, S4, S7, display red (R), S2, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels The high level of VCOM AC voltage Connect to a stabilizing capacitor The low level of VCOM AC voltage Adjust the VCOML level with the VDV bits Connect to a stabilizing capacitor Reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor Charge-pump and Regulator Circuit A supply voltage to the analog circuit Connect to an external power supply of 25 ~ 36V A supply voltage to the digital circuit Connect to an external power supply of 25 ~ 36V An internal reference voltage for the step-up circuit1 The amplitude between VCI and GND is determined by the VC[2:] bits Make sure to set the VCI1 voltage so that the DDVDH, VGH and VGL voltages are set within the respective specification Power supply for the source driver and Vcom drive Power supply for the gate driver Power supply for the gate driver VCOML driver power supply VCL = 5 ~ VCI Place a stabilizing capacitor between GND C11A, C11B I/O Step-up Capacitor connection pins for the step-up circuit 1 Page 12 of 113 Version: 19

13 Pin Name I/O Type Descriptions C12A, C12B capacitor C13A, C13B Step-up C21A, C21B I/O capacitor C22A, C22B Capacitor connection pins for the step-up circuit 2 Output voltage generated from the reference voltage VREG1OUT I/O Stabilizing The voltage level is set with the VRH bits capacitor VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREG1OUT = 3 ~ (DDVDH 5)V Power Pads A supply voltage to the interface pins: IOVCC I IM[3:], nreset, ncs, nwr, nrd, RS, DB[17:], VSYNC, HSYNC, DOTCLK, Power ENABLE, SCL, SDI, SDO supply IOVcc = 165 ~ 36V In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise VDD O Power Digital circuit power pad Connect these pins with the 1uF capacitor DGND I Power DGND for the digital side: DGND = V In case of COG, connect to GND on the FPC supply to prevent noise AGND I Power AGND for the analog side: AGND = V In case of COG, connect to GND on the FPC supply to prevent noise VGMMA1, 62 O - Test pad Leave these pins as open VGLDMY1~4 O Unused gate lines Connect unused gate lines to fix the level at VGL Test Pads DUMMY3, 5~27,3, Dummy pad Leave these pins as open Short circuited within the chip for COG contact resistance measurement DUMMYR DUMMYR1,2, 28, pins are short circuited as below: DUMMYR1 and DUMMYR29 DUMMYR2 and DUMMYR28 DUMMY - - Dummy pad and no output (no gold bump) IOVCCDUM O Connect unused interface and test pins to these pins on the glass to fix voltage AGNDDUM1~6 O - levels Leave open when not used DGNDDUM1~7 O - TESTO1~16 O Open Test pins Leave them open TEST1, 2, 3 I IOGND Test pins (internal pull low) Connect to GND or leave these pins as open TS~8 I OPEN Test pins (internal pull low) Leave them open TSO O OPEN Test pins Leave it open or short to ground TEST_EN I OPEN Test pins Leave it open or short to ground Page 13 of 113 Version: 19

14 Liquid crystal power supply specifications Table 1 No Item Description 1 TFT Source Driver 72 pins (24 x RGB) 2 TFT Gate Driver 32 pins 3 TFT Display s Capacitor Structure Cst structure only (Common VCOM) S1 ~ S72 V ~ V63 grayscales 4 Liquid Crystal Drive Output G1 ~ G32 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes 5 Input Voltage IOVcc 165 ~ 36V VCI 25 ~ 36V DDVDH 45V ~ 6V VGH 1V ~ 2V 6 Liquid Crystal Drive Voltages VGL -5V ~ -15V VCL -19V ~ -3V VGH - VGL Max 3V VCI - VCL Max 6V DDVDH VCI1 x2 7 Internal Step-up Circuits VGH VCI1 x4, x5, x6 VGL VCI1 x-3, x-4, x-5 VCL VCI1 x-1 Page 14 of 113 Version: 19

15 Chip 5 Pad Pad Location: Size: thickness 188um : 28 um x 68um (typ) Arrangement Pad Center and Coordination Coordinate Au bump Bump height: Size: Origin: 12um Chip (typ) center DGNDDUM1 DUMMYR um 5um Output Input x Pads to 94um DUMMYR2 TESTO1 TESTO2 TESTO3 8um panel TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 LEDPWM LEDPWM TESTO9 TESTO1 TESTO11 TESTO12 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND TESTO13 TESTO14 DGNDDUM2 IM /ID IM1 IM2 IM3 IOVCCDUM TESTO15 TESTO16 TEST3 TEST2 TEST1 DGNDDUM3 FMARK VSYNC HSYNC DOTCLK ENABLE TEST_EN DB[17] DB[16] DB[15] TS[8] TS[7] DB[14] DB[13] DB[12] TS[6] TS[5] DB[11] DB[1] DB[9] IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC a-si TFT LCD Single Chip Driver Bump View DB[8] DB[7] DB[6] TS[4] TS[3] DB[5] DB[4] DB[3] TS[2] TS[1] DB[2] DB[1] DB[] TS[] TSO DGNDDUM5 ncs RS nwr/scl nrd nreset SDO SDI DGNDDUM6 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DGNDDUM7 VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD DGND DGND DGND DGND DGND DGND DGND DGND VGS AGND AGND AGND AGND AGND AGND AGND AGND VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOM VCOM VCOM VCOM VCOM VCOM VCOML VCOML VCOML VCOML VCOML VCOML VCOML C11A C11A C11A C11A C11A C11B C11B C11B C11B C11B C12B C12B C12B C12B C12B C12A C12A C12A C12A C12A DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DUMMY1 VREG1OUT DUMMY11 DUMMY12 AGNDDUM1 AGNDDUM2 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI AGNDDUM3 VGH VGH VGH VGH VGH VGH AGNDDUM4 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM5 VCL VCL VCL VCL C13B C13B C13B C13B C13A C13A C13A C13A AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND C21B C21B C21B C21A C21A C21A C22B C22B C22B C22A C22A C22A DUMMY 13 DUMMY 14 DUMMY 15 DUMMY 16 DUMMY 17 AGNDDUM Face Up (Bump View) x y S35 (,) DUM M Y31 DUM M Y3 DUM M YR2 9 DUM M YR2 8 VGL DM Y4 G2 G4 G6 G8 G 31 6 G 34 8 G 32 VGLDM Y 3 DUM M Y27 DUM M Y26 DUM M Y25 S1 S2 S3 S4 8 S35 9 S36 VGM M A1 VGM M A62 S36 1 S36 2 S36 3 S71 7 S71 8 S71 9 S72 DUM M Y24 DUM M Y23 DUM M Y22 VGL DM Y2 G31 9 G31 7 G31 5 G7 G5 G3 G1 VGL DM Y1 DUM M Y21 DUM M Y2 DUM M Y19 DUM M Y18 Page 15 of 113 Version: 19

16 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1 DGNDDUM IOVCC VGS DUMMYR IOVCC AGND DUMMYR IOVCC AGND TESTO[1] IOVCC AGND TESTO[2] IOVCC AGND TESTO[3] IOVCC AGND TESTO[4] IOVCC AGND TESTO[5] IOVCC AGND TESTO[6] DB[8] AGND TESTO[7] DB[7] VCOMH TESTO[8] DB[6] VCOMH DUMMY TS[4] VCOMH DUMMY TS[3] VCOMH TESTO[9] DB[5] VCOMH TESTO[1] DB[4] VCOMH TESTO[11] DB[3] VCOM TESTO[12] TS[2] VCOM DGND TS[1] VCOM DGND DB[2] VCOM DGND DB[1] VCOM DGND DB[] VCOM DGND TS[] VCOML DGND TSO VCOML DGND DGNDDUM VCOML DGND ncs VCOML DGND RS VCOML DGND nwr/scl VCOML TESTO[13] nrd VCOML TESTO[14] nreset C11A DGNDDUM SDO C11A IM/ID SDI C11A IM DGNDDUM C11A IM DUMMY C11A IM DUMMY C11B IOVCCDUM DUMMY C11B TESTO[15] DUMMY C11B TESTO[16] DUMMY C11B TEST DGNDDUM C11B TEST VCC C12B TEST VCC C12B DGNDDUM VCC C12B FMARK VCC C12B VSYNC VCC C12B HSYNC VCC C12A DOTCLK VDD C12A ENABLE VDD C12A TEST_EN VDD C12A DB[17] VDD C12A DB[16] VDD DDVDH DB[15] VDD DDVDH TS[8] VDD DDVDH TS[7] VDD DDVDH DB[14] DGND DDVDH DB[13] DGND DDVDH DB[12] DGND DDVDH TS[6] DGND DDVDH TS[5] DGND DDVDH DB[11] DGND DDVDH DB[1] DGND DUMMY DB[9] DGND VREG1OUT Page 16 of 113 Version: 19

17 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 181 DUMMY AGND G[71] DUMMY AGND G[73] AGNDDUM C21B G[75] AGNDDUM C21B G[77] VCI C21B G[79] VCI C21A G[81] VCI C21A G[83] VCI C21A G[85] VCI C22B G[87] VCI C22B G[89] VCI C22B G[91] VCI C22A G[93] VCI C22A G[95] VCI C22A G[97] VCI DUMMY G[99] VCI DUMMY G[11] VCI DUMMY G[13] VCI DUMMY G[15] VCI DUMMY G[17] VCI AGNDDUM G[19] VCI DUMMY G[111] AGNDDUM DUMMY G[113] VGH DUMMY G[115] VGH DUMMY G[117] VGH VGLDMY G[119] VGH G[1] G[121] VGH G[3] G[123] VGH G[5] G[125] AGNDDUM G[7] G[127] VGL G[9] G[129] VGL G[11] G[131] VGL G[13] G[133] VGL G[15] G[135] VGL G[17] G[137] VGL G[19] G[139] VGL G[21] G[141] VGL G[23] G[143] VGL G[25] G[145] VGL G[27] G[147] AGNDDUM G[29] G[149] VCL G[31] G[151] VCL G[33] G[153] VCL G[35] G[155] VCL G[37] G[157] C13B G[39] G[159] C13B G[41] G[161] C13B G[43] G[163] C13B G[45] G[165] C13A G[47] G[167] C13A G[49] G[169] C13A G[51] G[171] C13A G[53] G[173] AGND G[55] G[175] AGND G[57] G[177] AGND G[59] G[179] AGND G[61] G[181] AGND G[63] G[183] AGND G[65] G[185] AGND G[67] G[187] AGND G[69] G[189] Page 17 of 113 Version: 19

18 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 361 G[191] G[311] S[669] G[193] G[313] S[668] G[195] G[315] S[667] G[197] G[317] S[666] G[199] G[319] S[665] G[21] VGLDMY S[664] G[23] DUMMY S[663] G[25] DUMMY S[662] G[27] DUMMY S[661] G[29] S[72] S[66] G[211] S[719] S[659] G[213] S[718] S[658] G[215] S[717] S[657] G[217] S[716] S[656] G[219] S[715] S[655] G[221] S[714] S[654] G[223] S[713] S[653] G[225] S[712] S[652] G[227] S[711] S[651] G[229] S[71] S[65] G[231] S[79] S[649] G[233] S[78] S[648] G[235] S[77] S[647] G[237] S[76] S[646] G[239] S[75] S[645] G[241] S[74] S[644] G[233] S[73] S[643] G[245] S[72] S[642] G[247] S[71] S[641] G[249] S[7] S[64] G[251] S[699] S[639] G[253] S[698] S[638] G[255] S[697] S[637] G[257] S[696] S[636] G[259] S[695] S[635] G[261] S[694] S[634] G[263] S[693] S[633] G[265] S[692] S[632] G[267] S[691] S[631] G[269] S[69] S[63] G[271] S[689] S[629] G[273] S[688] S[628] G[275] S[687] S[627] G[277] S[686] S[626] G[233] S[685] S[625] G[281] S[684] S[624] G[283] S[683] S[623] G[285] S[682] S[622] G[287] S[681] S[621] G[289] S[68] S[62] G[291] S[679] S[619] G[293] S[678] S[618] G[295] S[677] S[617] G[297] S[676] S[616] G[299] S[675] S[615] G[31] S[674] S[614] G[33] S[673] S[613] G[35] S[672] S[612] G[37] S[671] S[611] G[39] S[67] S[61] Page 18 of 113 Version: 19

19 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 541 S[69] S[549] S[489] S[68] S[548] S[488] S[67] S[547] S[487] S[66] S[546] S[486] S[65] S[545] S[485] S[64] S[544] S[484] S[63] S[543] S[483] S[62] S[542] S[482] S[61] S[541] S[481] S[6] S[54] S[48] S[599] S[539] S[479] S[598] S[538] S[478] S[597] S[537] S[477] S[596] S[536] S[476] S[595] S[535] S[475] S[594] S[534] S[474] S[593] S[533] S[473] S[592] S[532] S[472] S[591] S[531] S[471] S[59] S[53] S[47] S[589] S[529] S[469] S[588] S[528] S[468] S[587] S[527] S[467] S[586] S[526] S[466] S[585] S[525] S[465] S[584] S[524] S[464] S[583] S[523] S[463] S[582] S[522] S[462] S[581] S[521] S[461] S[58] S[52] S[46] S[579] S[519] S[459] S[578] S[518] S[458] S[577] S[517] S[457] S[576] S[516] S[456] S[575] S[515] S[455] S[574] S[514] S[454] S[573] S[513] S[453] S[572] S[512] S[452] S[571] S[511] S[451] S[57] S[51] S[45] S[569] S[59] S[449] S[568] S[58] S[448] S[567] S[57] S[447] S[566] S[56] S[446] S[565] S[55] S[445] S[564] S[54] S[444] S[563] S[53] S[443] S[562] S[52] S[442] S[561] S[51] S[441] S[56] S[5] S[44] S[559] S[499] S[439] S[558] S[498] S[438] S[557] S[497] S[437] S[556] S[496] S[436] S[555] S[495] S[435] S[554] S[494] S[434] S[553] S[493] S[433] S[552] S[492] S[432] S[551] S[491] S[431] S[55] S[49] S[43] Page 19 of 113 Version: 19

20 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 721 S[429] S[369] S[311] S[428] S[368] S[31] S[427] S[367] S[39] S[426] S[366] S[38] S[425] S[365] S[37] S[424] S[364] S[36] S[423] S[363] S[35] S[422] S[362] S[34] S[421] S[361] S[33] S[42] VGMMA S[32] S[419] VGMMA S[31] S[418] S[36] S[3] S[417] S[359] S[299] S[416] S[358] S[298] S[415] S[357] S[297] S[414] S[356] S[296] S[413] S[355] S[295] S[412] S[354] S[294] S[411] S[353] S[293] S[41] S[352] S[292] S[49] S[351] S[291] S[48] S[35] S[29] S[47] S[349] S[289] S[46] S[348] S[288] S[45] S[347] S[287] S[44] S[346] S[286] S[43] S[345] S[285] S[42] S[344] S[284] S[41] S[343] S[283] S[4] S[342] S[282] S[399] S[341] S[281] S[398] S[34] S[28] S[397] S[339] S[233] S[396] S[338] S[278] S[395] S[337] S[277] S[394] S[336] S[276] S[393] S[335] S[275] S[392] S[334] S[274] S[391] S[333] S[273] S[39] S[332] S[272] S[389] S[331] S[271] S[388] S[33] S[27] S[387] S[329] S[269] S[386] S[328] S[268] S[385] S[327] S[267] S[384] S[326] S[266] S[383] S[325] S[265] S[382] S[324] S[264] S[381] S[323] S[263] S[38] S[322] S[262] S[379] S[321] S[261] S[378] S[32] S[26] S[377] S[319] S[259] S[376] S[318] S[258] S[375] S[317] S[257] S[374] S[316] S[256] S[373] S[315] S[255] S[372] S[314] S[254] S[371] S[313] S[253] S[37] S[312] S[252] Page 2 of 113 Version: 19

21 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 91 S[251] S[191] S[131] S[25] S[19] S[12] S[249] S[189] S[129] S[248] S[188] S[128] S[247] S[187] S[127] S[246] S[186] S[126] S[245] S[185] S[125] S[244] S[184] S[124] S[233] S[183] S[123] S[242] S[182] S[122] S[241] S[181] S[121] S[24] S[18] S[12] S[239] S[179] S[119] S[238] S[178] S[118] S[237] S[177] S[117] S[236] S[176] S[116] S[235] S[175] S[115] S[234] S[174] S[114] S[233] S[173] S[113] S[232] S[172] S[112] S[231] S[171] S[111] S[23] S[17] S[11] S[229] S[169] S[19] S[228] S[168] S[18] S[227] S[167] S[17] S[226] S[12] S[16] S[225] S[165] S[15] S[224] S[164] S[14] S[223] S[163] S[13] S[222] S[162] S[12] S[221] S[161] S[11] S[22] S[16] S[1] S[219] S[159] S[99] S[218] S[158] S[98] S[217] S[157] S[97] S[216] S[156] S[96] S[215] S[155] S[95] S[214] S[154] S[94] S[213] S[153] S[93] S[212] S[152] S[92] S[211] S[151] S[91] S[21] S[15] S[9] S[29] S[149] S[89] S[28] S[148] S[88] S[27] S[147] S[87] S[26] S[146] S[86] S[25] S[145] S[85] S[24] S[144] S[84] S[23] S[143] S[83] S[22] S[142] S[82] S[21] S[141] S[81] S[2] S[14] S[8] S[199] S[139] S[79] S[198] S[138] S[78] S[197] S[137] S[77] S[196] S[136] S[76] S[195] S[135] S[75] S[194] S[134] S[74] S[193] S[133] S[73] S[192] S[132] S[72] Page 21 of 113 Version: 19

22 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 181 S[71] S[11] G[23] S[7] S[1] G[228] S[69] S[9] G[226] S[68] S[8] G[224] S[67] S[7] G[222] S[66] S[6] G[22] S[65] S[5] G[218] S[64] S[4] G[216] S[63] S[3] G[214] S[62] S[2] G[212] S[61] S[1] G[21] S[6] DUMMY G[28] S[59] DUMMY G[26] S[58] DUMMY G[24] S[57] VGLDMY G[22] S[56] G[32] G[2] S[55] G[318] G[198] S[54] G[316] G[196] S[53] G[314] G[194] S[52] G[312] G[192] S[51] G[31] G[19] S[5] G[38] G[188] S[49] G[36] G[186] S[48] G[34] G[184] S[47] G[32] G[182] S[46] G[3] G[18] S[45] G[298] G[178] S[44] G[296] G[176] S[43] G[294] G[174] S[42] G[292] G[172] S[41] G[29] G[17] S[4] G[288] G[168] S[39] G[286] G[12] S[38] G[284] G[164] S[37] G[282] G[162] S[36] G[28] G[16] S[35] G[278] G[158] S[34] G[276] G[156] S[33] G[274] G[154] S[32] G[272] G[152] S[31] G[27] G[15] S[3] G[268] G[148] S[29] G[266] G[146] S[28] G[264] G[144] S[27] G[262] G[142] S[26] G[26] G[14] S[25] G[258] G[138] S[24] G[256] G[136] S[23] G[254] G[134] S[22] G[252] G[132] S[21] G[25] G[12] S[2] G[248] G[128] S[19] G[246] G[126] S[18] G[244] G[124] S[17] G[242] G[122] S[16] G[24] G[12] S[15] G[238] G[118] S[14] G[236] G[116] S[13] G[234] G[114] S[12] G[232] G[112] Page 22 of 113 Version: 19

23 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1261 G[11] G[7] G[3] G[18] G[68] G[28] G[16] G[66] G[26] G[14] G[64] G[24] G[12] G[62] G[22] G[1] G[6] G[2] G[98] G[58] G[18] G[96] G[56] G[16] G[94] G[54] G[14] G[92] G[52] G[12] G[9] G[5] G[1] G[88] G[48] G[8] G[86] G[46] G[6] G[84] G[44] G[4] G[82] G[42] G[2] G[8] G[4] VGLDMY G[78] G[38] DUMMYR G[76] G[36] DUMMYR G[74] G[34] DUMMY G[72] G[32] DUMMY Page 23 of 113 Version: 19

24 S1 ~ S72 G1 ~ G32 DUMMY18~31 VGMMA1, 62 VGLDMY1~4 I/O Pads 25 Alignment mark a-si TFT LCD Single Chip Driver Unit: um Pad Pump Min 7 Unit: um Pad Pump Alignment Mark: 1 (Left) 5 Alignment Mark: 2 (Right) 5 Alignment mark X Y Page 24 of 113 Version: 19

25 6 Block Description MPU System Interface supports three system high-speed interfaces: i8-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR) The IR is the register to store index information from control registers and the internal GRAM The WDR is the register to temporarily store data to be written to control registers and the internal GRAM The RDR is the register to temporarily store data read from the GRAM Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation Data are read via the RDR from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time Registers selection by system interface (8-/9-/16-/18-bit bus width) I8 Function RS nwr nrd Write an index to IR register 1 Write to control registers or the internal GRAM by WDR register 1 1 Read from the internal GRAM by RDR register 1 1 Registers selection by the SPI system interface Function R/W RS Write an index to IR register Write to control registers or the internal GRAM by WDR register 1 Read from the internal GRAM by RDR register 1 1 Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK In RGB interface mode, data (DB17-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal Display data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External Display Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Page 25 of 113 Version: 19

26 Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1 The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 172,8 (24 x 32x 18/8) bytes with 18 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,144 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an internal oscillation resistor The frame rate is adjusted by the register setting LCD Driver Circuit The LCD driver circuit of consists of a 72-output source driver (S1 ~ S72) and a 32-output gate driver (G1~G32) Display pattern data are latched when the 72 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 72 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LCD module LCD Driver Power Supply Circuit The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD Page 26 of 113 Version: 19