ILI9335. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color. Datasheet

Transcription

1 a-si TFT LCD Single Chip Driver Datasheet Version: V19 Document No: DS_V19pdf ILI TECHNOLOGY CORP 8F, No38, Taiyuan St, Jhubei City, Hsinchu County 32, Taiwan, ROC Tel ; Fax

2 Table of Contents Section Page 1 Introduction 7 2 Features 8 3 Block Diagram 1 4 Pin Descriptions 11 5 Pad Arrangement and Coordination 15 6 Block Description 25 7 System Interface Interface Specifications Input Interfaces i8/18-bit System Interface i8/16-bit System Interface (DB[15:]) i8/16-bit System Interface (DB[17:1][8:1]) i8/9-bit System Interface (DB[17:9]) i8/8-bit System Interface (DB[17:1]) Serial Peripheral Interface (SPI) VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface Interface Timing 49 8 Register Descriptions 5 81 Registers Access 5 82 Instruction Descriptions Index (IR) ID code (Rh) Driver Output Control (R1h) LCD Driving Wave Control (R2h) Entry Mode (R3h) bits Data Format Selection (R5h) Display Control 1 (R7h) Display Control 2 (R8h) Display Control 3 (R9h) Display Control 4 (RAh) 64 Page 2 of 113 Version: 19

3 8211 RGB Display Interface Control 1 (RCh) Frame Marker Position (RDh) RGB Display Interface Control 2 (RFh) Power Control 1 (R1h) Power Control 2 (R11h) Power Control 3 (R12h) Power Control 4 (R13h) GRAM Horizontal/Vertical Address Set (R2h, R21h) Write Data to GRAM (R22h) Read Data from GRAM (R22h) Power Control 7 (R29h) Frame Rate and Color Control (R2Bh) Gamma Control (R3h ~ R3Dh) Horizontal and Vertical RAM Address Position (R5h, R51h, R52h, R53h) Gate Scan Control (R6h, R61h, R6Ah) Partial Image 1 Display Position (R8h) Partial Image 1 RAM Start/End Address (R81h, R82h) Partial Image 2 Display Position (R83h) Partial Image 2 RAM Start/End Address (R84h, R85h) Panel Interface Control 1 (R9h) Panel Interface Control 2 (R92h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) OTP VCM Programming Control (RA1h) OTP VCM Status and Enable (RA2h) OTP Programming ID Key (RA5h) Deep stand by control (RE6h) 82 9 OTP Programming Flow 84 1 GRAM Address Map & Read/Write Window Address Function 9 12 Gamma Correction Application Configuration of Power Supply Circuit Display ON/OFF Sequence Standby and Sleep Mode Power Supply Configuration Voltage Generation Applied Voltage to the TFT panel Partial Display Function 15 Page 3 of 113 Version: 19

4 14 Electrical Characteristics Absolute Maximum Ratings DC Characteristics Reset Timing Characteristics AC Characteristics i8-system Interface Timing Characteristics Serial Data Transfer Interface Timing Characteristics RGB Interface Timing Characteristics Vcom Driving Revision History 113 Page 4 of 113 Version: 19

5 Figures FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION 28 FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT 29 FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT 3 FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT 31 FIGURE 6 DATA FORMAT OF SPI INTERFACE 34 FIGURE7 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 35 FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= 1 AND DFM= 1 ) 36 FIGURE9 DATA TRANSMISSION THROUGH VSYNC INTERFACE) 37 FIGURE1 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE 37 FIGURE11 OPERATION THROUGH VSYNC INTERFACE 38 FIGURE13 RGB INTERFACE DATA FORMAT 41 FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE 42 FIGURE15 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE 43 FIGURE16 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE 44 FIGURE17 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE 45 FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING 48 FIGURE2 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL 49 FIGURE21 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 5 FIGURE22 REGISTER SETTING WITH I8 SYSTEM INTERFACE 51 FIGURE 23 REGISTER READ/WRITE TIMING OF I8 SYSTEM INTERFACE 52 FIGURE24 GRAM ACCESS DIRECTION SETTING 57 FIGURE26 8-BIT MPU SYSTEM INTERFACE DATA FORMAT 59 FIGURE 27 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE 71 FIGURE 28 GRAM DATA READ BACK FLOW CHART 72 FIGURE 29 GRAM ACCESS RANGE CONFIGURATION 75 FIGURE3 GRAM READ/WRITE TIMING OF I8-SYSTEM INTERFACE 85 FIGURE31 I8-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS=, BGR= ) 87 FIGURE32 I8-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS=, BGR= ) 88 FIGURE 33 I8-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS= 1, BGR= 1 ) 89 FIGURE 34 GRAM ACCESS WINDOW MAP 9 FIGURE 35 GRAYSCALE VOLTAGE GENERATION 91 FIGURE 36 GRAYSCALE VOLTAGE ADJUSTMENT 92 FIGURE 37 GAMMA CURVE ADJUSTMENT 93 FIGURE 38 EXAMPLE OF RMP(N)~5 DEFINITION 95 FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM 98 FIGURE 4 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL 98 FIGURE 41 POWER SUPPLY CIRCUIT BLOCK 99 FIGURE 42 DISPLAY ON/OFF REGISTER SETTING SEQUENCE 11 Page 5 of 113 Version: 19

6 FIGURE 43 STANDBY/SLEEP MODE REGISTER SETTING SEQUENCE 12 FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE 13 FIGURE 45 VOLTAGE CONFIGURATION DIAGRAM 14 FIGURE 46 VOLTAGE OUTPUT TO TFT LCD PANEL 15 FIGURE 47 PARTIAL DISPLAY EXAMPLE 16 FIGURE 48 I8-SYSTEM BUS TIMING 19 FIGURE5 RGB INTERFACE TIMING 111 Page 6 of 113 Version: 19

7 1 Introduction a-si TFT LCD Single Chip Driver is a 262,144-color one-chip SoC driver for a-tft liquid crystal display with resolution of 24RGBx32 dots, comprising a 72-channel source driver, a 32-channel gate driver, 172,8 bytes RAM for graphic data of 24RGBx32 dots, and power supply circuit has four kinds of system interfaces which are i8-system MPU interface (8-/9-/16-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, DB[17:]), serial data transfer interface (SPI), RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, DB[17:]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 165V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where long battery life is a major concern Page 7 of 113 Version: 19

8 2 Features a-si TFT LCD Single Chip Driver Single chip solution for a liquid crystal QVGA TFT LCD display 24RGBx32-dot resolution capable with real 262,144 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 72-channel source driver and 32-channel gate driver Internal 172,8 bytes graphic RAM System interfaces i8 system interface with 8-/ 9-/16-/18-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:]) VSYNC interface (System interface + VSYNC) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 262,144 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LCD panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode deep stand by mode Low -power consumption architecture Low operating power supplies: IOVcc = 165V ~ 36 V (interface I/O) VCI = 25V ~ 36 V (analog) LCD Voltage drive: Source/VCOM power supply voltage DDVDH - GND = 45V ~ 6 VCL GND = -2V ~ -3V VCI VCL 6V Gate driver output voltage VGH - GND = 1V ~ 2V VGL GND = -5V ~ -15V Page 8 of 113 Version: 19

9 VGH VGL 3V VCOM driver output voltage VCOMH = (VCI+2)V ~ (DDVDH-2)V VCOML = (VCL+2)V ~ V VCOMH-VCOML 6V a-tft LCD storage capacitor: Cst only Page 9 of 113 Version: 19

10 nwr/scl nreset IOVCC IM[3:] ncs MPU 18-bit 16-bit 9-bit I/F Register Index DB[17:] SDO nrd SDI RS DOTCLK VSYNC HSYNC RGB SPI 18-bit 16-bit 18 (IR) Register Control TEST1 I/F (CR) 7 Address Counter 18 TS[8:] TEST2 VSYNC I/F Operation Graphics 18 (AC) Source Driver LCD S[72:1] ENABLE TEST3 18 Latch Read Write Latch V63 18 VREG1OUT GND VCC Regulator Graphics (GRAM) RAM18 Grayscale Reference ~ Voltage VGS VDDD DUMMY2~27 DUMMY1~15 RC-OSC Controller Timing Driver LCD Gate G[32:1] VCI1 GND Charge-pump Power Circuit VCOM C1AC1BDVDHC12AC12B VCL C2AC2BVGHVGL Generator VCOM C13AC13B C21AC21B VCOMH VCOML 3 Block Diagram Page 1 of 113 Version: 19

11 4 Pin Descriptions Pin Name I/O Type Descriptions Input Interface Select the MPU system interface mode IM3 IM2 IM1 IM MPU-Interface Mode DB Pin in use Setting invalid 1 Setting invalid 1 i8-system 16-bit interface DB[17:1], DB[8:1] 1 1 i8-system 8-bit interface DB[17:1] IM3, IM2, IM1, IM/ID I IOVcc 1 ID Serial Peripheral Interface (SPI) SDI, SDO 1 1 * Setting invalid 1 Setting invalid 1 1 i8-system 16-bit interface DB[15:] 1 1 i8-system 18-bit interface DB[17:] i8-system 9-bit interface DB[17:9] 1 1 * * Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code ID setting A chip select signal ncs I MPU IOVcc Low: the is selected and accessible High: the is not selected and not accessible Fix to the GND level when not in use A register select signal RS I MPU IOVcc Low: select an index or status register High: select a control register Fix to either IOVcc or GND level when not in use A write strobe signal and enables an operation to write data when the signal is low nwr/scl I MPU IOVcc Fix to either IOVcc or GND level when not in use SPI Mode: Synchronizing clock signal in SPI mode nrd I MPU IOVcc A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GND level when not in use nreset I MPU IOVcc A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SDI I MPU IOVcc SPI interface input pin The data is latched on the rising edge of the SCL signal SDO O MPU IOVcc SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SDO as floating when not used An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: DB[17:1] is used 9-bit I/F: DB[17:9] is used 16-bit I/F: DB[17:1] and DB[8:1] is used DB[17:] I/O MPU IOVcc 18-bit I/F: DB[17:] is used 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: DB[17:12] are used 16-bit RGB I/F: DB[17:13] and DB[11:1] are used 18-bit RGB I/F: DB[17:] are used Unused pins must be fixed to GND level ENABLE I MPU IOVcc Data ENEABLE signal for RGB interface operation Low: Select (access enabled) Page 11 of 113 Version: 19

12 DOTCLK VSYNC HSYNC FMARK Pin Name I/O Type Descriptions I I I O MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc S72~S1 O LCD G32~G1 O LCD VCOM VCOMH VCOML VGS VCI VCC VCI1 DDVDH VGH VGL VCL O O O I I I O O O O O TFT common electrode Stabilizing capacitor Stabilizing capacitor GND or external resistor Power supply Power supply Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal Fix to either IOVcc or GND level when not in use Dot clock signal for RGB interface operation DPL = : Input data on the rising edge of DOTCLK DPL = 1 : Input data on the falling edge of DOTCLK Fix to the GND level when not in use Frame synchronizing signal for RGB interface operation VSPL = : Active low VSPL = 1 : Active high Fix to the GND level when not in use Line synchronizing signal for RGB interface operation HSPL = : Active low HSPL = 1 : Active high Fix to the GND level when not in use Output a frame head pulse signal The FMARK signal is used when writing RAM data in synchronization with frame Leave the pin open when not in use LCD Driving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S1 SS = 1, the data in the RAM address h is output from S72 S1, S4, S7, display red (R), S2, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels The high level of VCOM AC voltage Connect to a stabilizing capacitor The low level of VCOM AC voltage Adjust the VCOML level with the VDV bits Connect to a stabilizing capacitor Reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor Charge-pump and Regulator Circuit A supply voltage to the analog circuit Connect to an external power supply of 25 ~ 36V A supply voltage to the digital circuit Connect to an external power supply of 25 ~ 36V An internal reference voltage for the step-up circuit1 The amplitude between VCI and GND is determined by the VC[2:] bits Make sure to set the VCI1 voltage so that the DDVDH, VGH and VGL voltages are set within the respective specification Power supply for the source driver and Vcom drive Power supply for the gate driver Power supply for the gate driver VCOML driver power supply VCL = 5 ~ VCI Place a stabilizing capacitor between GND C11A, C11B I/O Step-up Capacitor connection pins for the step-up circuit 1 Page 12 of 113 Version: 19

13 Pin Name I/O Type Descriptions C12A, C12B capacitor C13A, C13B Step-up C21A, C21B I/O capacitor C22A, C22B Capacitor connection pins for the step-up circuit 2 Output voltage generated from the reference voltage VREG1OUT I/O Stabilizing The voltage level is set with the VRH bits capacitor VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREG1OUT = 3 ~ (DDVDH 5)V Power Pads A supply voltage to the interface pins: IOVCC I IM[3:], nreset, ncs, nwr, nrd, RS, DB[17:], VSYNC, HSYNC, DOTCLK, Power ENABLE, SCL, SDI, SDO supply IOVcc = 165 ~ 36V In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise VDD O Power Digital circuit power pad Connect these pins with the 1uF capacitor DGND I Power DGND for the digital side: DGND = V In case of COG, connect to GND on the FPC supply to prevent noise AGND I Power AGND for the analog side: AGND = V In case of COG, connect to GND on the FPC supply to prevent noise VGMMA1, 62 O - Test pad Leave these pins as open VGLDMY1~4 O Unused gate lines Connect unused gate lines to fix the level at VGL Test Pads DUMMY3, 5~27,3, Dummy pad Leave these pins as open Short circuited within the chip for COG contact resistance measurement DUMMYR DUMMYR1,2, 28, pins are short circuited as below: DUMMYR1 and DUMMYR29 DUMMYR2 and DUMMYR28 DUMMY - - Dummy pad and no output (no gold bump) IOVCCDUM O Connect unused interface and test pins to these pins on the glass to fix voltage AGNDDUM1~6 O - levels Leave open when not used DGNDDUM1~7 O - TESTO1~16 O Open Test pins Leave them open TEST1, 2, 3 I IOGND Test pins (internal pull low) Connect to GND or leave these pins as open TS~8 I OPEN Test pins (internal pull low) Leave them open TSO O OPEN Test pins Leave it open or short to ground TEST_EN I OPEN Test pins Leave it open or short to ground Page 13 of 113 Version: 19

14 Liquid crystal power supply specifications Table 1 No Item Description 1 TFT Source Driver 72 pins (24 x RGB) 2 TFT Gate Driver 32 pins 3 TFT Display s Capacitor Structure Cst structure only (Common VCOM) S1 ~ S72 V ~ V63 grayscales 4 Liquid Crystal Drive Output G1 ~ G32 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes 5 Input Voltage IOVcc 165 ~ 36V VCI 25 ~ 36V DDVDH 45V ~ 6V VGH 1V ~ 2V 6 Liquid Crystal Drive Voltages VGL -5V ~ -15V VCL -19V ~ -3V VGH - VGL Max 3V VCI - VCL Max 6V DDVDH VCI1 x2 7 Internal Step-up Circuits VGH VCI1 x4, x5, x6 VGL VCI1 x-3, x-4, x-5 VCL VCI1 x-1 Page 14 of 113 Version: 19

15 Chip 5 Pad Pad Location: Size: thickness 188um : 28 um x 68um (typ) Arrangement Pad Center and Coordination Coordinate Au bump Bump height: Size: Origin: 12um Chip (typ) center DGNDDUM1 DUMMYR um 5um Output Input x Pads to 94um DUMMYR2 TESTO1 TESTO2 TESTO3 8um panel TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 LEDPWM LEDPWM TESTO9 TESTO1 TESTO11 TESTO12 DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND TESTO13 TESTO14 DGNDDUM2 IM /ID IM1 IM2 IM3 IOVCCDUM TESTO15 TESTO16 TEST3 TEST2 TEST1 DGNDDUM3 FMARK VSYNC HSYNC DOTCLK ENABLE TEST_EN DB[17] DB[16] DB[15] TS[8] TS[7] DB[14] DB[13] DB[12] TS[6] TS[5] DB[11] DB[1] DB[9] IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC a-si TFT LCD Single Chip Driver Bump View DB[8] DB[7] DB[6] TS[4] TS[3] DB[5] DB[4] DB[3] TS[2] TS[1] DB[2] DB[1] DB[] TS[] TSO DGNDDUM5 ncs RS nwr/scl nrd nreset SDO SDI DGNDDUM6 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DGNDDUM7 VCC VCC VCC VCC VCC VCC VDD VDD VDD VDD VDD VDD VDD VDD DGND DGND DGND DGND DGND DGND DGND DGND VGS AGND AGND AGND AGND AGND AGND AGND AGND VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOM VCOM VCOM VCOM VCOM VCOM VCOML VCOML VCOML VCOML VCOML VCOML VCOML C11A C11A C11A C11A C11A C11B C11B C11B C11B C11B C12B C12B C12B C12B C12B C12A C12A C12A C12A C12A DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH DUMMY1 VREG1OUT DUMMY11 DUMMY12 AGNDDUM1 AGNDDUM2 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI1 VCI VCI VCI VCI VCI VCI VCI VCI VCI AGNDDUM3 VGH VGH VGH VGH VGH VGH AGNDDUM4 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNDDUM5 VCL VCL VCL VCL C13B C13B C13B C13B C13A C13A C13A C13A AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND C21B C21B C21B C21A C21A C21A C22B C22B C22B C22A C22A C22A DUMMY 13 DUMMY 14 DUMMY 15 DUMMY 16 DUMMY 17 AGNDDUM Face Up (Bump View) x y S35 (,) DUM M Y31 DUM M Y3 DUM M YR2 9 DUM M YR2 8 VGL DM Y4 G2 G4 G6 G8 G 31 6 G 34 8 G 32 VGLDM Y 3 DUM M Y27 DUM M Y26 DUM M Y25 S1 S2 S3 S4 8 S35 9 S36 VGM M A1 VGM M A62 S36 1 S36 2 S36 3 S71 7 S71 8 S71 9 S72 DUM M Y24 DUM M Y23 DUM M Y22 VGL DM Y2 G31 9 G31 7 G31 5 G7 G5 G3 G1 VGL DM Y1 DUM M Y21 DUM M Y2 DUM M Y19 DUM M Y18 Page 15 of 113 Version: 19

16 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1 DGNDDUM IOVCC VGS DUMMYR IOVCC AGND DUMMYR IOVCC AGND TESTO[1] IOVCC AGND TESTO[2] IOVCC AGND TESTO[3] IOVCC AGND TESTO[4] IOVCC AGND TESTO[5] IOVCC AGND TESTO[6] DB[8] AGND TESTO[7] DB[7] VCOMH TESTO[8] DB[6] VCOMH DUMMY TS[4] VCOMH DUMMY TS[3] VCOMH TESTO[9] DB[5] VCOMH TESTO[1] DB[4] VCOMH TESTO[11] DB[3] VCOM TESTO[12] TS[2] VCOM DGND TS[1] VCOM DGND DB[2] VCOM DGND DB[1] VCOM DGND DB[] VCOM DGND TS[] VCOML DGND TSO VCOML DGND DGNDDUM VCOML DGND ncs VCOML DGND RS VCOML DGND nwr/scl VCOML TESTO[13] nrd VCOML TESTO[14] nreset C11A DGNDDUM SDO C11A IM/ID SDI C11A IM DGNDDUM C11A IM DUMMY C11A IM DUMMY C11B IOVCCDUM DUMMY C11B TESTO[15] DUMMY C11B TESTO[16] DUMMY C11B TEST DGNDDUM C11B TEST VCC C12B TEST VCC C12B DGNDDUM VCC C12B FMARK VCC C12B VSYNC VCC C12B HSYNC VCC C12A DOTCLK VDD C12A ENABLE VDD C12A TEST_EN VDD C12A DB[17] VDD C12A DB[16] VDD DDVDH DB[15] VDD DDVDH TS[8] VDD DDVDH TS[7] VDD DDVDH DB[14] DGND DDVDH DB[13] DGND DDVDH DB[12] DGND DDVDH TS[6] DGND DDVDH TS[5] DGND DDVDH DB[11] DGND DDVDH DB[1] DGND DUMMY DB[9] DGND VREG1OUT Page 16 of 113 Version: 19

17 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 181 DUMMY AGND G[71] DUMMY AGND G[73] AGNDDUM C21B G[75] AGNDDUM C21B G[77] VCI C21B G[79] VCI C21A G[81] VCI C21A G[83] VCI C21A G[85] VCI C22B G[87] VCI C22B G[89] VCI C22B G[91] VCI C22A G[93] VCI C22A G[95] VCI C22A G[97] VCI DUMMY G[99] VCI DUMMY G[11] VCI DUMMY G[13] VCI DUMMY G[15] VCI DUMMY G[17] VCI AGNDDUM G[19] VCI DUMMY G[111] AGNDDUM DUMMY G[113] VGH DUMMY G[115] VGH DUMMY G[117] VGH VGLDMY G[119] VGH G[1] G[121] VGH G[3] G[123] VGH G[5] G[125] AGNDDUM G[7] G[127] VGL G[9] G[129] VGL G[11] G[131] VGL G[13] G[133] VGL G[15] G[135] VGL G[17] G[137] VGL G[19] G[139] VGL G[21] G[141] VGL G[23] G[143] VGL G[25] G[145] VGL G[27] G[147] AGNDDUM G[29] G[149] VCL G[31] G[151] VCL G[33] G[153] VCL G[35] G[155] VCL G[37] G[157] C13B G[39] G[159] C13B G[41] G[161] C13B G[43] G[163] C13B G[45] G[165] C13A G[47] G[167] C13A G[49] G[169] C13A G[51] G[171] C13A G[53] G[173] AGND G[55] G[175] AGND G[57] G[177] AGND G[59] G[179] AGND G[61] G[181] AGND G[63] G[183] AGND G[65] G[185] AGND G[67] G[187] AGND G[69] G[189] Page 17 of 113 Version: 19

18 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 361 G[191] G[311] S[669] G[193] G[313] S[668] G[195] G[315] S[667] G[197] G[317] S[666] G[199] G[319] S[665] G[21] VGLDMY S[664] G[23] DUMMY S[663] G[25] DUMMY S[662] G[27] DUMMY S[661] G[29] S[72] S[66] G[211] S[719] S[659] G[213] S[718] S[658] G[215] S[717] S[657] G[217] S[716] S[656] G[219] S[715] S[655] G[221] S[714] S[654] G[223] S[713] S[653] G[225] S[712] S[652] G[227] S[711] S[651] G[229] S[71] S[65] G[231] S[79] S[649] G[233] S[78] S[648] G[235] S[77] S[647] G[237] S[76] S[646] G[239] S[75] S[645] G[241] S[74] S[644] G[233] S[73] S[643] G[245] S[72] S[642] G[247] S[71] S[641] G[249] S[7] S[64] G[251] S[699] S[639] G[253] S[698] S[638] G[255] S[697] S[637] G[257] S[696] S[636] G[259] S[695] S[635] G[261] S[694] S[634] G[263] S[693] S[633] G[265] S[692] S[632] G[267] S[691] S[631] G[269] S[69] S[63] G[271] S[689] S[629] G[273] S[688] S[628] G[275] S[687] S[627] G[277] S[686] S[626] G[233] S[685] S[625] G[281] S[684] S[624] G[283] S[683] S[623] G[285] S[682] S[622] G[287] S[681] S[621] G[289] S[68] S[62] G[291] S[679] S[619] G[293] S[678] S[618] G[295] S[677] S[617] G[297] S[676] S[616] G[299] S[675] S[615] G[31] S[674] S[614] G[33] S[673] S[613] G[35] S[672] S[612] G[37] S[671] S[611] G[39] S[67] S[61] Page 18 of 113 Version: 19

19 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 541 S[69] S[549] S[489] S[68] S[548] S[488] S[67] S[547] S[487] S[66] S[546] S[486] S[65] S[545] S[485] S[64] S[544] S[484] S[63] S[543] S[483] S[62] S[542] S[482] S[61] S[541] S[481] S[6] S[54] S[48] S[599] S[539] S[479] S[598] S[538] S[478] S[597] S[537] S[477] S[596] S[536] S[476] S[595] S[535] S[475] S[594] S[534] S[474] S[593] S[533] S[473] S[592] S[532] S[472] S[591] S[531] S[471] S[59] S[53] S[47] S[589] S[529] S[469] S[588] S[528] S[468] S[587] S[527] S[467] S[586] S[526] S[466] S[585] S[525] S[465] S[584] S[524] S[464] S[583] S[523] S[463] S[582] S[522] S[462] S[581] S[521] S[461] S[58] S[52] S[46] S[579] S[519] S[459] S[578] S[518] S[458] S[577] S[517] S[457] S[576] S[516] S[456] S[575] S[515] S[455] S[574] S[514] S[454] S[573] S[513] S[453] S[572] S[512] S[452] S[571] S[511] S[451] S[57] S[51] S[45] S[569] S[59] S[449] S[568] S[58] S[448] S[567] S[57] S[447] S[566] S[56] S[446] S[565] S[55] S[445] S[564] S[54] S[444] S[563] S[53] S[443] S[562] S[52] S[442] S[561] S[51] S[441] S[56] S[5] S[44] S[559] S[499] S[439] S[558] S[498] S[438] S[557] S[497] S[437] S[556] S[496] S[436] S[555] S[495] S[435] S[554] S[494] S[434] S[553] S[493] S[433] S[552] S[492] S[432] S[551] S[491] S[431] S[55] S[49] S[43] Page 19 of 113 Version: 19

20 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 721 S[429] S[369] S[311] S[428] S[368] S[31] S[427] S[367] S[39] S[426] S[366] S[38] S[425] S[365] S[37] S[424] S[364] S[36] S[423] S[363] S[35] S[422] S[362] S[34] S[421] S[361] S[33] S[42] VGMMA S[32] S[419] VGMMA S[31] S[418] S[36] S[3] S[417] S[359] S[299] S[416] S[358] S[298] S[415] S[357] S[297] S[414] S[356] S[296] S[413] S[355] S[295] S[412] S[354] S[294] S[411] S[353] S[293] S[41] S[352] S[292] S[49] S[351] S[291] S[48] S[35] S[29] S[47] S[349] S[289] S[46] S[348] S[288] S[45] S[347] S[287] S[44] S[346] S[286] S[43] S[345] S[285] S[42] S[344] S[284] S[41] S[343] S[283] S[4] S[342] S[282] S[399] S[341] S[281] S[398] S[34] S[28] S[397] S[339] S[233] S[396] S[338] S[278] S[395] S[337] S[277] S[394] S[336] S[276] S[393] S[335] S[275] S[392] S[334] S[274] S[391] S[333] S[273] S[39] S[332] S[272] S[389] S[331] S[271] S[388] S[33] S[27] S[387] S[329] S[269] S[386] S[328] S[268] S[385] S[327] S[267] S[384] S[326] S[266] S[383] S[325] S[265] S[382] S[324] S[264] S[381] S[323] S[263] S[38] S[322] S[262] S[379] S[321] S[261] S[378] S[32] S[26] S[377] S[319] S[259] S[376] S[318] S[258] S[375] S[317] S[257] S[374] S[316] S[256] S[373] S[315] S[255] S[372] S[314] S[254] S[371] S[313] S[253] S[37] S[312] S[252] Page 2 of 113 Version: 19

21 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 91 S[251] S[191] S[131] S[25] S[19] S[12] S[249] S[189] S[129] S[248] S[188] S[128] S[247] S[187] S[127] S[246] S[186] S[126] S[245] S[185] S[125] S[244] S[184] S[124] S[233] S[183] S[123] S[242] S[182] S[122] S[241] S[181] S[121] S[24] S[18] S[12] S[239] S[179] S[119] S[238] S[178] S[118] S[237] S[177] S[117] S[236] S[176] S[116] S[235] S[175] S[115] S[234] S[174] S[114] S[233] S[173] S[113] S[232] S[172] S[112] S[231] S[171] S[111] S[23] S[17] S[11] S[229] S[169] S[19] S[228] S[168] S[18] S[227] S[167] S[17] S[226] S[12] S[16] S[225] S[165] S[15] S[224] S[164] S[14] S[223] S[163] S[13] S[222] S[162] S[12] S[221] S[161] S[11] S[22] S[16] S[1] S[219] S[159] S[99] S[218] S[158] S[98] S[217] S[157] S[97] S[216] S[156] S[96] S[215] S[155] S[95] S[214] S[154] S[94] S[213] S[153] S[93] S[212] S[152] S[92] S[211] S[151] S[91] S[21] S[15] S[9] S[29] S[149] S[89] S[28] S[148] S[88] S[27] S[147] S[87] S[26] S[146] S[86] S[25] S[145] S[85] S[24] S[144] S[84] S[23] S[143] S[83] S[22] S[142] S[82] S[21] S[141] S[81] S[2] S[14] S[8] S[199] S[139] S[79] S[198] S[138] S[78] S[197] S[137] S[77] S[196] S[136] S[76] S[195] S[135] S[75] S[194] S[134] S[74] S[193] S[133] S[73] S[192] S[132] S[72] Page 21 of 113 Version: 19

22 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 181 S[71] S[11] G[23] S[7] S[1] G[228] S[69] S[9] G[226] S[68] S[8] G[224] S[67] S[7] G[222] S[66] S[6] G[22] S[65] S[5] G[218] S[64] S[4] G[216] S[63] S[3] G[214] S[62] S[2] G[212] S[61] S[1] G[21] S[6] DUMMY G[28] S[59] DUMMY G[26] S[58] DUMMY G[24] S[57] VGLDMY G[22] S[56] G[32] G[2] S[55] G[318] G[198] S[54] G[316] G[196] S[53] G[314] G[194] S[52] G[312] G[192] S[51] G[31] G[19] S[5] G[38] G[188] S[49] G[36] G[186] S[48] G[34] G[184] S[47] G[32] G[182] S[46] G[3] G[18] S[45] G[298] G[178] S[44] G[296] G[176] S[43] G[294] G[174] S[42] G[292] G[172] S[41] G[29] G[17] S[4] G[288] G[168] S[39] G[286] G[12] S[38] G[284] G[164] S[37] G[282] G[162] S[36] G[28] G[16] S[35] G[278] G[158] S[34] G[276] G[156] S[33] G[274] G[154] S[32] G[272] G[152] S[31] G[27] G[15] S[3] G[268] G[148] S[29] G[266] G[146] S[28] G[264] G[144] S[27] G[262] G[142] S[26] G[26] G[14] S[25] G[258] G[138] S[24] G[256] G[136] S[23] G[254] G[134] S[22] G[252] G[132] S[21] G[25] G[12] S[2] G[248] G[128] S[19] G[246] G[126] S[18] G[244] G[124] S[17] G[242] G[122] S[16] G[24] G[12] S[15] G[238] G[118] S[14] G[236] G[116] S[13] G[234] G[114] S[12] G[232] G[112] Page 22 of 113 Version: 19

23 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1261 G[11] G[7] G[3] G[18] G[68] G[28] G[16] G[66] G[26] G[14] G[64] G[24] G[12] G[62] G[22] G[1] G[6] G[2] G[98] G[58] G[18] G[96] G[56] G[16] G[94] G[54] G[14] G[92] G[52] G[12] G[9] G[5] G[1] G[88] G[48] G[8] G[86] G[46] G[6] G[84] G[44] G[4] G[82] G[42] G[2] G[8] G[4] VGLDMY G[78] G[38] DUMMYR G[76] G[36] DUMMYR G[74] G[34] DUMMY G[72] G[32] DUMMY Page 23 of 113 Version: 19

24 S1 ~ S72 G1 ~ G32 DUMMY18~31 VGMMA1, 62 VGLDMY1~4 I/O Pads 25 Alignment mark a-si TFT LCD Single Chip Driver Unit: um Pad Pump Min 7 Unit: um Pad Pump Alignment Mark: 1 (Left) 5 Alignment Mark: 2 (Right) 5 Alignment mark X Y Page 24 of 113 Version: 19

25 6 Block Description MPU System Interface supports three system high-speed interfaces: i8-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR) The IR is the register to store index information from control registers and the internal GRAM The WDR is the register to temporarily store data to be written to control registers and the internal GRAM The RDR is the register to temporarily store data read from the GRAM Data from the MPU to be written to the internal GRAM are first written to the WDR and then automatically written to the internal GRAM in internal operation Data are read via the RDR from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time Registers selection by system interface (8-/9-/16-/18-bit bus width) I8 Function RS nwr nrd Write an index to IR register 1 Write to control registers or the internal GRAM by WDR register 1 1 Read from the internal GRAM by RDR register 1 1 Registers selection by the SPI system interface Function R/W RS Write an index to IR register Write to control registers or the internal GRAM by WDR register 1 Read from the internal GRAM by RDR register 1 1 Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK In RGB interface mode, data (DB17-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal Display data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External Display Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Page 25 of 113 Version: 19

26 Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus 1 The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 172,8 (24 x 32x 18/8) bytes with 18 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,144 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an internal oscillation resistor The frame rate is adjusted by the register setting LCD Driver Circuit The LCD driver circuit of consists of a 72-output source driver (S1 ~ S72) and a 32-output gate driver (G1~G32) Display pattern data are latched when the 72 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 72 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LCD module LCD Driver Power Supply Circuit The LCD drive power supply circuit generates the voltage levels VREG1OUT, VGH, VGL and Vcom for driving an LCD Page 26 of 113 Version: 19

27 7 System Interface 71 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, DOTCLK and data bus DB[17:] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode RAM Access Setting (RM) Display Operation Mode (DM[1:]) Internal operating clock only (Displaying still pictures) RGB interface (1) (Displaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (Displaying moving pictures) System interface (RM = ) RGB interface (RM = 1) System interface (RM = ) System interface (RM = ) Internal operating clock (DM[1:] = ) RGB interface (DM[1:] = 1) RGB interface (DM[1:] = 1) VSYNC interface (DM[1:] = 1) Note 1) Registers are set only via the system interface Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 27 of 113 Version: 19

28 System System Interface 18/16/6 ncs RS nwr nrd DB[17:] RGB Interface EN ABLE VSYNC HSYNC DOTCLK Figure1 System Interface and RGB Interface connection 72 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting registers and GRAM access IM3 IM2 IM1 IM MPU-Interface Mode DB Pin in use Setting invalid 1 Setting invalid 1 i8-system 16-bit interface DB[17:1], DB[8:1] 1 1 i8-system 8-bit interface DB[17:1] 1 ID Serial Peripheral Interface (SPI) SDI, SDO 1 1 * Setting invalid 1 Setting invalid 1 1 i8-system 16-bit interface DB[15:] 1 1 i8-system 18-bit interface DB[17:] i8-system 9-bit interface DB[17:9] 1 1 * * Setting invalid Page 28 of 113 Version: 19

29 721 i8/18-bit System Interface The i8/18-bit system interface is selected by setting the IM[3:] as 11 levels 18-bit System Interface 17DB ( K 16DB 15DB colors) 14DB TRI=, 13DB 12DB DFM[1:]= 11DB 1DB ]= Write Input 9DB 8DB 7DB 6DB 5DB 4DB 3DB 2DB 1DB Register Data GRAM Data & R5R4R3R2R1RG5G4 17WD 16WD 15WD 14WD 13WD 12WD 11WD 1WD RGB Mapping G3 9WD G2G1GB5B4B3B2B1 8WD 7WD 6WD 5WD 4WD 3WD 2WD 1WD B System ncs A2 nwr nrd D[31:] 18 ncs RS nwr nrd DB[17:] Figure2 18-bit System Interface Data Format Page 29 of 113 Version: 19

30 a-si TFT LCD Single Chip Driver TRIDFM 722 i8/16-bit System Interface (DB[15:]) The i8/16-bit system interface is selected by setting the IM[3:] as 11 levels The 262K or 65K color can be display through * 16-bit MPU System Interface Data Format the 16-bit MPU interface When the 262K color is displayed, two transfers (1 st transfer: 2 bits, 2 nd transfer: 16 bits R5 DB 15 or 1 st R4 DB 14 transfer: R3 DB 13R2 DB R1 DB 11 bits, R DB 1 2 nd G5 DB9 DB8 transfer: G41st Transfer G3DB7 2 bits) G2DB6 G1 are necessary G 5DB B5 4DB3 B4 for B3 DB2 DB the B2 116-bit B1 DB CPU B interface system 16-bit interface (1 transfers/pixel) 65,536 colors DB R5 15R4 14DB R3 13DB R2 12DB R1 11R DB 1G5 DB9 1st DB8 G4Transfer G3 7DB6 G2DB5 G1G 4DB B5 3DB2 B4B3 DB1 B2 DB 2nd B1 15Transfer B DB 14 8-system 16-bit interface (2 transfers/pixel) 262,144 colors 1 1 DB R5 1st Transfer R4 DB R3 15DB R2 14DB R1 13R DB 12G5 11DB1 G4G32nd DB8 G2Transfer DB7 G1G 6DB B5 5DB4 DB3 DB B2 2 DB1 B 8-system 16-bit interface (2 transfers/pixel) 262,144 colors 1 DB 9 DB TRIDFM 16-bit MPU System Interface Data Format 723 i8/16-bit System Interface (DB[17:1][8:1]) * DB R5 17R4 DB 16R3 DB 15R2 14DB R1 13R DB 12G5 DB 11G4 DB 11st Transfer G3G2 DB 8G1 DB7 G DB6 B5 5DB B4 4 DB3 DB2 DB1 B system 16-bit interface (1 transfers/pixel) 65,536 colors DB R5 17R4 DB 16R3 DB 15R2 14DB R1 13R DB 12G5 DB 111st G4 DB 1Transfer G3 DB 8G2 DB 7G1 DB6 G DB5 B5 4DB B4 3 DB2 DB1 2nd 17Transfer DB B 16 8-system 16-bit interface (2 transfers/pixel) 262,144 colors 1 1 1st DB R5 2 Transfer R4 DB1 R3 DB 17R2 16DB R1 15R DB 14G5 DB 13G4 DB 12G3 DB 112nd G2 DB 1Transfer G1 DB8 G DB7 B5 6DB B4 5B3 DB4 B2 DB3 DB2 B1DB B 1 8-system 16-bit interface (2 transfers/pixel) 262,144 colors The i8/16-bit system interface is selected by setting the IM[3:] as 1 levels The 262K or 65K color can be display through the 16-bit MPU interface When the 262K color is displayed, two transfers (1 st transfer: 2 bits, 2 nd transfer: 16 bits or 1 st transfer: 16 bits, 2 nd transfer: 2 bits) are necessary for the 16-bit CPU interface Figure3 16-bit System Interface Data Format Page 3 of 113 Version: 19

31 724 i8/9-bit System Interface (DB[17:9]) The i8/9-bit system interface is selected by setting the IM[3:] as 111 and the DB17~DB9 pins are used to transfer the data When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused DB[8:] pins must be tied to GND ncs 9-bit System A1 System 1st Transfer nwr Input Interface 17DB ( K 16DB 15DB colors) 14DB TRI=, (Upper bits) nrd 13DBDFM D[8:] GRAM Write Register Data Data & RGB Mapping R5R4R3R2R1RG5G4 17WD 16WD 15WD 14WD 13WD G2G1GB5B4B3B2B1 ncs RS nwr 12DB DFM[1:]= 11DB 1DB ]= nrd 9 DB[17:9] 9 12WD 11WD 1WD G3 9WD 17DB 8WD 16DB 7WD 15DB 2nd 6WD 14DB Transfer 5WD 13DB (Lower 4WD 12DB bits) 3WD 11DB 2WD 1DB 1WD B 9 Figure4 9-bit System Interface Data Format 725 i8/8-bit System Interface (DB[17:1]) The i8/8-bit system interface is selected by setting the IM[3:] as 11 and the DB17~DB1 pins are used to transfer the data When writing the 16-bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 18 bits internally (see the figure below) and then written into GRAM The unused DB[9:] pins must be tied to GND Page 31 of 113 Version: 19

32 TRI DFM * system 1 8-system system 8-bit MPU System Interface Data Format a-si TFT LCD Single Chip Driver 17DB 16DB 15DB 14DB 13DB 12DB 11DB 1 17DB 16DB 15DB 14DB 13DB 12DB 11DB 1 R5R4R31st R2Transfer R1RG5G4G3G2G1G2nd B5Transfer 1st B4B3B2B1B DB R5 11Transfer R4 1DB R3 17DB R2 16DB R1 152nd DB R 14Transfer G5 13DB G4 12DB G3 11DB G2 1DB G1 17DB G 16DB B5 153rd DB B4 14Transfer B3 13DB B2 12DB B1 11DB B 1 R5 17DB R4 161st DB R3 15Transfer R2 14DB R1 13 R 12DB G5 17DB G4 162nd DB G3 15Transfer G2 14DB G1 13DB G 12DB B5 17DB B4 163rd DB B3 15Transfer B2 14DB B1 13DB B 12 8-bit interface (2 transfers/pixel) 65,536 colors 8-bit interface (3 transfers/pixel) 262,144 colors 8-bit interface (3 transfers/pixel) 262,144 colors Figure5 8-bit System Interface Data Format Page 32 of 113 Version: 19

33 73 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:] pins as 1x level The chip select pin (ncs), the serial transfer clock pin (SCL), the serial data input pin (SDI) and the serial data output pin (SDO) are used in SPI mode The ID pin sets the least significant bit of the identification code The DB[17:] pins, which are not used, must be tied to GND The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS =, either index write operation or status read operation is executed When RS = 1, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) Data is written when the R/W bit is and read back when the R/W bit is 1 After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are 16-bit format and receive the first and the second byte datat as the upper and the lower eight bits of the 16-bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start Device ID code RS R/W ID 1/ 1/ Note: ID bit is selected by setting the IM/ID pin RS and R/W Bit Function RS R/W Function Set an index register 1 Read a status 1 Write a register or GRAM data 1 1 Read a register or GRAM data Page 33 of 113 Version: 19

34 Serial a-si TFT LCD Single Chip Driver SPI Peripheral Interface for register access Register Input DataD15D14D13D12D11D1 DataIB 15IB 14IB 13IB 12IB 11IB 1IB9 D9 IB8 D8 IB7IB6IB5IB4IB3IB2IB1 D7 D6 D5 D4 D3 D2 D1 IB D Serial Input Peripheral Data Interface 65K colors Write GRAM Data 17WD D15D14D13D12D11D1D9 16WD 15WD 14WD 13WD 12WD 11WD 1WD D8 9WD D78WD D67WD D56WD D4 5WD D34WD D23WD D12WD D1WD RGB Data mappingr5r4r3r2r1rg5g4 Register G3G2G1GB5B4B3B2B1B Figure 6 Data Format of SPI Interface Page 34 of 113 Version: 19

35 (a) Basic data transmission through SPI ncs (Input) Start End SCL (Input) SDI (Input) ID RS RW D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Start Byte Index register, registers setting, and GRAM write SDO (Output) D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Status, registers read and GRAM read (b) Consecutive data transmission through SPI Start ncs (Input) SCL (Input) SDI (Input) Start Byte Register 1 upper eight bits Register 1 lower eight bits Register 2 upper eight bits Register 2 lower eight bits Note: The first byte after the start byte is always the upper eight bits Register 1 execution time (c) GRAM data read transmission ncs (Input) Start End SCL (Input) SDI (Input) Start Byte RS=1, RW=1 SDO (Output) Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read upper byte RAM read lower byte Note: Five bytes of invalid dummy data read after the start byte (d) Status/registers read transmission Start ncs (Input) End SCL (Input) SDI (Input) SDO (Output) Start Byte Register 1 upper eight bits Register 1 lower eight bits Note: One byte of invalid dummy data read after the start byte Figure7 Data transmission through serial peripheral interface (SPI) Page 35 of 113 Version: 19

36 (e) Basic data transmission through SPI ncs (Input) Start End SCL (Input) SDI (Input) ID RS RW D23 D22 D21 D12 D19 D18 D17 D16 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Start Byte GRAM data write SDO (Output) D23 D22 D21 D12 D19 D18 D17 D16 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D GRAM data read (f) GRAM data write transmission Start ncs (Input) End SCL (Input) SDI (Input) Start Byte RAM data 1 1st transfer RAM data 1 2nd transfer RAM data 1 3rd transfer RAM data 2 1st transfer RAM data 2 2nd transfer RAM data 2 3rd transfer SDO (Output) Note: Five bytes of invalid dummy data read after the start byte GRAM Data (1) execution time GRAM Data (2) execution time (g) GRAM data read transmission Start ncs (Input) End SCL (Input) SDI (Input) Start Byte RS=1, RW=1 SDO (Output) Dummy read 1 Dummy read 2 Dummy read 3 Dummy read 4 Dummy read 5 RAM read 1st byte RAM read 2nd byte RAM read 3rd byte Note: Five bytes of invalid dummy data read after the start byte RAM data transfer in SPI mode when TRI=1 and DFM[1:]=1 Figure8 Data transmission through serial peripheral interface (SPI), TRI= 1 and DFM= 1 ) Page 36 of 113 Version: 19

37 74 VSYNC Interface supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i8 system interface When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting DM[1:] = 1 and RM = VSYNC MPU ncs RS nwr DB[17:] Figure9 Data transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal All display data are stored in GRAM to minimize total data transfer required for moving picture display VSYNC Write data to RAM through system interface Display operation synchronized with internal clocks Rewriting screen data Rewriting screen data Figure1 Moving picture data transmission through VSYNC interface Page 37 of 113 Version: 19

38 VSYNC Back porch (14 lines) RAM Write Display operation Display (32 lines) Front porch (2 lines) Black period Figure11 Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula Internal clock frequency (fosc) [Hz] = FrameFrequency x (DisplayLine (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation Minimum RAM write speed ( HZ ) 24 x DisplayLines ( NL ) [( BackPorch ( BP )+ DisplayLines ( NL ) - margins ] x 16 ( clocks ) x 1 / fosc Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below [Example] Display size: 24 RGB 32 lines Lines: 32 lines (NL = 1111) Back porch: 14 lines (BP = 111) Front porch: 2 lines (FP = 1) Frame frequency: 6 Hz Frequency fluctuation: 1% Internal oscillator clock (fosc) [Hz] = 6 x [ ] x 16 clocks x (11/9) 394KHz Page 38 of 113 Version: 19

39 57 MHz When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration In the above example, the calculated internal clock frequency with ±1% margin variation is considered and ensures to complete the display operation within one VSYNC cycle The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation Minimum speed for RAM writing [Hz] > 24 x 32 x 394K / [ ( )lines x 16clocks] The above theoretical value is calculated based on the premise that the starts to write data into the internal GRAM on the falling edge of VSYNC There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed The GRAM write speed of 57MHz or more will guarantee the completion of GRAM write operation before the starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker Notes in using the VSYNC interface 1 The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration 2 The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display 3 When switching from the internal clock operation mode (DM[1:] = ) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, ie after completing the display of the frame 4 The partial display, vertical scroll functions are not available in VSYNC interface mode and set the AM bit to to transfer display data Page 39 of 113 Version: 19

40 System Interface Mode to VSYNC interface mode System Interface VSYNC interface mode to System Interface Mode Opeartion through VSYNC interface Set AM= Set GRAM Address Set DM[1:]=1, RM= for VSYNC interface mode Set index register to R22h Display operation in synchronization with internal clocks DM[1:], RM become enable after completion of displaying 1 frame Set DM[1:]=, RM= for system interface mode Wait more than 1 frame System Interface Display operation in synchronization with VSYNC DM[1:], RM become enable after completion of displaying 1 frame Display operation in synchronization with internal clocks Wait more than 1 frame Write data to GRAM through VSYNC interface Display operation in synchronization with VSYNC Note: input VSYNC for more than 1 frame period after setting the DM, RM register Opeartion through VSYNC interface Figure12 Transition flow between VSYNC and internal clock operation modes Page 4 of 113 Version: 19

41 75 RGB Input Interface The RGB Interface mode is available for and the interface is selected by setting the RIM[1:] bits as following table RIM1 RIM RGB Interface DB pins 18-bit 18-bit RGB Interface DB[17:] 1 16-bit RGB Interface DB[17:13], DB[11:1] 1 6-bit RGB Interface DB[17:12] Input RGB Interface ( K colors) 1 1 Setting prohibited GRAM Write Register Data Data & RGB Mapping R5R4R3R2R1RG5G4 17WD 17DB 16WD 16DB 15WD 15DB 14WD 14DB 13WD 13DB 12WD 12DB 11DB 11WD 1DB 1WD 9DB G3 9WD G2G1GB5B4B3B2B1 8WD 8DB 7WD 7DB 6WD 6DB 5WD 5DB 4DB 4WD 3WD 3DB 2WD 2DB 1WD 1DB B 16-bit Input RGB Interface (65 65K colors) GRAM Write Register Data Data & R5R4R3R2R1RG5G4 17WD 17DB 16WD 16DB 15WD 15DB 14WD 14DB 6-bit RGB RGB Mapping DB 11WD 1DB 1WD 9DB G3 9WD G2G1GB5B4B3B2B1 8WD 8DB 7WD 7DB 6WD 6DB 5WD 5DB 4DB 4WD 3WD 3DB 2WD 2DB 1 B Input Interface 17DB ( K 16DB colors) 1st Write Data 15DB Transfer 14DB 13DB Register 12 GRAM RGB Mapping Data & R5R4R3R2R1RG5G4 17WD 16WD 15WD 14WD 13WD 12WD 17DB 11WD 16DB 2nd 1WD 15DB Transfer G3 9WD 14DB G2G1GB5B4B3B2B1 8WD 13DB 7WD 12 6WD 17DB 5WD 16DB 3rd 4WD 15DB Transfer 3WD 14DB 2WD 13DB 1WD 12 B Figure13 RGB Interface Data Format Page 41 of 113 Version: 19

42 751 RGB Interface The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and DOTCLK signals The RGB interface transfers the updated data to GRAM and the update area is defined by the window address function The back porch and front porch are used to set the RGB interface timing VSYNC Back porch period (BP[3:]) RAM data display area Moving picture display area Display period (NL[4:] Front porch period (FP[3:]) HSYNC DOTCLK ENABLE DB[17:] Note 1: Front porch period continues until the next input of VSYNC Note 2: Input DOTCLK throughout the operation Note 3: Supply the VSYNC, HSYNC and DOTCLK with frequency that can meet the resolution requirement of panel Figure14 GRAM Access Area by RGB Interface Page 42 of 113 Version: 19

43 752 RGB Interface Timing The timing chart of 18-/16-bit RGB interface mode is shown as follows 1 frame Back porch Front porch VSYNC VLW >= 1H HSYNC DOTCLK ENABLE DB[17:] HSYNC HLW >= 3 DOTCLK // 1H DOTCLK // DTST >= HLW ENABLE // DB[17:] Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time Note 1: Use the high speed write mode (HWM=1) to write data through the RGB interface Figure15 Timing Chart of Signals in 18-/16-bit RGB Interface Mode Page 43 of 113 Version: 19

44 The timing chart of 6-bit RGB interface mode is shown as follows 1 frame Back porch Front porch VSYNC VLW >= 1H HSYNC DOTCLK ENABLE DB[17:12] HSYNC HLW >= 3 DOTCLK // 1H DOTCLK // DTST >= HLW ENABLE // DB[17:12] R G B R G B // B R G B Valid data VLW: VSYNC low period HLW: HSYNC low period DTST: data transfer startup time Note 1) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with DOTCLKs Note 2) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of DOTCLKs Figure16 Timing chart of signals in 6-bit RGB interface mode Page 44 of 113 Version: 19

45 753 Moving Picture Mode has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture The window address function defined the update area of GRAM Only the moving picture area of GRAM is updated When display the moving picture in RGB interface mode, the DB[17:] can be switched as system interface to update still picture area and registers, such as icons RAM access via a system interface in RGB-I/F mode allows GRAM access via the system interface in RGB interface mode In RGB interface mode, data are written to the internal GRAM in synchronization with DOTCLK and ENABLE signals When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = ) and the still picture of GRAM When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = 1 and the index register to R22h to start accessing RAM via the RGB interface If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM The following figure illustrates the operation of the when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface Still Picture Area Moving Picture Area Update a frame Update a frame VSYNC ENABLE DOTCLK DB[17:] Set IR to R22h Update moving picture area Set RM= Set AD[15:] Set IR to R22h Update display data in other than the moving picture area Set AD[15:] Set RM=1 Set IR to R22h Update moving picture area Figure17 Example of update the still and moving picture Page 45 of 113 Version: 19

46 754 6-bit RGB Interface The 6-bit RGB interface is selected by setting the RIM[1:] bits to 1 The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals Display data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus (DB[17:12]) according to the data enable Input RGB Data interface with 6-bit data bus signal (ENABLE) Unused pins (DB[11:]) must be fixed at GND level Registers can be set by the system interface (i8/spi) RGB Assignment R5R4R3R2R1RG5G4 17DB 16DB 15DB 14DB 13DB 12 17DB 16DB G3 15DB G2G1GB5B4B3B2B1 14DB 13DB 12DB 17DB 16DB 15DB 14DB 13DB B 12 1 st Transfer 2 nd Transfer 3 rd Transfer Data transfer synchronization in 6-bit RGB interface mode has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (ie on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of DOTCLK) HSYNC Accordingly, the number of DOTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly Otherwise it will affect the display of that frame as well as the next frame DOTCLK ENABLE DB[17:12] Transfer synchronization 1st2nd3rd1st2nd3rd1st2nd3rd1st2nd3rd Page 46 of 113 Version: 19

47 bit RGB Interface 16-bit Input RGB Interface (65 65K colors) enable signal (ENABLE) Registers are set only via the system interface GRAM Write Register Data Data & RGB Mapping R5R4R3R2R1RG5G4 17WD 17DB 16WD 16DB 15DB 15WD 14DB 14WD DB 11WD 1WD 1DB G3 9WD 9DB G2G1GB5B4B3B2B1 8WD 8DB 7WD 7DB 6WD 6DB 5WD 5DB 4DB 4WD 3DB 3WD 2WD 2DB 1 The 16-bit RGB interface is selected by setting the RIM[1:] bits to 1 The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals Display data are transferred to the internal RAM in synchronization with the display operation via 16-bit RGB data bus (DB17-13, DB11-1) according to the data B bit RGB Interface Input RGB 17DB 16DB 15DB 14DB 13DB 12DB 11DB 1DB 9DB 8DB 7DB 6DB 5DB 4DB 3DB 2DB 1DB signal (ENABLE) Registers are set only via the system interface RGB Assignment Data interface with 18-bit data bus R5R4R3R2R1RG5G4G3G2G1GB5B4B3B2B1B The 18-bit RGB interface is selected by setting the RIM[1:] bits to The display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals Display data are transferred to the internal RAM in synchronization with the display operation via 18-bit RGB data bus (DB[17:]) according to the data enable Notes in using the RGB Input Interface 1 The following are the functions not available in RGB Input Interface mode Function RGB interface I8 system interface Partial display Not available Available Scroll function Not available Available Interlaced scan Not available Not available Graphics operation function Not available Not available 2 VSYNC, HSYNC, and DOTCLK signals must be supplied throughout a display operation period 3 The periods set with the NO[1:] bits (gate output non-overlap period), STD[1:] bits (source output delay period) and EQ[1:] bits (equalization period) are not based on the internal clock but based on DOTCLK in Page 47 of 113 Version: 19

48 RGB interface mode 4 In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a DOTCLK input In other words, it takes 3 DOTCLK inputs to transfer one pixel Be sure to complete data transfer in units of 3 DOTCLK inputs in 6-bit RGB interface mode 5 In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of 3 DOTCLK Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE, DB[17:]) to contain DOTCLK inputs of a multiple of 3 to complete data transfer in units of pixels 6 When switching from the internal operation mode to the RGB Input Interface mode, or the other way around, follow the sequence below 7 In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame 8 In RGB interface mode, a RAM address (AD[15:]) is set in the address counter every frame on the falling edge of VSYNC interface Write data through RGB Figure18 Internal clock operation/rgb interface mode switching with RGB system Set DM[1:]=1, RGB Interface to write interface data through interface operation interface Write data to write through data system through RM= Set AD[15;] mode Write System RGB data interface system Interface to GRAM interface operation through (GRAM Set IR data to R22h Set AD[15;] Write data to GRAM write) with Set DM[1:]=1, RGB interface RM=1 mode system interface through (GRAM Set IR data to R22h RGB Interface operation write) System Interface operation Figure19 GRAM access between system interface and RGB interface Page 48 of 113 Version: 19

49 a-si TFT LCD Single Chip Driver 76 Interface Timing The following are diagrams of interfacing timing with LCD panel control signals in internal operation and RGB interface modes DOTCLK HSYNC VSYNC // ENABLE DB[17:] //// FLM G32 G1 G2 S[72:1] VCOM // Figure2 Relationship between RGB I/F signals and LCD Driving Signals for Panel Page 49 of 113 Version: 19

50 8 Register Descriptions 81 Registers Access a-si TFT LCD Single Chip Driver adopts 18-bit bus interface architecture for high-performance microprocessor All the functional blocks of starts to work after receiving the correct instruction from the external microprocessor by the 18-, 16-, 9-, 8-bit interface The index register (IR) stores the register address to which the instructions and display data will be written The register selection signal (RS), the read/write signals (nrd/nwr) and data bus D17- are used to read/write the instructions and data of The registers of the are categorized into the following groups 1 Specify the index of register (IR) 2 Read a status 3 Display control 4 Power management Control 5 Graphics data processing 6 Set internal GRAM address (AC) 7 Transfer data to/from the internal GRAM (R22) 8 Internal grayscale γ-correction (R3 ~ R39) Normally, the display data (GRAM) is most often updated, and in order since the can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function, there are fewer loads on the program in the microprocessor As the following figure Serial Peripheral Interface for register access shows, the way of assigning data to the 16 register bits (D[15:]) varies for each interface Send registers in accordance with the following data transfer format SPI Register Input DataD15D14D13D12D11D1 DataD15D14D13D12D11D1 D8 D8 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D9D9 D D Figure21 Register Setting with Serial Peripheral Interface (SPI) Page 5 of 113 Version: 19

51 i8/m68 Data a-si TFT LCD Single Chip Driver (DB[17:]) Bussystem 18-bit 17DB 16DB data 15DB bus 14DB interface 13DB 12DB 11DB 1DB 9DB 8DB 7DB 6DB 5DB 4DB 3DB 2DB 1DB Register (D[15:]) Bit D15D14D13D12D11D1D9D8 D7D6D5D4D3D2D1D i8/m68 Data (DB[17:1]), (DB[8:1]) system 16-bit 17DB 16DB data 15DB bus 14DB interface Register Bus 13DB 12DB 11DB 1 8DB 7DB 6DB 5DB 4DB 3DB 2DB (D[15:]) Bit D15D14D13D12D11D1D9D8 D7D6D5D4D3D2D1D 1 i8/m68 Data (DB[17:9]) Bussystem 9-bit 17DB 16DB data 15DB bus interface 14DB 1st Transfer Register Bit 13DB 12DB 11DB 1DB (D[15:]) D15D14D13D12D11D1D9D89 D7D6D5D4D3D2D1D 17DB 16DB 15DB 14DB 2nd Transfer 13DB 12DB 11DB 1DB 9 i8/m68 Data (DB[17:1]) Bussystem 8-bit 17DB 16DB data 15DB bus 1st interface/serial 14DB Transfer 13DB 12DB 11DB peripheral 1 interface (2/3 transmission) Register (D[15:]) Bit D15D14D13D12D11D1D9D8 D7D6D5D4D3D2D1D 17DB 16DB 15DB 2nd 14DB Transfer 13DB 12DB 11DB 1 Figure22 Register setting with i8 System Interface Page 51 of 113 Version: 19

52 i8 18-/16 16-bit System Bus Interface Timing a-si TFT LCD Single Chip Driver nwr DB[17:] nrd RS ncs (a) Write to register Write register index Write register data nwr DB[17:] nrd RS ncs (b) Read from register Write register index Read register data i8 9-/8-bit System Bus Interface Timing nwr DB[17:1] nrd RS ncs (a) Write to register (b) Read from register h Write register index high Write byte register data low Write byte register data nwr DB[17:1] nrd RS ncs h Write register index high Read byte register data low Read byte register data Figure 23 Register Read/Write Timing of i8 System Interface Page 52 of 113 Version: 19

53 82 Instruction Descriptions No Registers Name R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D IR Index Register W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID h Driver Code Read RO h Driver Output Control 1 W 1 SM SS 2h LCD Driving Control W 1 B/C 3h Entry Mode W 1 TRI DFM BGR ORG I/D1 I/D AM 5h 16 bits data format control W 1 EPF1 EPF 7h Display Control 1 W 1 PTDE1 PTDE BASEE GON DTE CL D1 D 8h Display Control 2 W 1 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP 9h Display Control 3 W 1 PTS1 PTS PTG1 PTG ISC3 ISC2 ISC1 ISC Ah Display Control 4 W 1 FMARKOE FMI2 FMI1 FMI Ch RGB Display Interface Control 1 W 1 ENC2 ENC1 ENC RM DM1 DM RIM1 RIM Dh Frame Maker Position W 1 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP Fh RGB Display Interface Control 2 W 1 VSPL HSPL EPL DPL 1h Power Control 1 W 1 SAP BT2 BT1 BT APE AP2 AP1 AP SLP STB 11h Power Control 2 W 1 DC12 DC11 DC1 DC2 DC1 DC VC2 VC1 VC 12h Power Control 3 W 1 VCIRE VRH3 VRH2 VRH1 VRH 13h Power Control 4 W 1 VDV4 VDV3 VDV2 VDV1 VDV 2h Horizontal GRAM Address Set W 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD 21h Vertical GRAM Address Set W 1 AD16 AD15 AD14 AD13 AD12 AD11 AD1 AD9 AD8 22h Write Data to GRAM W 1 RAM write data (WD17-) / read data (RD17-) bits are transferred via different data bus lines according to the selected interfaces 29h Power Control 7 W 1 VCM5 VCM4 VCM3 VCM2 VCM1 VCM 2Bh Frame Rate and Color Control W 1 FRS[3] FRS[2] FRS[1] FRS[] 3h Gamma Control 1 W 1 KP1[2] KP1[1] KP1[] KP[2] KP[1] KP[] 31h Gamma Control 2 W 1 KP3[2] KP3[1] KP3[] KP2[2] KP2[1] KP2[] 32h Gamma Control 3 W 1 KP5[2] KP5[1] KP5[] KP4[2] KP4[1] KP4[] 35h Gamma Control 4 W 1 RP1[2] RP1[1] RP1[] RP[2] RP[1] RP[] 36h Gamma Control 5 W 1 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[] VRP[3] VRP[2] VRP[1] VRP[] 37h Gamma Control 6 W 1 KN1[2] KN1[1] KN1[] KN[2] KN[1] KN[] 38h Gamma Control 7 W 1 KN3[2] KN3[1] KN3[] KN2[2] KN2[1] KN2[] 39h Gamma Control 8 W 1 KN5[2] KN5[1] KN5[] KN4[2] KN4[1] KN4[] 3Ch Gamma Control 9 W 1 RN1[2] RN1[1] RN1[] RN[2] RN[1] RN[] 3Dh Gamma Control 1 W 1 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[] VRN[3] VRN[2] VRN[1] VRN[] 5h Horizontal Address Start W 1 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA Page 53 of 113 Version: 19

54 No Registers Name R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Position 51h Horizontal Address End Position W 1 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA 52h Vertical Address Start Position W 1 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA 53h Vertical Address End Position W 1 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA 6h Driver Output Control 2 W 1 GS NL5 NL4 NL3 NL2 NL1 NL SCN5 SCN4 SCN3 SCN2 SCN1 SCN 61h Base Image Display Control W 1 NDL VLE REV 6Ah Vertical Scroll Control W 1 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL 8h Partial Image 1 Display Position W 1 PTDP8 PTDP7 PTDP6 PTDP5 PTDP4 PTDP3 PTDP2 PTDP1 PTDP 81h Partial Image 1 Area (Start Line) W 1 PTSA8 PTSA7 PTSA6 PTSA5 PTSA4 PTSA3 PTSA2 PTSA1 PTSA 82h Partial Image 1 Area (End Line) W 1 PTEA8 PTEA7 PTEA6 PTEA5 PTEA4 PTEA3 PTEA2 PTEA1 PTEA 83h Partial Image 2 Display Position W 1 PTDP18 PTDP17 PTDP16 PTDP15 PTDP14 PTDP13 PTDP12 PTDP11 PTDP1 84h Partial Image 2 Area (Start Line) W 1 PTSA18 PTSA17 PTSA16 PTSA15 PTSA14 PTSA13 PTSA12 PTSA11 PTSA1 85h Partial Image 2 Area (End Line) W 1 PTEA18 PTEA17 PTEA16 PTEA15 PTEA14 PTEA13 PTEA12 PTEA11 PTEA1 9h Panel Interface Control 1 W 1 DIVI1 DIVI RTNI4 RTNI3 RTNI2 RTNI1 RTNI 92h Panel Interface Control 2 W 1 NOWI2 NOWI1 NOWI 95h Panel Interface Control 4 W 1 DIVE1 DIVE 97h Panel Interface Control 5 W 1 NOWE3 NOWE2 NOWE1 NOWE A1h OTP VCM Programming Control W 1 OTP_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ PGM_EN OTP5 OTP4 OTP3 OTP2 OTP1 OTP A2h OTP VCM Status and Enable W 1 PGM_ PGM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ CNT1 CNT D5 D4 D3 D2 D1 D EN A5h OTP Programming ID Key W 1 KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY E6h Deep stand by mode control W 1 DSTB Page 54 of 113 Version: 19

55 821 Index (IR) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID The index register specifies the address of register (Rh ~ RFFh) or RAM which will be accessed 822 ID code (Rh) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D RO The device code 9335 h is read out when read this register 823 Driver Output Control (R1h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 SM SS Default SS: Select the shift direction of outputs from the source driver When SS =, the shift direction of outputs is from S1 to S72 When SS = 1, the shift direction of outputs is from S72 to S1 In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins To assign R, G, B dots to the source driver pins from S1 to S72, set SS = To assign R, G, B dots to the source driver pins from S72 to S1, set SS = 1 When changing SS or BGR bits, RAM data must be rewritten SM: Sets the gate driver pin arrangement in combination with the GS bit (R6h) to select the optimal scan mode for the module SM GS Scan Direction Gate Output Sequence G1 to G319 G2 to G32 G1, G2, G3, G4,,G316 G317, G318, G319, G32 Page 55 of 113 Version: 19

56 1 G1 to G319 G2 to G32 G32, G319, G318,, G6, G5, G4, G3, G2, G1 G1, G3, G5, G7,,G311 G313, G315, G317, G319 1 G1 to G319 G2 to G32 G2, G4, G6, G8,,G312 G314, G316, G318, G32 G32, G318, G316,, G1, G8, G6, G4, G2 1 1 G1 to G319 G2 to G32 G319, G317, G315,, G9, G78, G5, G3, G1 Page 56 of 113 Version: 19

57 824 LCD Driving Wave Control (R2h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 B/C Default B/C : Frame/Field inversion 1 : Line inversion 825 Entry Mode (R3h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 TRI DFM BGR ORG I/D1 I/D AM Default 1 1 AM Control the GRAM update direction When AM =, the address is updated in horizontal writing direction When AM = 1, the address is updated in vertical writing direction When a window area is set by registers R5h ~R53h, only the addressed GRAM area is updated based on I/D[1:] and AM bits setting I/D[1:] Horizontal I/D[1:] Control Vertical = the address : decrement : I/D[1:] Horizontal counter Vertical = (AC) to : 1 automatically decrement : increment I/D[1:] Horizontal increase Vertical = : 1 increment : decrementi/d[1:] Horizontal decrease by 1 Vertical = when update : 11 increment : one pixel display data Refer to the following figure for the details AM Horizontal = AM Vertical = 1 B E B E B B E B E E E B E B B E Figure24 GRAM Access Direction Setting ORG Moves the origin address according to the ID setting when a window address area is made This function is enabled when writing data with the window address area using high-speed RAM write ORG = : The origin address is not moved In this case, specify the address to start write operation according to the GRAM address map within the window address area ORG = 1 : The original address h moves according to the I/D[1:] setting Notes: 1 When ORG=1, only the origin address address h can be set in the RAM address set registers R2h, and R21h Page 57 of 113 Version: 19

58 2 In RAM read operation, make sure to set ORG= BGR Swap the R and B order of written data BGR= : Follow the RGB order to write the pixel data BGR= 1 : Swap the RGB data to BGR in writing into GRAM TRI When TRI = 1, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface It is also possible to send data via the 16-bit interface or SPI in the transfer mode that realizes display in 262k TRI colors in combination with DFM bits When not using these interface modes, be sure to set TRI = DFM DFM Set * the mode of 16-bit MPU System Interface Data Format transferring data to the internal RAM when TRI = 1 See the following figures for details R5 17DB R4 16DB R3 15DB R2 14DB R1 13DB R 12DB G5 11DB G4 1 1st Transfer G3DB G2 8DB G1 7DB G 6DB B5 5DB B4 4DB B3 3DB B2 2DB B1 1B system 16-bit interface (1 transfers/pixel) 65,536 colors 1 R5 17DB R4 16DB R3 15DB R2 14DB R1 13DB R 12DB G5 111st DB G4 1Transfer G3 8DB G2 7DB G1 6DB G 5DB B5 4DB B4 3DB B3 2DB B2 12nd DB B1 17Transfer DB B 16 8-system 16-bit interface (2 transfers/pixel) 262,144 colors 1 1 1st DB R5 2 Transfer R4 1DB R3 17DB R2 16DB R1 15DB R 14DB G5 13DB G4 12DB G3 112nd DB G2 1Transfer G1 8DB G 7DB B5 6DB B4 5DB B3 4DB B2 3DB B1 2DB B 1 8-system 16-bit interface (2 transfers/pixel) 262,144 colors Figure25 16-bit MPU System Interface Data Format Page 58 of 113 Version: 19

59 TRI DFM * system 1 8-system system 8-bit MPU System Interface Data Format a-si TFT LCD Single Chip Driver 17DB 16DB 15DB 14DB 13DB 12DB 11DB 1 17DB 16DB 15DB 14DB 13DB 12DB 11DB 1 R5R4R31st R2Transfer R1RG5G4G3G2G1G2nd B5Transfer 1st B4B3B2B1B DB R5 11Transfer R4 1DB R3 17DB R2 16DB R1 152nd DB R 14Transfer G5 13DB G4 12DB G3 11DB G2 1DB G1 17DB G 16DB B5 153rd DB B4 14Transfer B3 13DB B2 12DB B1 11DB B 1 R5 17DB R4 161st DB R3 15Transfer R2 14DB R1 13 R 12DB G5 17DB G4 162nd DB G3 15Transfer G2 14DB G1 13DB G 12DB B5 17DB B4 163rd DB B3 15Transfer B2 14DB B1 13DB B 12 8-bit interface (2 transfers/pixel) 65,536 colors 8-bit interface (3 transfers/pixel) 262,144 colors 8-bit interface (3 transfers/pixel) 262,144 colors Figure26 8-bit MPU System Interface Data Format Page 59 of 113 Version: 19

60 826 16bits Data Format Selection (R5h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 FPF1 EPF Default Data Bus DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB EPF= Frame Data R5 R4 R3 R2 R1 R G5 G4 G3 G2 G1 G B5 B4 B3 B2 B1 B Read Data DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB Data Bus DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB EPF=1 Frame Data R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 G B5 B4 B3 B2 B1 Read Data DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB Data Bus DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB EPF=1 Frame Data R5 R4 R3 R2 R1 1 G5 G4 G3 G2 G1 G B5 B4 B3 B2 B1 1 Read Data DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB Data Bus EPF=11 Frame Data DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB Condition Copy Condition Copy R5 R4 R3 R2 R1 R G5 G4 G3 G2 G1 G B5 B4 B3 B2 B1 B Read Data DB15 DB14 DB13 DB12 DB11 DB1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB Input data Green Data Green data = odd R/B Data R=B Green data = even R!= B By-pass G is copied to R/B Page 6 of 113 Version: 19

61 827 Display Control 1 (R7h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 PTDE1 PTDE BASEE GON DTE CL D1 D Default D[1:] Set D[1:]= 11 to turn on the display panel, and D[1:]= to turn off the display panel A graphics display is turned on the panel when writing D1 = 1, and is turned off when writing D1 = When writing D1 =, the graphics display data is retained in the internal GRAM and the displays the data when writing D1 = 1 When D1 =, ie while no display is shown on the panel, all source outputs becomes the GND level to reduce charging/discharging current, which is generated within the LCD while driving liquid crystal with AC voltage When the display is turned off by setting D[1:] = 1, the continues internal display operation When the display is turned off by setting D[1:] =, the internal display operation is halted completely In combination with the GON, DTE setting, the D[1:] setting controls display ON/OFF D1 D BASEE Source, VCOM Output internal operation GND Halt 1 1 GND Operate 1 Non-lit display Operate 1 1 Non-lit display Operate Base image display Operate Note: 1 data write operation from the microcontroller is performed irrespective of the setting of D[1:] bits 2 The D[1:] setting is valid on both 1 st and 2 nd displays 3 The non-lit display level from the source output pins is determined by instruction (PTS) CL When CL = 1, the 8-color display mode is selected CL 262, Colors GON and DTE Set the output level of gate driver G1 ~ G32 as follows GON DTE G1 ~G32 Gate Output VGH 1 VGH 1 VGL 1 1 Normal Display BASEE PTDE[1:] Base image display enable bit When BASEE =, no base image is displayed The drives liquid crystal at non-lit display level or displays only partial images When BASEE = 1, the base image is displayed The D[1:] setting has higher priority over the BASEE setting Page 61 of 113 Version: 19

62 Partial image 2 and Partial image 1 enable bits PTDE1/ = : turns off partial image Only base image is displayed PTDE1/ = 1: turns on partial image Set the base image display enable bit to (BASEE = ) 828 Display Control 2 (R8h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 FP7 FP6 FP5 FP4 FP3 FP2 FP1 FP BP7 BP6 BP5 BP4 BP3 BP2 BP1 BP Default 1 1 FP[7:]/BP[7:] FP[7:] /BP[7:] The FP[7:] and BP[7:] bits specify the line number of front and back porch periods respectively When setting the FP[7:] and BP[7:] value, the following conditions shall be met: BP + FP 256 lines FP 2 lines BP 2 lines Number of lines for Front Porch Number of lines for Back Porch h Setting Prohibited Setting Prohibited 1h Setting Prohibited Setting Prohibited 2h 2 lines 2 lines 3h 3 lines 3 lines 4h 4 lines 4 lines 5h 5 lines 5 lines 6h 6 lines 6 lines 7h 7 lines 7 lines 8h 8 lines 8 lines 9h 9 lines 9 lines Ah 1 lines 1 lines : : : 7Fh 127 lines 127 lines 8h 128 lines 128 lines 81h Setting Prohibited Setting Prohibited : : : FFh Setting Prohibited Setting Prohibited VSYNC Display Area Back Porch Front Porch Note: The output timing to the LCD is delayed by 2 lines period from the input of synchronizing signal Page 62 of 113 Version: 19

63 829 Display Control 3 (R9h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 PTS1 PTS PTG1 PTG ISC3 ISC2 ISC1 ISC Default ISC[3:]: Specify the scan cycle interval of gate driver in non-display area when PTG[1:]= 1 to select interval scan Then scan cycle is set as odd number from ~29 frame periods The polarity is inverted every scan cycle ISC3 ISC2 ISC1 ISC Scan Cycle f FLM=6 Hz frame - 1 frame frame 5ms frame 84ms 1 7 frame 117ms frame 15ms frame 184ms frame 217ms 1 15 frame 251ms frame 284ms frame 317ms frame 351ms frame 384ms frame 418ms frame 451ms frame 484ms PTG[1:] Set the scan mode in non-display area PTG1 PTG Gate outputs in non-display area Source outputs in non-display area Vcom output Normal scan Set with the PTS[1:] bits VcomH/VcomL 1 Setting Prohibited Interval scan Set with the PTS[1:] bits VcomH/VcomL 1 1 Setting Prohibited - - PTS[1:] Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays) When PTS[1] = 1, the operation of amplifiers which generates the grayscales other than V and V63 are halted PTS[1:] Source output level Grayscale amplifier Positive polarity Negative polarity in operation V63 V V63 to V 1 Setting Prohibited Setting Prohibited - 1 GND GND V63 to V 11 Hi-Z Hi-Z V63 to V Notes: 1 The power efficiency can be improved by halting grayscale amplifiers only in non-display drive period 2 The gate output level in non-lit display area drive period is determined by PTG[1:] Page 63 of 113 Version: 19

64 821 Display Control 4 (RAh) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 FMARKOE FMI2 FMI1 FMI Default FMI[2:] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate FMARKOE When FMARKOE=1, starts to output FMARK signal in the output interval set by FMI[2:] bits FMI[2:] Output Interval 1 frame 1 2 frame 11 4 frame 11 6 frame Others Setting disabled 8211 RGB Display Interface Control 1 (RCh) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 ENC2 ENC1 ENC RM DM1 DM RIM1 RIM Default RIM[1:] Select the RGB interface data width RIM1 RIM RGB Interface Mode 18-bit RGB interface (1 transfer/pixel), DB[17:] 1 16-bit RGB interface (1 transfer/pixel), DB[17:13] and DB[11:1] 1 6-bit RGB interface (3 transfers/pixel), DB[17:12] 1 1 Setting disabled Note1: Registers are set only by the system interface Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch DM[1:] Select the display operation mode DM1 DM Display Interface Internal system clock 1 RGB interface 1 VSYNC interface 1 1 Setting disabled The DM[1:] setting allows switching between internal clock operation mode and external display interface operation mode However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited RM Select the interface to access the GRAM Set RM to 1 when writing display data by the RGB interface RM Interface for RAM Access System interface/vsync interface 1 RGB interface Page 64 of 113 Version: 19

65 Display State Operation Mode RAM Access (RM) Display Operation Mode (DM[1:] Still pictures Internal clock operation System interface Internal clock operation (RM = ) (DM[1:] = ) Moving pictures RGB interface (1) RGB interface RGB interface (RM = 1) (DM[1:] = 1) Rewrite still picture area while RGB interface Displaying moving pictures System interface (RM = ) RGB interface (DM[1:] = 1) Moving pictures VSYNC interface System interface VSYNC interface (RM = ) (DM[1:] = 1) Note 1: Registers are set only via the system interface or SPI interface Note 2: Refer to the flowcharts of RGB Input Interface section for the mode switch ENC[2:] Set the GRAM write cycle through the RGB interface ENC[2:] GRAM Write Cycle (Frame periods) 1 Frame 1 2 Frames 1 3 Frames 11 4 Frames 1 5 Frames 11 6 Frames 11 7 Frames Frames 8212 Frame Marker Position (RDh) FMP BP+NL+FP period (1H) Make sure the 9 h R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP1 FMP Default EMP[8:] Sets the output position of frame cycle (frame marker) When FMP[8:]=, a high-active pulse FMARK is output at the start of back porch period for one display line FMP[8:] FMARK Output Position 9 h th line 9 h1 1 st line 9 h2 2 nd line 9 h3 3 rd line 9 h rd line 9 h th line 9 h th line Page 65 of 113 Version: 19

66 8213 RGB Display Interface Control 2 (RFh) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 VSPL HSPL EPL DPL Default DPL: Sets the signal polarity of the DOTCLK pin DPL = The data is input on the rising edge of DOTCLK DPL = 1 The data is input on the falling edge of DOTCLK EPL: Sets the signal polarity of the ENABLE pin EPL = The data DB17- is written when ENABLE = Disable data write operation when ENABLE = 1 EPL = 1 The data DB17- is written when ENABLE = 1 Disable data write operation when ENABLE = HSPL: Sets the signal polarity of the HSYNC pin HSPL = Low active HSPL = 1 High active VSPL: Sets the signal polarity of the VSYNC pin VSPL = Low active VSPL = 1 High active 8214 Power Control 1 (R1h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 SAP BT2 BT1 BT APE AP2 AP1 AP SLP STB Default SLP: When SLP = 1, enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption In the sleep mode, the GRAM data and instructions cannot be updated except the following instruction a Exit sleep mode (SLP = ) STB: When STB = 1, enters the standby mode and the display operation stops except the GRAM power supply to reduce the power consumption In the STB mode, the GRAM data and instructions cannot be updated except the following instruction a Exit standby mode (STB = ) AP[2:]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit The larger constant current enhances the drivability of the LCD, but it also increases the current consumption Adjust the constant current taking the trade-off into account between the display quality and the current consumption In no-display period, set AP[2:] = to halt the operational amplifier circuits and the step-up circuits to reduce current consumption Page 66 of 113 Version: 19

67 AP[2:] Gamma driver amplifiers Source driver amplifiers Halt Halt SAP: Source Driver output control SAP=, Source driver is disabled SAP=1, Source driver is enabled When starting the charge-pump of LCD in the Power ON stage, make sure that SAP=, and set the SAP=1, after starting up the LCD power supply circuit APE: Power supply enable bit Set APE = 1 to start the generation of power supply according to the power supply startup sequence BT[3:]: Sets the factor used in the step-up circuits Select the optimal step-up factor for the operating voltage To reduce power consumption, set a smaller factor BT[2:] DDVDH VCL VGH VGL 3 h VCI1 x 2 - VCI1 - VCI1 x 5 3 h1 VCI1 x 6 - VCI1 x 4 VCI1 x 2 - VCI1 3 h2 - VCI1 x 3 3 h3 - VCI1 x 5 3 h4 VCI1 x 2 - VCI1 VCI1 x 5 - VCI1 x 4 3 h5 - VCI1 x 3 3 h6 - VCI1 x 4 VCI1 x 2 - VCI1 VCI1 x 4 3 h7 - VCI1 x 3 Notes: 1 Connect capacitors to the capacitor connection pins when generating DDVDH, VGH, VGL and VCL levels 2 Make sure DDVDH = 6V (max), Page 67 of 113 Version: 19

68 8215 Power Control 2 (R11h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 DC12 DC11 DC1 DC2 DC1 DC VC2 VC1 VC Default VC[2:] Sets the ratio factor of VCI to generate the reference voltages VCI1 VC2 VC1 VC VCI1 voltage 95 x VCI 1 9 x VCI 1 85 x VCI x VCI 1 75 x VCI x VCI 1 1 Disabled x VCI DC[2:]: Selects the operating frequency of the step-up circuit 1 The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption Adjust the frequency taking the trade-off between the display quality and the current consumption into account DC1[2:]: Selects the operating frequency of the step-up circuit 2 The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption Adjust the frequency taking the trade-off between the display quality and the current consumption into account DC2 DC1 DC Step-up circuit1 Step-up circuit2 DC12 DC11 DC1 step-up frequency (f DCDC1) step-up frequency (f DCDC2) Fosc Fosc / 4 1 Fosc / 2 1 Fosc / 8 1 Fosc / 4 1 Fosc / Fosc / Fosc / 32 1 Fosc / 16 1 Fosc / Fosc / Fosc / Fosc / Fosc / Halt step-up circuit Halt step-up circuit 2 Note: Be sure f DCDC1 f DCDC2 when setting DC[2:] and DC1[2:] Page 68 of 113 Version: 19

69 8216 Power Control 3 (R12h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 VCIRE VRH3 VRH2 VRH1 VRH Default VRH[3:] Set the amplifying rate (16 ~ 19) of VCI applied to output the VREG1OUT level, which is a reference level for the VCOM level and the grayscale voltage level VCIRE: Select the external reference voltage VCI or internal reference voltage VCIR VCIRE= External reference voltage VCI (default) VCIRE =1 Internal reference voltage 25V VCIRE = VCIRE =1 VRH3 VRH2 VRH1 VRH VREG1OUT VRH3 VRH2 VRH1 VRH VREG1OUT Halt Halt 1 VCI x V x 2 = 5V 1 VCI x V x 25 = 5125V 1 1 VCI x V x 21 = 525V 1 VCI x V x 22 = 55V 1 1 VCI x V x 23 = 575V 1 1 VCI x V x 24 = 6V VCI x V x 24 = 6V 1 VCI x V x 16 = 4V 1 1 VCI x V x 165 = 4125V 1 1 VCI x V x 17 = 425V VCI x V x 175 = 4375V 1 1 VCI x V x 18 = 45V VCI x V x 185 = 4625V VCI x V x 19 = 475V VCI x V x 195 = 4875V When VCI<25V, Internal reference voltage will be same as VCI Make sure that VC and VRH setting restriction: VREG1OUT (DDVDH - 2)V Page 69 of 113 Version: 19

70 8217 Power Control 4 (R13h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 VDV4 VDV3 VDV2 VDV1 VDV Default VDV[4:] Select the factor of VREG1OUT to set the amplitude of Vcom alternating voltage from 7 to 124 x VREG1OUT VDV4 VDV3 VDV2 VDV1 VDV VCOM amplitude VDV4 VDV3 VDV2 VDV1 VDV VCOM amplitude VREG1OUT x 7 1 VREG1OUT x 94 1 VREG1OUT x VREG1OUT x 96 1 VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x 1 1 VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x 18 1 VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x 124 Set VDV[4:] to let Vcom amplitude less than 6V 8218 GRAM Horizontal/Vertical Address Set (R2h, R21h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD W 1 AD16 AD15 AD14 AD13 AD12 AD11 AD1 AD9 AD8 Default AD[16:] Set the initial value of address counter (AC) The address counter (AC) is automatically updated in accordance to the setting of the AM, I/D bits as data is written to the internal GRAM The address counter is not automatically updated when read data from the internal GRAM AD[16:] GRAM Data Map 17 h ~ 17 hef 1 st line GRAM Data 17 h1 ~ 17 h1ef 2 nd line GRAM Data 17 h2 ~ 17 h2ef 3 rd line GRAM Data 17 h3 ~ 17 h3ef 4 th line GRAM Data 17 h13d ~ 17 h13def 318 th line GRAM Data 17 h13e ~ 17 h13eef 319 th line GRAM Data 17 h13f ~ 17 h13fef 32 th line GRAM Data Note1: When the RGB interface is selected (RM = 1 ), the address AD[16:] is set to the address counter every frame on the falling edge of VSYNC Page 7 of 113 Version: 19

71 8219 Write Data to GRAM (R22h) R/W RS D17 D16 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 RAM write data (WD[17:], the DB[17:] pin assignment differs for each interface This register is the GRAM access port When update the display data through this register, the address counter (AC) is increased/decreased automatically 18-bit 822 Read GRAM Data from GRAM (R22h) RGB System Interface RD[17:] Read 18-bit data from GRAM through the read data register (RDR) Output Write Mapping Register Data Data & R5R4R3R2R1RG5G4 17DB 17RD 16DB 16RD 15DB 15RD 14DB 14RD 13DB 13RD 12DB 12RD G3G2G1GB5B4B3B2B1 11DB 11RD 1DB 1RD B 9DB 9RD 8DB 8RD 7DB 7RD 6DB 6RD 5DB 5RD4RD3RD2RD 4DB 3DB 2DB 1RD 1DB 16-bit GRAM RGB System Interface Output Write Mapping Register Data Data & R5R4R3R2R1RG5G4 17DB 17RD 16DB 16RD 15DB 15RD 14DB 14RD 13DB 13RD G3G2G1GB5B4B3B2B1 12DB 12RD 11DB 11RD 1RD 9RD B 8DB 8RD 7DB 7RD 6DB 6RD 5DB 5RD4RD3RD2RD 4DB 3DB 2DB 1RD1 9-bit GRAM RGB System Interface Output Write Mapping Register Data Data & R5R4R3R2R1RG5G4 17DB 17RD G3G2G1GB5B4B3B2B1 16DB 16RD 15DB 15RD 14DB 14RD B 13DB 13RD 12DB 12RD 11DB 11RD 1DB 1RD 9RD 17DB 8RD 16DB 7RD 15DB 6RD 14DB 5RD4RD3RD2RD 13DB 12DB 11DB 1DB 8-bit System Interface / Serial Data 1st TransferInterface 2nd Transfer 9 GRAM RGB Output Write Mapping Register Data Data & R5R4R3R2R1RG5G4G3G2G1GB5B4B3B2B1 17DB 17RD B 16DB 16RD 15DB 15RD 1st 14DB 14RD Transfer 13DB 13RD 12DB 12RD 11DB 11RD 1RD 9RD 17DB 8RD 16DB 7RD 15DB 6RD 2nd 14DB 5RD4RD3RD2RD Transfer 13DB 12DB 11DB 1 1RD R/W RS D17 D16 D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D R 1 RAM Read Data (RD[17:], the DB[17:] pin assignment differs for each interface Figure 27 Data Read from GRAM through Read Data Register in 18-/16-/9-/8-bit Interface Mode Page 71 of 113 Version: 19

72 Set a-si I/D TFT AM, LCD HAS/HEA, Single VSA/VEA Chip Driver Set address M Dummy GRAM -> read Read (invalid data data) Read Output (data of address latch Read datalatch -> DB[17:] M) Read Read Output datalatch (data of -> address DB[17:] M+1) Set address N Dummy GRAM -> read Read (invalid data data) Read Output (data of address latch Read datalatch -> DB[17:] N) Figure 28 GRAM Data Read Back Flow Chart Page 72 of 113 Version: 19

73 8221 Power Control 7 (R29h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 VCM5 VCM4 VCM3 VCM2 VCM1 VCM Default VCM[5:] Set the internal VcomH voltage VCM5 VCM4 VCM3 VCM2 VCM1 VCM VCOMH VCM5 VCM4 VCM3 VCM2 VCM1 VCM VCOMH VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x 85 1 VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x 86 1 VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x 88 1 VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x 92 1 VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x VREG1OUT x Frame Rate and Color Control (R2Bh) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 FRS3 FRS2 FRS1 FRS Default FRS[4:] Set the frame rate when the internal resistor is used for oscillator circuit FRS[3:] FRS[3:] Frame Rate 4 h h h h h h h h h h ha hb hc hd he Setting Prohibited hf Setting Prohibited Page 73 of 113 Version: 19

74 8223 Gamma Control (R3h ~ R3Dh) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D R3h W 1 KP1[2] KP1[1] KP1[] KP[2] KP[1] KP[] R31h W 1 KP3[2] KP3[1] KP3[] KP2[2] KP2[1] KP2[] R32h W 1 KP5[2] KP5[1] KP5[] KP4[2] KP4[1] KP4[] R35h W 1 RP1[2] RP1[1] RP1[] RP[2] RP[1] RP[] R36h W 1 VRP1[4] VRP1[3] VRP1[2] VRP1[1] VRP1[] VRP[3] VRP[2] VRP[1] VRP[] R37h W 1 KN1[2] KN1[1] KN1[] KN[2] KN[1] KN[] R38h W 1 KN3[2] KN3[1] KN3[] KN2[2] KN2[1] KN2[] R39h W 1 KN5[2] KN5[1] KN5[] KN4[2] KN4[1] KN4[] R3Ch W 1 RN1[2] RN1[1] RN1[] RN[2] RN[1] RN[] R3Dh W 1 VRN1[4] VRN1[3] VRN1[2] VRN1[1] VRN1[] VRN[3] VRN[2] VRN[1] VRN[] KP5-[2:] : RP1-[2:] : VRP1-[4:] : KN5-[2:] : RN1-[2:] : VRN1-[4:] : γfine adjustment register for positive polarity γgradient adjustment register for positive polarity γamplitude adjustment register for positive polarity γfine adjustment register for negative polarity γgradient adjustment register for negative polarity γamplitude adjustment register for negative polarity For details γ-correction Function section 8224 Horizontal and Vertical RAM Address Position (R5h, R51h, R52h, R53h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D R5h W 1 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA R51h W 1 HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA R52h W 1 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA R53h W 1 VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA R5h R51h Default R52h R53h HSA[7:]/HEA[7:] HSA[7:] and HEA[7:] represent the respective addresses at the start and end of the window address area in horizontal direction By setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data The HSA and HEA bits must be set before starting RAM write operation In setting these bits, be sure h HSA[7:]< HEA[7:] EF h and 1 h HEA-HAS VSA[8:]/VEA[8:] VSA[8:] and VEA[8:] represent the respective addresses at the start and end of the window address area in vertical direction By setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data The VSA and VEA bits must be set before starting RAM write operation In setting, be sure h VSA[8:]< VEA[8:] 13F h Page 74 of 113 Version: 19

75 VSA VEA hhsa HEA a-si TFT LCD Single Chip Driver Window Area Address GRAM Address Area13FEFh Figure 29 GRAM Access Range Configuration h HSA[7:] HEA[7:] EF h h VSA[8:] VEA[8:] 13F h Note1 The window address range must be within the GRAM address space Note2 Data are written to GRAM in four-words when operating in high speed mode, the dummy write operations should be inserted depending on the window address area For details, see the High-Speed RAM Write Function section Page 75 of 113 Version: 19

76 8225 Gate Scan Control (R6h, R61h, R6Ah) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D R6h W 1 GS NL5 NL4 NL3 NL2 NL1 NL SCN5 SCN4 SCN3 SCN2 SCN1 SCN R61h W 1 NDL VLE REV R6Ah W 1 VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL1 VL R6h R61h Default R6Ah SCN[5:] The allows to specify the gate line from which the gate driver starts to scan by setting the SCN[5:] bits SCN[5:] SM= Scanning Start Position SM=1 GS= GS=1 GS= GS=1 h G1 G32 G1 G32 1h G9 G312 G17 G34 2h G17 G34 G33 G288 3h G25 G296 G49 G272 4h G33 G288 G65 G256 5h G41 G28 G81 G24 6h G49 G272 G97 G224 7h G57 G264 G113 G28 8h G65 G256 G129 G192 9h G73 G248 G145 G176 Ah G81 G24 G161 G16 Bh G89 G232 G177 G144 Ch G97 G224 G193 G128 Dh G15 G216 G29 G112 Eh G113 G28 G2 G96 Fh G121 G2 G18 G8 1h G129 G192 G34 G64 11h G137 G184 G5 G48 12h G145 G176 G66 G32 13h G153 G168 G82 G16 14h G161 G16 G98 G319 15h G169 G152 G114 G33 16h G177 G144 G13 G287 17h G185 G136 G146 G271 18h G193 G128 G162 G255 19h G21 G12 G178 G239 1Ah G29 G112 G194 G223 1Bh G217 G14 G114 G27 1Ch G225 G96 G13 G191 1Dh G233 G88 G146 G175 1Eh G241 G8 G162 G159 1Fh G249 G72 G178 G143 2h G257 G64 G194 G127 21h G265 G56 G21 G111 22h G273 G48 G226 G95 23h G281 G4 G242 G79 24h G289 G32 G258 G63 25h G297 G24 G274 G47 26h G35 G16 G29 G31 27h G313 G8 G36 G15 28h ~ 3Fh Setting disabled Setting disabled Setting disabled Setting disabled Note: When SM=1, it is a interlacing scanning Please reference page 72! Page 76 of 113 Version: 19

77 NL[5:]: Sets the number of lines to drive the LCD at an interval of 8 lines The GRAM address mapping is not affected by the number of lines set by NL[5:] The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel NL[5:] LCD Drive Line 6 h 8 lines 6 h1 16 lines 6 h2 24lines 6 h1d 24 lines 6 h1e 248 lines 6 h1f 256 lines 6 h2 264 lines 6 h lines 6 h22 28 lines 6 h lines 6 h lines 6 h25 34 lines 6 h line 6 h27 32 line Others Setting inhibited NDL: Sets the source driver output level in the non-display area NDL Non-Display Area Positive Polarity Negative Polarity V63 V 1 V V63 GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:] and NL[4:] The scan direction determined by GS = can be reversed by setting GS = 1 When GS =, the scan direction is from G1 to G32 When GS = 1, the scan direction is from G32 to G1 REV: Enables the grayscale inversion of the image by setting REV=1 REV 1 GRAM Data 18 h 18 h3ffff 18 h 18 h3ffff Source Output in Display Area Positive polarity negative polarity V63 V V V63 V V63 V63 V VLE: Vertical scroll display enable bit When VLE = 1, the starts displaying the base image from the line (of the physical display) determined by VL[8:] bits VL[8:] sets the amount of scrolling, which is the Page 77 of 113 Version: 19

78 number of lines to shift the start line of the display from the first line of the physical display Note that the partial image display position is not affected by the base image scrolling The vertical scrolling is not available in external display interface operation In this case, make sure to set VLE = VLE Base Image Display Fixed 1 Enable Scrolling VL[8:]: Sets the scrolling amount of base image The base image is scrolled in vertical direction and displayed from the line determined by VL[8:] Make sure that VL[8:] Partial Image 1 Display Position (R8h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D PTD PTD PTD PTD PTD PTD PTD PTD PTD W 1 P[8] P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[] Default PTDP[8:]: Sets the display start position of partial image 1 The display areas of the partial images 1 and 2 must not overlap each another 8227 Partial Image 1 RAM Start/End Address (R81h, R82h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 PTS PTS PTS PTS PTS PTS PTS PTS PTS A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[] W 1 PTE PTE PTE PTE PTE PTE PTE PTE PTE A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[] Default PTSA[8:] PTEA[8:]: Sets the start line address and the end line address of the RAM area storing the data of partial image 1 Make sure PTSA[8:] PTEA[8:] 8228 Partial Image 2 Display Position (R83h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D PTD PTD PTD PTD PTD PTD PTD PTD PTD W 1 P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[] Default PTDP1[8:]: Sets the display start position of partial image 2 The display areas of the partial images 1 and 2 must not overlap each another 8229 Partial Image 2 RAM Start/End Address (R84h, R85h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 PTS PTS PTS PTS PTS PTS PTS PTS PTS A1[8] A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[] W 1 PTE PTE PTE PTE PTE PTE PTE PTE PTE A1[8] A1[7] A1[6] A1[5] A1[4] A1[3] A1[2] A1[1] A1[] Default PTSA1[8:] PTEA1[8:]: Sets the start line address and the end line address of the RAM area storing the data of partial image 2 Make sure PTSA1[8:] PTEA1[8:] Page 78 of 113 Version: 19

79 823 Panel Interface Control 1 (R9h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 DIVI1 DIVI RTNI4 RTNI3 RTNI2 RTNI1 RTNI Default 1 RTNI[4:]: Sets 1H (line) clock number of internal clock operating mode In this mode, display operation is synchronized with internal clock signal RTNI[4:] Clocks/Line RTNI[4:] Clocks/Line ~1111 Setting Disabled clocks 1 16 clocks clocks clocks clocks clocks clocks clocks clocks 11 2 clocks clocks clocks clocks clocks clocks clocks DIVI[1:]: Sets the division ratio of internal clock frequency DIVI1 DIVI Division Ratio Internal Operation Clock Frequency 1 fosc / fosc / fosc / fosc / Panel Interface Control 2 (R92h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 NOWI[2] NOWI[1] NOWI[] Default 1 1 NOWI[2:]: Sets the gate output non-overlap period when display operation is synchronized with internal clock signal NOWI[2:] Gate Non-overlap Period Setting inhibited 1 1 clocks 1 2 clocks 11 3 clocks 1 4 clocks 11 5 clocks 11 6 clocks 111 Setting inhibited Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (DIVI), from the reference point Page 79 of 113 Version: 19

80 8232 Panel Interface Control 4 (R95h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 DIVE1 DIVE Default 1 DIVE[1:]: Sets the division ratio of DOTCLK when display operation is synchronized with RGB interface signals DIVE[1:] Division Ratio 18/16-bit RGB Interface DOTCLK=5MHz 6-bit x 3 Transfers RGB Interface DOTCLK=5MHz Setting Prohibited Setting Prohibited - Setting Prohibited - 1 1/4 4 DOTCLKS 8 µs 12 DOTCLKS 8 µs 1 1/8 8 DOTCLKS 16 µs 24 DOTCLKS 16 µs 11 1/16 16 DOTCLKS 32 µs 48 DOTCLKS 32 µs 8233 Panel Interface Control 5 (R97h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 NOWE3 NOWE2 NOWE1 NOWE Default 1 1 NOWE[3:]: Sets the gate output non-overlap period when the display operation is synchronized with RGB interface signals NOWE[3:] Gate Non-overlap Period NOWE[3:] Gate Non-overlap Period Setting inhibited 1 8 clocks 1 1 clocks 11 9 clocks 1 2 clocks 11 1 clocks 11 3 clocks 111 Setting inhibited 1 4 clocks 11 Setting inhibited 11 5 clocks 111 Setting inhibited 11 6 clocks 111 Setting inhibited clocks 1111 Setting inhibited Note: 1 clock = (number of data transfer/pixel) x DIVE (division ratio) [DOTCLK] Page 8 of 113 Version: 19

81 8234 OTP VCM Programming Control (RA1h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D OTP_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ W 1 PGM_EN OTP5 OTP4 OTP3 OTP2 OTP1 OTP Default OTP_PGM_EN: OTP programming enable When program OTP, must set this bit OTP data can be programmed 2 times VCM_OTP[5:]: OTP programming data for VCOMH voltage, the voltage refer to VCM[5:] value 8235 OTP VCM Status and Enable (RA2h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D PGM_ PGM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ W 1 CNT1 CNT D5 D4 D3 D2 D1 D EN Default PGM_CNT[1:]: OTP programmed record These bits are read only OTP_PGM_CNT[1:] Description OTP clean 1 OTP programmed 1 time 1 OTP programmed 2 times 11 OTP programmed 3 times VCM_D[5:]: OTP VCM data read value These bits are read only VCM_EN: OTP VCM data enable 1 : Set this bit to enable OTP VCM data to replace R29h VCM value : Default value, use R29h VCM value 8236 OTP Programming ID Key (RA5h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY W Default KEY[15:]: OTP Programming ID key protection Before writing OTP programming data RA1h, it must write RA5h with xaa55 value first to make OTP programming successfully If RA5h is not written with xaa55, OTP programming will be fail See OTP Programming flow Page 81 of 113 Version: 19

82 8237 Deep stand by control (RE6h) R/W RS D15 D14 D13 D12 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D W 1 DSTB Default DSTB: When DSTB = 1, the enters the deep standby mode In deep standby mode, the internal logic power supply is turned off to reduce power consumption The GRAM data and instruction setting are not maintained when the enters the deep standby mode, and they must be reset after exiting deep standby mode Basic operation The basic operation modes of 9335 are as shown in the following diagram Page 82 of 113 Version: 19

83 CPU interface transition setting sequences Deep Standby Mode Enter deep standby mode Display Off Sequence Set RE6h:DSTB = 1 Release from deep standby Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Set ncs pin low to high x6 Registers set as default value 's register setting GRAM data setting Display On Sequence > 1 n sec ncs > 1 n sec > 31ms Page 83 of 113 Version: 19

84 9 OTP Programming Flow a-si TFT LCD Single Chip Driver V C OM H O TP program m ing Flow S tart R es et C heck P G M _C N T=2'b11? Y N S et R E B h= x81 S upply D D V D H = 7V D GN D = GN D W rite V C M D ata & E na ble V C M program R A 1h = x8 x x (xx =6 bit V C M value) S et ID K ey R A5 h= xa A 55 W ai t for P rogram m ing A t leas t 1 m s D isa ble V C M P rogram R A 1 hd 11=1 'b R A 1h =x R em ov e D D V D H voltage C o nfirm OTP value R A 2h D = 1'b1 R A 2h =x1 R es et E nd Page 84 of 113 Version: 19

85 1 GRAM Address Map & Read/Write i8 18-/16 16-bit System Bus Interface Timing nwr DB[17:] nrd RS ncs (a) Write to GRAM Write index 22h registerto Write Nth GRAM pixel data nwr DB[17:] nrd RS ncs (b) Read from GRAM Write (N+1)th GRAM pixel data Write (N+2)th GRAM pixel data Write (N+3)th GRAM pixel data Write (a) i8 Write 9-/8-bit to GRAM System index 22h registerto Dummy Bus Interface Read 1st Read data Timing Nth pixel 2nd (N+1)th Read pixel data 3rd (N+2)th Read pixel data nwr (b) DB[17:9] nrd RS ncs Read from h GRAM 22h high 1st write byte1st Nth pixel low write byte 2nd high write byte2nd (N+1)th low pixel write byte high 3rd write byte3rd (N+2)th low pixel write byte nwr DB[17:9] nrd RS ncs h 22h Dummy Read 1Dummy Read 2 high 1st read byte1st Nth pixel low read byte2nd high read byte2nd (N+1)th low pixel byte read has an internal graphics RAM (GRAM) of 172,8 bytes to store the display data and one pixel is constructed of 18 bits The GRAM can be accessed through the i8 system, SPI and RGB interfaces Figure3 GRAM Read/Write Timing of i8-system Interface Page 85 of 113 Version: 19

86 GRAM address map table of SS=, BGR= SS=, BGR= S1 S3 S4 S6 S7 S9 S1 S12 S517 S519 S52 S522 S523 S525 S526 S72 GS= GS=1 DB17 DB17 DB17 DB17 DB17 DB17 DB17 DB17 G1 G32 h 1h 2h 3h ECh Edh Eeh Efh G2 G319 1h 11h 12h 13h 1Ech 1Edh 1Eeh 1Efh G3 G318 2h 21h 22h 23h 2Ech 2Edh 2Eeh 2Efh G4 G317 3h 31h 32h 33h 3Ech 3Edh 3Eeh 3Efh G5 G316 4h 41h 42h 43h 4Ech 4Edh 4Eeh 4Efh G6 G315 5h 51h 52h 53h 5Ech 5Edh 5Eeh 5Efh G7 G314 6h 61h 62h 63h 6Ech 6Edh 6Eeh 6Efh G8 G313 7h 71h 72h 73h 7Ech 7Edh 7Eeh 7Efh G9 G312 8h 81h 82h 83h 8Ech 8Edh 8Eeh 8Efh G1 G311 9h 91h 92h 93h 9Ech 9Edh 9Eeh 9Efh G311 G1 136h 1361h 1362h 1363h 136Ech 136Edh 136Eeh 136Efh G312 G9 137h 1371h 1372h 1373h 137Ech 137Edh 137Eeh 137Efh G313 G8 138h 1381h 1382h 1383h 138Ech 138Edh 138Eeh 138Efh G314 G7 139h 1391h 1392h 1393h 139Ech 139Edh 139Eeh 139Efh G315 G6 13Ah 13A1h 13A2h 13A3h 13AECh 13AEDh 13AEEh 13AEFh G316 G5 13Bh 13B1h 13B2h 13B3h 13BECh 13BEDh 13BEEh 13BEFh G317 G4 13Ch 13C1h 13C2h 13C3h 13CECh 13CEDh 13CEEh 13CEFh G318 G3 13Dh 13D1h 13D2h 13D3h 13DECh 13DEDh 13DEEh 13DEFh G319 G2 13Eh 13E1h 13E2h 13E3h 13EECh 13EEDh 13EEEh 13EEFh G32 G1 13Fh 13F1h 13F2h 13F3h 13FECh 13FEDh 13FEEh 13FEFh Page 86 of 113 Version: 19

87 i8 8/M68 system 18-bit 17DB data 16DB bus 15DB interface a-si TFT LCD Single Chip Driver RGB GRAM AssignmentR5R4R3R2R1RG5G4 Data 14DB 13DB 12DB 11DB 1DB9DB 8DB 7DB 6DB 5DB 4DB 3DB 2DB 1DB S (3n+1) G3G2G1GB5B4B3B2B1B i8 8/M68 GRAM system Data 16-bit 17DB data 16DB bus 15DB interface RGB AssignmentR5R4R3R2R1RG5G4 14DB 13DB 12DB 11DB 1G3 G2G1GB5B4B3B2B1 8DB 7DB 6DB 5DB 4DB 3DB 2DB 1 S (3n+1) B i8 8/M68 GRAM system Data9-bit 17DB data 16DB bus interface 15DB 14DB 13DB 12DB 11DB 1DB9 17DB 16DB 15DB 14DB 13DB 12DB 11DB 1DB 9 1 st Transfer 2 nd Transfer Source Output Pin S (3n+2) S (3n+3)N= to 239 Source Output Pin S (3n+2) S (3n+3)N= to 239 Source RGB AssignmentR5R4R3R2R1RG5G4 Output Pin S (3n+1) G3 S (3n+2) G2G1GB5B4B3B2B1 S (3n+3)N= to 239 B GRAM Data and display data of 18-/16-/9-bit system interface (SS= ", BGR= ") Figure31 i8-system Interface with 18-/16-/9-bit Data Bus (SS=, BGR= ) Page 87 of 113 Version: 19

88 i8 8/M68 a-si TFT LCD Single Chip Driver GRAM system Data8-bit 17DB interface 16DB 15DB / SPI 1st 14DB Interface transfer 13DB (212DB transfers/pixel 11DB pixel) 24RGBx32 Resolution 1 and 262K color RGB AssignmentR5R4R3R2R1RG5G4 S (3n+1) G3G2G1GB5B4B3B2B1 17DB 16DB 15DB 2nd 14DB transfer 13DB 12DB 11DB 1B i8 8/M68 system 8-bit interface (3 transfers/pixel pixel, TRI= 1", DFM[1:]= ]= ") RGB GRAM AssignmentR5R4R3R2R1RG5G4 Data 11DB 1 17DB 16DB 15DB 14DB 13DB 12DB G3 11DB G2G1GB5B4B3B2B1 1 17DB 16DB 15DB 14DB 13DB 12DB 11DB S (3n+1) B 1 1 st Transfer 2 nd Transfer 3 rd Transfer i8 8/M68 system RGB GRAM Assignment Data 8-bit interface 17DB 16DB (3 transfers/pixel 15DB 14DB pixel, 13DB TRI= 1", 12 DFM[1:]= ]= 1 1) Source Output PinR5R4R3R2R1RG5G4 17DB 16DB G3 15DB G2G1GB5B4B3B2B1 14DB 13DB 12DB 17DB 16DB 15DB 14DB 13DB B 12 1 st Transfer 2 nd Transfer 3 rd Transfer i8 8/M68 system 8-bit interface (SS= ", BGR= ") Source Output Pin S (3n+2) S (3n+3)N= to 239 Source Output Pin S (3n+2) S (3n+3)N= to 239 S (3n+1) S (3n+2) S (3n+3)N= to 239 Figure32 i8-system Interface with 8-bit Data Bus (SS=, BGR= ) Page 88 of 113 Version: 19

89 GRAM address map table of SS=1, BGR=1 SS=1, BGR=1 S72 S718 S717 S715 S714 S712 S711 S79 S12 S1 S9 S7 S6 S4 S3 S1 GS= GS=1 DB17 DB17 DB17 DB17 DB17 DB17 DB17 DB17 G1 G32 h 1h 2h 3h Ech Edh Eeh Efh G2 G319 1h 11h 12h 13h 1Ech 1Edh 1Eeh 1Efh G3 G318 2h 21h 22h 23h 2Ech 2Edh 2Eeh 2Efh G4 G317 3h 31h 32h 33h 3Ech 3Edh 3Eeh 3Efh G5 G316 4h 41h 42h 43h 4Ech 4Edh 4Eeh 4Efh G6 G315 5h 51h 52h 53h 5Ech 5Edh 5Eeh 5Efh G7 G314 6h 61h 62h 63h 6Ech 6Edh 6Eeh 6Efh G8 G313 7h 71h 72h 73h 7Ech 7Edh 7Eeh 7Efh G9 G312 8h 81h 82h 83h 8Ech 8Edh 8Eeh 8Efh G1 G311 9h 91h 92h 93h 9Ech 9Edh 9Eeh 9Efh G311 G1 136h 1361h 1362h 1363h 136Ech 136Edh 136Eeh 136Efh G312 G9 137h 1371h 1372h 1373h 137Ech 137Edh 137Eeh 137Efh G313 G8 138h 1381h 1382h 1383h 138Ech 138Edh 138Eeh 138Efh G314 G7 139h 1391h 1392h 1393h 139Ech 139Edh 139Eeh 139Efh G315 G6 13Ah 13A1h 13A2h 13A3h 13AECh 13AEDh 13AEEh 13AEFh G316 G5 13Bh 13B1h 13B2h 13B3h 13BECh 13BEDh 13BEEh 13BEFh G317 i8 8/M68 G4 13Ch 13C1h 13C2h 13C3h 13CECh 13CEDh 13CEEh 13CEFh G318 G3 13Dh 13D1h 13D2h 13D3h 13DECh 13DEDh 13DEEh 13DEFh G319 G2 GRAM system 13Eh Data 18-bit 17DB data 16DB bus 13E1h 15DB interface 14DB 13E2h 13DB 12DB 11DB 13E3h 1DB 9DB 8DB 7DB 13EECh 6DB 5DB 13EEDh 4DB 3DB 13EEEh 2DB 1DB 13EEFh G32 G1 13Fh 13F1h 13F2h 13F3h 13FECh 13FEDh 13FEEh 13FEFh RGB AssignmentR5R4R3R2R1RG5G4 S (72-3n) G3G2G1GB5B4B3B2B1B i8 8/M68 system 9-bit 17DB data 16DB bus interface RGB GRAM AssignmentR5R4R3R2R1RG5G4 Data 15DB 14DB 13DB 12DB 11DB 1DB G3 9G2G1GB5B4B3B2B1 17DB 16DB 15DB 14DB 13DB 12DB 11DB 1DB9 B 1 st Transfer 2 nd Transfer GRAM Data and display data of 18-/9-bit system interface (SS= 1", BGR= 1") Source Output Pin S (719-3n) S (718-3n)N= to 239 Source Output Pin S (72-3n) S (719-3n) S (718-3n) N= to 239 Figure 33 i8-system Interface with 18-/9-bit Data Bus (SS= 1, BGR= 1 ) Page 89 of 113 Version: 19

90 11 Window Address Function a-si TFT LCD Single Chip Driver The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM The window address area is made by setting the horizontal address register (start: HSA[7:], end: HEA[7:] bits) and the vertical address register (start: VSA[8:], end: VEA[8:] bits) The AM bit sets the transition direction of RAM address (either increment or decrement) These bits enable the to write data including image data consecutively not taking data wrap positions into account The window address area must be made within the GRAM address map area Also, the GRAM address bits (RAM address set register) must be an address within the window address area [Window address setting area] (Horizontal direction) H HSA[7:] HEA[7:] EF H (Vertical direction) H VSA[8:] VEA[8:] 13F H [RAM address, AD (an address within a window address area)]] (RAM address) HSA[7:] AD[7:] HEA[7:] h GRAM Address Map VSA[8:] AD[15:8] VEA[8:] 21h 211hWindow Address Area23Fh 213Fh 4F1h 4F3Fh 13F h Window HSA[7:] VSA[8:] address = 2h, 1h, setting VEA[8:] HEA[7:] area= 4Fh, 3Fh, AM I/D = 1 (increment) (horizontal writing) EF h 13FEF h Figure 34 GRAM Access Window Map Page 9 of 113 Version: 19

91 12 Gamma Correction a-si TFT LCD Single Chip Driver incorporates the γ-correction function to display 262,144 colors for the LCD panel The γ-correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers for positive and negative polarities, to make VREG1OUT PRP/NGradient Adjustment RegisterPRP/N1 PKP/N5 Fine Adjustment PKP/N4PKP/N3PKP/N2PKP/N1PKP/N Registers (6 x 3 bits) VRP/N Adjustment Amplitude Register VRP/N1 available with liquid crystal panels of various characteristics 8 to 1 selection VgP/VgN VgP1/VgN1 8 to 1 selection 8 to 1 selection V2 V V1 VgP8/VgN8 8 to 1 selection 8 to 1 selection VgP2/VgN2 VgP43/VgN43 V8 V7 V2 VgP55/VgN55 V43 V55 8 to 1 selection VgP62/VgN62 V56 VgP63/VgN63 V62 V63 V61 VGS Figure 35 Grayscale Voltage Generation Page 91 of 113 Version: 19

92 8 to 1 Selection to Selection to Selection to Selection 8 to 1 Selection 8 to 1 Selection 8 to 1 Selection to Selection to Selection to Selection 8 to 1 Selection 8 to 1 Selection Figure 36 Grayscale Voltage Adjustment Page 92 of 113 Version: 19

93 4- Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level To adjust the gradient, the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP[2:]/PRN[2:], PRP1[2:]/PRN1[2:] The registers consist of positive and negative polarity registers, allowing asymmetric drive 4- Amplitude adjustment registers The amplitude adjustment registers, VRP[3:]/VRN[3:], VRP1[4:]/VRN1[4:], are used to adjust the amplitude of grayscale voltages To adjust the amplitude, the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted Same as the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers 4- Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor, in respective 8-to-1 selectors Same with other registers, the fine adjustment Grayscale voltage registers consist of positive and Grayscale voltage negative polarity registers Grayscale voltage Gradient adjustment Amplitude adjustment Fine adjustment Figure 37 Gamma Curve Adjustment Register Groups Positive Polarity Negative Polarity Description Gradient PRP [2:] PRN [2:] Variable resistor VRCP, VRCN adjustment PRP1 [2:] PRN1 [2:] Variable resistor VRCP1, VRCN1 Amplitude VRP [3:] VRN [3:] Variable resistor VROP, VRON adjustment VRP1 [4:] VRN1 [4:] Variable resistor VROP1, VRON1 KP [2:] KN [2:] 8-to-1 selector (voltage level of grayscale 1) KP1 [2:] KN1 [2:] 8-to-1 selector (voltage level of grayscale 8) Fine adjustment KP2 [2:] KN2 [2:] 8-to-1 selector (voltage level of grayscale 2) KP3 [2:] KN3 [2:] 8-to-1 selector (voltage level of grayscale 43) KP4 [2:] KN4 [2:] 8-to-1 selector (voltage level of grayscale 55) KP5 [2:] KN5 [2:] 8-to-1 selector (voltage level of grayscale 62) Page 93 of 113 Version: 19

94 Ladder resistors and 8-to-1 selector Block configuration The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to-1 selectors Each 8-to-1 selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage Both variable resistors and 8-to-1 selectors are controlled according to the γ-correction registers This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels Variable resistors uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)/VRCP(N)1); amplitude adjustment (1) (VROP(N)); and the amplitude adjustment (2) (VROP(N)1) The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows Gradient adjustment Amplitude adjustment (1) Amplitude adjustment (2) PRP(N)/1[2:] Register VRCP(N)/1 Resistance VRP(N)[3:] Register VROP(N) Resistance VRP(N)1[4:] Register VROP(N)1 Resistance R R R 1 4R 1 2R 1 1R 1 8R 1 4R 1 2R 11 12R : : : : 1 16R : : : : 11 2R R R 11 24R R R R R R 8-to-1 selectors The 8-to-1 selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)1~6) The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages Fine adjustment registers and selected voltage Register Selected Voltage KP(N)[2:] VgP(N)1 VgP(N)8 VgP(N)2 VgP(N)43 VgP(N)55 VgP(N)62 VP(N)1 VP(N)9 VP(N)17 VP(N)25 VP(N)33 VP(N)41 1 VP(N)2 VP(N)1 VP(N)18 VP(N)26 VP(N)34 VP(N)42 1 VP(N)3 VP(N)11 VP(N)19 VP(N)27 VP(N)35 VP(N)43 11 VP(N)4 VP(N)12 VP(N)2 VP(N)28 VP(N)36 VP(N)44 1 VP(N)5 VP(N)13 VP(N)21 VP(N)29 VP(N)37 VP(N)45 11 VP(N)6 VP(N)14 VP(N)22 VP(N)3 VP(N)38 VP(N)46 11 VP(N)7 VP(N)15 VP(N)23 VP(N)31 VP(N)39 VP(N) VP(N)8 VP(N)16 VP(N)24 VP(N)32 VP(N)4 VP(N)48 Page 94 of 113 Version: 19

95 Fine adjustment registers and selected resistor Register Selected Resistor KP(N)[2:] RMP(N) RMP(N)1 RMP(N)2 RMP(N)3 RMP(N)4 RMP(N)5 R R R R R R 1 4R 1R 1R 1R 1R 4R 1 8R 2R 2R 2R 2R 8R 11 12R 3R 3R 3R 3R 12R 1 16R 4R 4R 4R 4R 16R 11 2R 5R 5R 5R 5R 2R RP R 6R RP2 6R 6R 6R 24R R 7R RP3 VP1 VP2 VP3 VP4 7R 7R 7R 28R RP4 RP5 RP6 RP7 VP5 VP6 VP7 VP8 KP[2:]=1 RMP=8R VgP1=VP3 4Rx7=28R { { Figure 38 Example of RMP(N)~5 definition Page 95 of 113 Version: 19

96 Data h a-si TFT LCD Single Chip Driver 1h Positive polarity output voltage Negative polarity output voltage Gamma 2h correction resister ratio 3h 4h 5h VP (VgP) VN (VgN) 6h VP1 (VgP1) VN1 (VgN1) 7h VP2 (VP8+(VP1-VP8)*(3/48)) VN2 (VN8+(VN1-VN8)*(3/48)) VP3 (VP8+(VP1-VP8)*(23/48)) VN3 (VN8+(VN1-VN8)*(23/48)) VP4 (VP8+(VP1-VP8)*(16/48)) VN4 (VN8+(VN1-VN8)*(16/48)) Ah 8h 9h VP5 (VP8+(VP1-VP8)*(12/48)) VN5 (VN8+(VN1-VN8)*(12/48)) VP6 (VP8+(VP1-VP8)*(8/48)) VN6 (VN8+(VN1-VN8)*(8/48)) VP7 (VP8+(VP1-VP8)*(4/48)) VN7 (VN8+(VN1-VN8)*(4/48)) Dh Bh Ch VP8 (VgP8) VN8 (VgN8) Eh VP9 VP2+(VP8-VP2)*(22/24) VN9 VN2+(VN8-VN2)*(22/24) Fh VP1 VP2+(VP8-VP2)*(2/24) VN1 VN2+(VN8-VN2)*(2/24) 1h VP11 VP2+(VP8-VP2)*(18/24) VN11 VN2+(VN8-VN2)*(18/24) 11h VP12 VP2+(VP8-VP2)*(16/24) VN12 VN2+(VN8-VN2)*(16/24) 12h VP13 VP2+(VP8-VP2)*(14/24) VN13 VN2+(VN8-VN2)*(14/24) 13h VP14 VP2+(VP8-VP2)*(12/24) VN14 VN2+(VN8-VN2)*(12/24) 14h VP15 VP2+(VP8-VP2)*(1/24) VN15 VN2+(VN8-VN2)*(1/24) 15h VP16 VP2+(VP8-VP2)*(8/24) VN16 VN2+(VN8-VN2)*(8/24) 16h VP17 VP2+(VP8-VP2)*(6/24) VN17 VN2+(VN8-VN2)*(6/24) 17h VP18 VP2+(VP8-VP2)*(4/24) VN18 VN2+(VN8-VN2)*(4/24) VP19 VP2+(VP8-VP2)*(2/24) VN19 VN2+(VN8-VN2)*(2/24) VP2 (VgP2) VN2 (VgN2) 1Ah 18h 19h VP21 (VP43+(VP2-VP43)*(22/23)) VN21 (VN43+(VN2-VN43)*(22/23)) VP22 (VP43+(VP2-VP43)*(21/23)) VN22 (VN43+(VN2-VN43)*(21/23)) VP23 (VP43+(VP2-VP43)*(2/23)) VN23 (VN43+(VN2-VN43)*(2/23)) 1Dh 1Bh 1Ch VP24 (VP43+(VP2-VP43)*(19/23)) VN24 (VN43+(VN2-VN43)*(19/23)) 1Eh VP25 (VP43+(VP2-VP43)*(18/23)) VN25 (VN43+(VN2-VN43)*(18/23)) 1Fh VP26 (VP43+(VP2-VP43)*(17/23)) VN26 (VN43+(VN2-VN43)*(17/23)) VP27 (VP43+(VP2-VP43)*(16/23)) VN27 (VN43+(VN2-VN43)*(16/23)) VP28 (VP43+(VP2-VP43)*(15/23)) VN28 (VN43+(VN2-VN43)*(15/23)) VP29 (VP43+(VP2-VP43)*(14/23)) VN29 (VN43+(VN2-VN43)*(14/23)) VP3 (VP43+(VP2-VP43)*(13/23)) VN3 (VN43+(VN2-VN43)*(13/23)) VP31 (VP43+(VP2-VP43)*(12/23)) VN31 (VN43+(VN2-VN43)*(12/23)) Page 96 of 113 Version: 19

97 Data Positive polarity output voltage Negative polarity output voltage 2h VP32 (VP43+(VP2-VP43)*(11/23)) VN32 (VN43+(VN2-VN43)*(11/23)) 21h VP33 (VP43+(VP2-VP43)*(1/23)) VN33 (VN43+(VN2-VN43)*(1/23)) 22h VP34 (VP43+(VP2-VP43)*(9/23)) VN34 (VN43+(VN2-VN43)*(9/23)) 23h VP35 (VP43+(VP2-VP43)*(8/23)) VN35 (VN43+(VN2-VN43)*(8/23)) 24h VP36 (VP43+(VP2-VP43)*(7/23)) VN36 (VN43+(VN2-VN43)*(7/23)) 25h VP37 (VP43+(VP2-VP43)*(6/23)) VN37 (VN43+(VN2-VN43)*(6/23)) 26h VP38 (VP43+(VP2-VP43)*(5/23)) VN38 (VN43+(VN2-VN43)*(5/23)) 27h VP39 (VP43+(VP2-VP43)*(4/23)) VN39 (VN43+(VN2-VN43)*(4/23)) 28h VP4 (VP43+(VP2-VP43)*(3/23)) VN4 (VN43+(VN2-VN43)*(3/23)) 29h VP41 (VP43+(VP2-VP43)*(2/23)) VN41 (VN43+(VN2-VN43)*(2/23)) 2Ah VP42 (VP43+(VP2-VP43)*(1/23)) VN42 (VN43+(VN2-VN43)*(1/23)) 2Bh VP43 (VgP43) VN43 (VgN43) 2Ch VP44 (VP55+(VP43-VP55)*(22/24)) VN44 (VN55+(VN43-VN55)*(22/24)) 2Dh VP45 (VP55+(VP43-VP55)*(2/24)) VN45 (VN55+(VN43-VN55)*(2/24)) 2Eh VP46 (VP55+(VP43-VP55)*(18/24)) VN46 (VN55+(VN43-VN55)*(18/24)) 2Fh VP47 (VP55+(VP43-VP55)*(16/24)) VN47 (VN55+(VN43-VN55)*(16/24)) 3h VP48 (VP55+(VP43-VP55)*(14/24)) VN48 (VN55+(VN43-VN55)*(14/24)) 31h VP49 (VP55+(VP43-VP55)*(12/24)) VN49 (VN55+(VN43-VN55)*(12/24)) 32h VP5 (VP55+(VP43-VP55)*(1/24)) VN5 (VN55+(VN43-VN55)*(1/24)) 33h VP51 (VP55+(VP43-VP55)*(8/24)) VN51 (VN55+(VN43-VN55)*(8/24)) 34h VP52 (VP55+(VP43-VP55)*(6/24)) VN52 (VN55+(VN43-VN55)*(6/24)) 35h VP53 (VP55+(VP43-VP55)*(4/24)) VN53 (VN55+(VN43-VN55)*(4/24)) 36h VP54 (VP55+(VP43-VP55)*(2/24)) VN54 (VN55+(VN43-VN55)*(2/24)) 37h VP55 (VgP55) VN55 (VgN55) 38h VP56 (VP62+(VP55-VP62)*(44/48)) VN56 (VN62+(VN55-VN62)*(44/48)) 39h VP57 (VP62+(VP55-VP62)*(4/48)) VN57 (VN62+(VN55-VN62)*(4/48)) 3Ah VP58 (VP62+(VP55-VP62)*(36/48)) VN58 (VN62+(VN55-VN62)*(36/48)) 3Bh VP59 (VP62+(VP55-VP62)*(32/48)) VN59 (VN62+(VN55-VN62)*(32/48)) 3Ch VP6 (VP62+(VP55-VP62)*(25/48)) VN6 (VN62+(VN55-VN62)*(25/48)) 3Dh VP61 (VP62+(VP55-VP62)*(18/48)) VN61 (VN62+(VN55-VN62)*(18/48)) 3Eh VP62 (VgP62) VN62 (VgN62) 3Fh VP63 (VgP63) VN63 (VgN63) Page 97 of 113 Version: 19

98 (S[72:1]) Source Output Driver a-si TFT LCD Single Chip Driver VCOM Negative polarity Postive polarity V Source Output Levels Negative Polarity Positive Polarity V63 GRAM Data Figure 39 Relationship between Source Output and VCOM Figure 4 Relationship between GRAM Data and Output Level Page 98 of 113 Version: 19

99 Page 99 of 113 Version: Application 131 Configuration of Power Supply Circuit Face Up (Bump View) Figure 41 Power Supply Circuit Block

100 The following table shows specifications of external elements connected to the s power supply circuit Items Recommended Specification Pin connection Capacity 1 µf (B characteristics) 63V VREG1OUT,VDD, VCL, C11A/B, C13 A/B, 1V DDVDH, C21 A/B, C22 A/B 25V VGH, VGL Page 1 of 113 Version: 19

101 Display Display OFF a-si TFT LCD Single Chip Driver GON Off D[1:] DTE = 11 Flow Display Power On Wait for more 2 frames Set SAP=1 Setting Flow Display Display D[1:] GON DTE = OFF 1 Wait D[1:] GON DTE for 2 = On frames 1 Wait for more 2 frames Display more GON Display D[1:] GON DTE OFF DTE On Display D[1:] 1 GON DTE On 1 Display AP[2:] PON SAP Supply = Off Wait D[1:] = 11 for more 2 frames Display Off Display D[1:] GON DTE = On 11 Display ON 132 Display ON/OFF Sequence Figure 42 Display On/Off Register Setting Sequence Page 11 of 113 Version: 19

102 133 Standby and Sleep Mode Set Display Standby Standby Off (STB Sequence = 1) Release (STB from = Standby ) Release standby from Display Sleep Set Sleep Off (SLP Sequence = 1) Release (SLP from = ) Sleep Release Sleep from Stabilizing 8ms or more time? R1 19h Stabilizing 8ms or more time R1 19h Display On Sequence Display On Sequence Figure 43 Standby/Sleep Mode Register Setting Sequence Page 12 of 113 Version: 19

103 134 Power Supply Configuration VCI Power VCIIOVCC Supply ON (VCC, VCI, IOVCC) or VCI, IOVCC IOVCC SimultaneouslyGND Power Display and On OFF Reset DTE D[1:] GON Display = OFF Setting Registers power supply setting startup before PON = Stabilizing 5ms LCD Supply Sequence or Power more ON time Power Set VDV[5:], VC[2:], supply PON=,BT[2:] VRH[3:], initial VCM[5;], setting = stabilizing Step-up 8ms or circuit more time power Registers supply setting startup for Power Set BT[2:],PON AP[2:],APE=1, DC1[2:], supply DC[2:] = operation 1, setting stabilizing Operational Amplifier time Set the Display Sequence other ON registers Display ON Set DTE=1 D[1:]=11 GON=1 SAP=1 Power ON Sequence When supplying and cutting off power, follow the sequence below The setting time for step-up circuits and Normal Display operational amplifiers depends on external resistance and capacitance Display Sequence OFF Display DTE=1 D[1:]=11 GON=1ON Setting Power Display Supply OFF SettingHalt SAP= Power Supply OFF (VCC, VCI, IOVCC) AP[2:] PON = = Or IOVCC, IOVCC IOVCC Power VCI OFF Simultaneously Sequence VCI GND Figure 44 Power Supply ON/OFF Sequence Page 13 of 113 Version: 19

104 a-si BT TFT LCD Single VGH Chip Driver VGH (+9 ~ 165V) 135 Voltage Generation The pattern diagram for setting the voltages and the waveforms of the voltages of the are as follows VLCD (45 ~ 55V) Vci VREG1OUT (3 ~ (VLCD-5)V) (25 ~ 33V) VC[2:] VRH VCI1 VCM DDVDH VDV VCOMH (3 ~ (VLCD-5)V) VCOML VCL ( ~ (VCL+5) -33V) ~ -1V) BT VGL VCL VGL (-4 ~ -165V) Figure 45 Voltage Configuration Diagram Note: The DDVDH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs The voltage levels in the following relationships (DDVDH VREG1OUT ) > 2V and (VCOML VCL) > 5V are the actual voltage levels When the alternating cycles of VCOM are set high (eg the polarity inverts every line cycle), current consumption is large In this case, check the voltage before use Page 14 of 113 Version: 19

105 24RGBx32 VGH Resolution and 262K color Output Gate VCOM VGL 136 Applied Voltage to the TFT panel Source output Figure 46 Voltage Output to TFT LCD Panel 137 Partial Display Function The allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers The following example shows the setting for partial display function: Base Image Display Setting BASEE NL[5:] 6 h27 Partial Image 1 Display Setting PTDE 1 PTSA[8:] 9 h PTEA[8:] 9 hf PTDP[8:] 9 h8 Partial Image 2 Display Setting PTDE1 1 PTSA1[8:] 9 h2 PTEA1[8:] 9 h2f PTDP1[8:] 9 hc Page 15 of 113 Version: 19

106 PTEA=9'hF PTSA=9'h PTEA1=9'h2F PTSA1=9'h2 GRAM Partial GRAM Image MAP Area1 LCD 12 (2nd (3rd (1st Panel line) a-si TFT LCD Single Chip Driver Partial GRAM Image Area2 Partial Display Image Area1 Partial Display Image Area2 319 (32th line) PTDP=9'h8 PTDP1=9'hC Figure 47 Partial Display Example Page 16 of 113 Version: 19

107 14 Electrical Characteristics 141 Absolute Maximum Ratings The absolute maximum rating is listed on following table When is used out of the absolute maximum ratings, the may be permanently damaged To use the within the following electrical characteristics limit is strongly recommended for normal operation If these electrical characteristic conditions are exceeded during normal operation, the will malfunction and cause poor reliability Item Symbol Unit Value Note Power supply voltage (1) IOVCC V -3 ~ , 2 Power supply voltage (1) VCI GND V -3 ~ , 4 Power supply voltage (1) DDVDH GND V -3 ~ + 6 1, 4 Power supply voltage (1) GND VCL V -3 ~ Power supply voltage (1) DDVDH VCL V -3 ~ + 9 1, 5 Power supply voltage (1) VGH VGL V 3 ~ + 3 1, 5 Input voltage Vt V -3 ~ VCC+ 3 1 Operating temperature Topr C -4 ~ , 9 Storage temperature Tstg C -55 ~ , 9 Notes: 1 GND must be maintained 2 (High) (VCC = VCC) GND (Low), (High) IOVCC GND (Low) 3 Make sure (High) VCI GND (Low) 4 Make sure (High) DDVDH GND (Low) 5 Make sure (High) DDVDH VCL (Low) 6 Make sure (High) VGH GND (Low) 7 Make sure (High) GND VGL (Low) 8 For die and wafer products, specified up to 85 C 9 This temperature specifications apply to the TCP package Page 17 of 113 Version: 19

108 142 DC Characteristics (VCC = VCI=25 ~ 36V, IOVCC = 165 ~ 36V, Ta= -4 ~ 85 C) Item Symbol Unit Test Condition Min Typ Max Note Input high voltage V IH V IOVCC= 165 ~ 36V 8*IOV CC - IOVCC - Input low voltage V IL V IOVCC= 165 ~ 36V -3-2*IOVCC - Output high voltage(1) ( DB-17 Pins) Output low voltage ( DB-17 Pins) V OH1 V IOH = -1 ma 8*IOV CC V OL1 V IOVCC=165~36V - - 2*IOVCC - I/O leakage current I LI µa Vin = ~ VCC Current consumption during normal operation (VCC GND)+ (IOVCC - GND ) Current consumption during standby mode (VCC GND)+ (IOVCC - GND ) LCD Drive Power Supply Current ( DDVDH-GND ) LCD Driving Voltage ( DDVDH-GND ) I OP µa VCC=IOVCC=28V, Ta=25 C, fosc = 512KHz ( Line) GRAM data = h - TBD - - I ST µa VCC=IOVCC=28V, Ta=25 C ILCD ma VCI=28V, VREG1OUT =48V DDVDH=52V, Frame Rate: 7Hz, line-inversion, Ta=25 C, GRAM data = h, DDVDH V Output deviation voltage V DEV mv Output offset voltage V OFFSET mv Note Note1: The Max value is between with measure point and Gamma setting value 143 Reset Timing Characteristics Reset Timing Characteristics (IOVCC = 165 ~ 36 V) nreset tres_l trres tres_h Item Symbol Unit Min Typ Max VIL VIH Reset low-level width t RES_L ms Reset rise time t rres µs Reset high-level width t RES_H ms Page 18 of 113 Version: 19

109 144 AC Characteristics 1441 i8-system Interface Timing Characteristics Normal Write Mode (IOVCC = 165~36V) Bus cycle time Item Symbol Unit Min Typ Max Test Condition Write t CYCW ns (75) - - Read t CYCR ns Write low-level pulse width PW LW ns (4) Write high-level pulse width PW HW ns (3 ) Read low-level pulse width PW LR ns Read high-level pulse width PW HR ns ncs/rs/ DB Write / Read rise / fall time t WRr/t WRf ns Setup time Write ( RS to ncs, E/nWR ) t AS ns Read ( RS to ncs, RW/nRD ) Address hold time t AH ns Write data set up time t DSW ns Write data hold time t H ns Read data delay time t DDR ns Read data hold time t DHR ns RS ncs VIH VIL tas t cs tah VIH VIL t chw nwr PWLW t cycw PWHW DB[17:] (Write) tas t wr f t t wrr DSW t H tcycr Valid data tah nrd DB[17:] (Read) PWLR t wrf t wrr PWHR tddr tdhr Valid data Figure 48 i8-system Bus Timing Page 19 of 113 Version: 19

110 1442 Serial Data Transfer Interface Timing Characteristics (IOVCC= 165 ~ 36V) Serial clock cycle time Serial clock high level Item Symbol Unit Min Typ Max Test Condition Write ( received ) t SCYC ns (1) - - Read ( transmitted ) t SCYC ns Write ( received ) t SCH ns pulse width Read ( transmitted ) t SCH ns Serial clock low level pulse Write ( received ) t SCL ns width Read ( transmitted ) t SCL ns Serial clock rise / fall time t SCr, t SCf ns Chip select set up time t CSU ns Chip select hold time t CH ns Serial input data set up time t SISU ns Serial input data hold time t SIH ns ncs VIL Serial output data set up time t SOD ns Serial output data hold time tcsuvihvil t SOH ns VIL tscrvih tsch VIHVIL VILVIH VIL tsihtscftscyctscl tch VIH SCL SDO SDI tsodvoh VOL Output Input Data Data VOH VOL VIH VIL Output Input Data Data VOH VOL VIHtSISU Figure 49 SPI System Bus Timing Page 11 of 113 Version: 19

111 1443 RGB Interface Timing Characteristics 18/16-bit Bus RGB Interface Mode (IOVCC = 165 ~ 36V) Item Symbol Unit Min Typ Max Test Condition VSYNC/HSYNC setup time t SYNCS ns ENABLE setup time t ENS ns ENABLE hold time t ENH ns PD Data setup time t PDS ns PD Data hold time t PDH ns DOTCLK high-level pulse width PWDH ns DOTCLK low-level pulse width PWDL ns DOTCLK cycle time t CYCD ns (15) DOTCLK, VSYNC, HSYNC, rise/fall time t rghr, t rghf ns bit Bus RGB Interface Mode (IOVCC = 165 ~ 36V) Item Symbol Unit Min Typ Max Test Condition VSYNC/HSYNC setup time t SYNCS ns ENABLE setup time t ENS ns ENABLE hold time t ENH ns PD Data setup time t PDS ns PD Data hold time t PDH ns DOTCLK high-level pulse width PWDH ns DOTCLK low-level pulse width PWDL ns DOTCLK cycle time t CYCD ns HSYNC DOTCLK, VSYNC trgbr trgbf VIH VSYNC, HSYNC, rise/fall time VILtASE tsyncs t rghr, t rghf ns HSYNC VSYNC VIH VILtENS tenh trgbf VIH VIH VIL VIL PWDL VIH VIH VIL trgbr PWDH VIL tpds tcycd tpdh VIH Write Data VIH VIL Figure5 RGB Interface Timing Page 111 of 113 Version: 19

112 1444 Vcom Driving a-si TFT LCD Single Chip Driver The Vcom driving capability is descript as shown in the graph below by setting R=1 Ω capacitor loaded! The output delay time is considered as 5r! with different Delay times means (tphl or tplh) VcomH 9933% VcomL tphl 67% tplh VCOM VCOM output delay time (us) Load capacitance (nf) Page 112 of 113 Version: 19

113 15 Revision History a-si TFT LCD Single Chip Driver Version No Date Page Description V 28/8/6 all new built V,1 28/8/14 14 Change condition of stand by and normal mode 28/1/8 15~24 Modify IC height and relative pad and alignment mark coordinate! 72 Frame rate modified 96 Schottky diode VCL-VGL GND-VGL 73 4 h HEA-HAS 1 h HEA-HAS 1 Modify figure 45 28/11/3 19,2,21 Modify pad coordinate of number 674,722, 859, 97 and 931 V,2 28/11/3 82, 83 Add deep stand by mode 61 Add 16 bit data format 99 Add application circuit 1 Modify Schottky diode number and capacitor number V,3 28/11/14 84 Modify OTP flow V,4 28/11/24 24 Modify alignment mark coordinate V,5 28/12/22 99,1 Modify component number V,6 28/12/3 8,12,13, Modify IOVCC, VCI, VCC range to 36V 18~111 V7 29/1/19 83 Add wake up timing 11 Add timing value 19 Add timing value V8 29/2/3 4, 48, 49 Delete HWM description 13 Delete MDDI description in IOVCC V9 29/2/19 47, 29 Remove interlaced and graphics function description V1 29/2/2 11, 28, 3, Add DB[15:], DB[7:], DB[8:]data input format 31 99, 1 Modify component number 29/3/4 57 Gate scan modification drawing V11 29/3/2 112 Add Vcom driving capability V12 29/3/24 61 Modify EPF setting of, 1 and 1 64 Modify PTS[2:] PTS[1:] V13 29/4/7 32 Modify drawing of data mapping V14~16 Modify for specific customers V17 29/6/22 74 Modify frame rate 19 Modify stand by current max value V18 29/7/14 11, 28 Modify IM= and 1 definition V19 29/9/7 99 Remove MDDI describe in configuration of power supply and 1 definition Page 113 of 113 Version: 19