ILI9325. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color. Datasheet

Transcription

1 a-si TFT LC Single Chip river atasheet Version: V43 ocument No: S_V43pdf ILI TECHNOLOGY CORP 4F, No 2, Tech 5 th Rd, Hsinchu Science Park, Taiwan 3, ROC Tel ; Fax

2 Table of Contents Section Page Introduction 7 2 Features 7 3 Block iagram 9 4 Pin escriptions 5 Pad Arrangement and Coordination 4 6 Block escription 2 7 System Interface 23 7 Interface Specifications Input Interfaces i8/8-bit System Interface i8/-bit System Interface i8/9-bit System Interface i8/8-bit System Interface Serial Peripheral Interface (SPI) VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface43 76 Interface Timing 46 8 Register escriptions 47 8 Registers Access Instruction escriptions 5 82 Index (IR) river Output Control (Rh) LC riving Wave Control (R2h) Entry Mode (R3h) Resizing Control Register (R4h) isplay Control (R7h) isplay Control 2 (R8h) isplay Control 3 (R9h) isplay Control 4 (RAh) 6 82 RGB isplay Interface Control (RCh) 6 82 Frame Marker Position (h) 62 Page 2 of Version: 43

3 82 RGB isplay Interface Control 2 (RFh) Power Control (Rh) Power Control 2 (Rh) Power Control 3 (Rh) Power Control 4 (Rh) GRAM Horizontal/Vertical Address Set (R2h, R2h) Write ata to GRAM (R22h) Read ata from GRAM (R22h) Power Control 7 (R29h) Frame Rate and Color Control (R2Bh) Gamma Control (R3h ~ R3h) Horizontal and Vertical RAM Address Position (R5h, R5h, R52h, R53h) Gate Scan Control (R6h, R6h, R6Ah) Partial Image isplay Position (R8h) Partial Image RAM Start/End Address (R8h, R82h) Partial Image 2 isplay Position (R83h) Partial Image 2 RAM Start/End Address (R84h, R85h) Panel Interface Control (R9h) Panel Interface Control 2 (R92h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) OTP VCM Programming Control (RAh) OTP VCM Status and Enable (RA2h) OTP Programming I Key (RA5h) 77 9 OTP Programming Flow 78 GRAM Address Map & Read/Write 79 Window Address Function 85 Gamma Correction 86 Application 9 Configuration of Power Supply Circuit 9 2 isplay ON/OFF Sequence 93 3 Standby and Sleep Mode 94 4 Power Supply Configuration 95 5 Voltage Generation 96 6 Applied Voltage to the TFT panel 97 7 Partial isplay Function 97 8 Resizing Function 98 4 Electrical Characteristics 4 Absolute Maximum Ratings Page 3 of Version: 43

4 42 C Characteristics 43 Reset Timing Characteristics 44 AC Characteristics 44 i8-system Interface Timing Characteristics 442 Serial ata Transfer Interface Timing Characteristics 443 RGB Interface Timing Characteristics 4 Revision History Page 4 of Version: 43

5 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 24 FIGURE2 8-BIT SYSTEM INTERFACE ATA FORMAT 25 FIGURE3 -BIT SYSTEM INTERFACE ATA FORMAT 26 FIGURE4 9-BIT SYSTEM INTERFACE ATA FORMAT 27 FIGURE5 8-BIT SYSTEM INTERFACE ATA FORMAT 28 FIGURE6 ATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE 28 FIGURE 7 ATA FORMAT OF SPI INTERFACE 3 FIGURE8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 3 FIGURE9 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= AN FM= ) 32 FIGURE ATA TRANSMISSION THROUGH VSYNC INTERFACE) 33 FIGURE MOVING PICTURE ATA TRANSMISSION THROUGH VSYNC INTERFACE 33 FIGURE OPERATION THROUGH VSYNC INTERFACE 34 FIGURE TRANSITION FLOW BETWEEN VSYNC AN INTERNAL CLOCK OPERATION MOES 36 FIGURE4 RGB INTERFACE ATA FORMAT 37 FIGURE GRAM ACCESS AREA BY RGB INTERFACE 38 FIGURE TIMING CHART OF SIGNALS IN 8-/-BIT RGB INTERFACE MOE 39 FIGURE TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 4 FIGURE8 EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 4 FIGURE9 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 44 FIGURE2 GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 45 FIGURE2 RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 46 FIGURE22 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 47 FIGURE23 REGISTER SETTING WITH I8 SYSTEM INTERFACE 48 FIGURE 24 REGISTER REA/WRITE TIMING OF I8 SYSTEM INTERFACE 49 FIGURE25 GRAM ACCESS IRECTION SETTING 55 FIGURE28 -BIT MPU SYSTEM INTERFACE ATA FORMAT 56 FIGURE29 8-BIT MPU SYSTEM INTERFACE ATA FORMAT 56 FIGURE 3 ATA REA FROM GRAM THROUGH REA ATA REGISTER IN 8-/-/9-/8-BIT INTERFACE MOE 67 FIGURE 3 GRAM ATA REA BACK FLOW CHART 68 FIGURE 32 GRAM ACCESS RANGE CONFIGURATION 7 FIGURE33 GRAM REA/WRITE TIMING OF I8-SYSTEM INTERFACE 79 FIGURE34 I8-SYSTEM INTERFACE WITH 8-/-/9-BIT ATA BUS (SS=, BGR= ) 8 FIGURE35 I8-SYSTEM INTERFACE WITH 8-BIT ATA BUS (SS=, BGR= ) 82 FIGURE 36 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 84 FIGURE 37 GRAM ACCESS WINOW MAP 85 FIGURE 38 GRAYSCALE VOLTAGE GENERATION 86 FIGURE 39 GRAYSCALE VOLTAGE AJUSTMENT 87 FIGURE 4 GAMMA CURVE AJUSTMENT 88 Page 5 of Version: 43

6 FIGURE 4 RELATIONSHIP BETWEEN SOURCE OUTPUT AN VCOM 9 FIGURE 42 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL 9 FIGURE 43 POWER SUPPLY CIRCUIT BLOCK 9 FIGURE 44 ISPLAY ON/OFF REGISTER SETTING SEQUENCE 93 FIGURE 45 STANY/SLEEP MOE REGISTER SETTING SEQUENCE 94 FIGURE 46 POWER SUPPLY ON/OFF SEQUENCE 95 FIGURE 47 VOLTAGE CONFIGURATION IAGRAM 96 FIGURE 48 VOLTAGE OUTPUT TO TFT LC PANEL 97 FIGURE 49 PARTIAL ISPLAY EXAMPLE 98 FIGURE 5 ATA TRANSFER IN RESIZING 99 FIGURE 5 RESIZING EXAMPLE 99 FIGURE 52 I8-SYSTEM BUS TIMING FIGURE 53 SPI SYSTEM BUS TIMING 4 FIGURE54 RGB INTERFACE TIMING Page 6 of Version: 43

7 Introduction a-si TFT LC Single Chip river is a 262,44-color one-chip SoC driver for a-tft liquid crystal display with resolution of 24RGBx32 dots, comprising a 72-channel source driver, a 32-channel gate driver, 2,8 bytes RAM for graphic data of 24RGBx32 dots, and power supply circuit has four kinds of system interfaces which are i8-system MPU interface (8-/9-/-/8-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [:]), serial data transfer interface (SPI) and RGB 6-/-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [:]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 5V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LC driver for medium or small size portable products such as digital cellular phones, smart phone, PA and PMP where long battery life is a major concern 2 Features Single chip solution for a liquid crystal QVGA TFT LC display 24RGBx32-dot resolution capable with real 262,44 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 72-channel source driver and 32-channel gate driver Internal 2,8 bytes graphic RAM High-speed RAM burst write function System interfaces i8 system interface with 8-/ 9-/-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [:]) VSYNC interface (System interface + VSYNC) Internal oscillator and hardware reset Resizing function ( /2, /4) Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Abundant functions for color display control γ-correction function enabling display in 262,44 colors Line-unit vertical scrolling function Page 7 of Version: 43

8 Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 5V ~ 33 V (interface I/O) Vci = 25V ~ 33 V (analog) LC Voltage drive: Source/VCOM power supply voltage VH - GN = 45V ~ 6 VCL GN = -2V ~ -3V VCI VCL 6V Gate driver output voltage VGH - GN = V ~ 2V VGL GN = -5V ~ -V VGH VGL 32V VCOM driver output voltage VCOMH = 3V ~ (VH-2)V VCOML = (VCL+5)V ~ V VCOMH-VCOML 6V a-tft LC storage capacitor: Cst only Page 8 of Version: 43

9 3 Block iagram IOVCC IM[3:] nreset Index Register (IR) ncs nwr/scl n RS SI SO MPU I/F 8-bit -bit 9-bit 8-bit SPI I/F 8 8 Control Register (CR) Address Counter (AC) LC Source river S[72:] [:] HSYNC VSYNC OTCLK ENABLE RGB I/F 8-bit -bit 6-bit 8 Graphics Operation 8 V63 ~ TEST TEST2 TEST3 TS[8:] VSYNC I/F 8 Read Latch 72 Write Latch 72 Grayscale Reference Voltage VREGOUT VGS VCC V Regulator Graphics RAM (GRAM) UMMY2~27 GN UMMY~ RC-OSC Timing Controller LC Gate river G[32:] VCI VCI Charge-pump Power Circuit VCOM Generator VCOM GN C+ VH C+ C+ VCL C2+ C22- C- C2- C22+ C- C- VGH VGL VCOMH VCOML Page 9 of Version: 43

10 4 Pin escriptions a-si TFT LC Single Chip river IM3, IM2, IM, IM/I ncs RS Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode nwr/scl n nreset SI SO [:] I I I I I I I O I/O IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc IM3 IM2 IM IM MPU-Interface Mode Pin in use Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO * Setting invalid Setting invalid Setting invalid i8-system 8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code I setting A chip select signal Low: the is selected and accessible High: the is not selected and not accessible Fix to the GN level when not in use A register select signal Low: select an index or status register High: select a control register Fix to either IOVcc or GN level when not in use A write strobe signal and enables an operation to write data when the signal is low Fix to either IOVcc or GN level when not in use SPI Mode: Synchronizing clock signal in SPI mode A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GN level when not in use A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SPI interface input pin The data is latched on the rising edge of the SCL signal SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SO as floating when not used An 8-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: [:] is used 9-bit I/F: [:9] is used -bit I/F: [:] and [8:] is used 8-bit I/F: [:] is used 8-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: [:] are used Page of Version: 43

11 Pin Name I/O Type escriptions -bit RGB I/F: [:] and [:] are used 8-bit RGB I/F: [:] are used ENABLE I MPU IOVcc Unused pins must be fixed to GN level ata ENEABLE signal for RGB interface operation Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal OTCLK VSYNC HSYNC FMARK I I I O MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc S72~S O LC G32~G O LC VCOM O TFT common electrode VCOMH O Stabilizing capacitor VCOML O Stabilizing capacitor GN or VGS I external resistor Fix to either IOVcc or GN level when not in use ot clock signal for RGB interface operation PL = : Input data on the rising edge of OTCLK PL = : Input data on the falling edge of OTCLK Fix to the GN level when not in use Frame synchronizing signal for RGB interface operation VSPL = : Active low VSPL = : Active high Fix to the GN level when not in use Line synchronizing signal for RGB interface operation HSPL = : Active low HSPL = : Active high Fix to the GN level when not in use Output a frame head pulse signal The FMARK signal is used when writing RAM data in synchronization with frame Leave the pin open when not in use LC riving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S SS =, the data in the RAM address h is output from S72 S, S4, S7, display red (R), S2, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels The high level of VCOM AC voltage Connect to a stabilizing capacitor The low level of VCOM AC voltage Adjust the VCOML level with the VV bits Connect to a stabilizing capacitor Reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor Charge-pump and Regulator Circuit Vci I Power A supply voltage to the analog circuit Connect to an external power supply supply of 25 ~ 33V GN I Power GN for the analog side: GN = V In case of COG, connect to supply GN on the FPC to prevent noise Vci O An internal reference voltage for the step-up circuit The amplitude between Vci and GN is determined by the VC[2:] Stabilizing bits capacitor Make sure to set the Vci voltage so that the VH, VGH and VGL voltages are set within the respective specification VH O Stabilizing Power supply for the source driver and Vcom drive Page of Version: 43

12 Pin Name I/O Type escriptions capacitor VGH O Stabilizing capacitor Power supply for the gate driver VGL O Stabilizing capacitor Power supply for the gate driver VCL O Stabilizing VcomL driver power supply capacitor VCL = 5 ~ VCI Place a stabilizing capacitor between GN C+, C- Step-up I/O C+, C- capacitor Capacitor connection pins for the step-up circuit C+, C- Step-up C2+, C2- I/O capacitor C22+, C22- Capacitor connection pins for the step-up circuit 2 Output voltage generated from the reference voltage VREGOUT IOVcc I/O Stabilizing capacitor I Power supply V O Power GN I Power supply GN = V Test Pads UMMY~ ummy pad - - UMMY2 ~ 27 Leave these pins as open IOGNUM O GN GN pin The voltage level is set with the VRH bits VREGOUT is () a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREGOUT = 3 ~ (VH 2)V Power Pads A supply voltage to the interface pins: IM[3:], nreset, ncs, nwr, n, RS, [:], VSYNC, HSYNC, OTCLK, ENABLE, SCL, SI, SO IOVcc = 5 ~ 33V and Vcc IOVcc In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise igital circuit power pad Connect these pins with the uf capacitor TESTO~ O Open Test pins Leave them open TEST, 2, 3 I IOGN Test pins (internal pull low) Connect to GN or leave these pins as open TS~8 I OPEN Test pins (internal pull low) Leave them open Liquid crystal power supply specifications Table No Item escription TFT Source river 72 pins (24 x RGB) 2 TFT Gate river 32 pins 3 TFT isplay s Capacitor Structure Cst structure only (Common VCOM) 4 Liquid Crystal rive Output 5 Input Voltage S ~ S72 V ~ V63 grayscales G ~ G32 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes IOVcc 5 ~ 33V Vci 25 ~ 33V Page of Version: 43

13 6 Liquid Crystal rive Voltages 7 Internal Step-up Circuits VH 45V ~ 6V VGH V ~ 2V VGL -5V ~ -V VCL -2V ~ -3V VGH - VGL Max 32V Vci - VCL Max 6V VH Vci x2 VGH Vci x4, x5, x6 VGL Vci x-3, x-4, x-5 VCL Vci x- Page of Version: 43

14 a-si TFT LC Single Chip river 4 Pad Arrangement and Coordination Chip Size: 82um x 87um Chip thickness : 28um or 4um (typ) Pad Location: Pad Center Coordinate Origin: Chip center Au bump height: um (typ) Au Bump Size: um x 98um Gate: G ~ G32 Source: S ~ S72 2 5um x 8um Input Pads Pad to 243 Alignment Marks 2 2 UMMY TEST IOGNUM TESTO TESTO2 TESTO3 IM/I IM IM2 IM3 TEST2 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO nreset nreset VSYNC HSYNC OTCLK ENABLE 4 TESTO 9 8 TEST3 TESTO TESTO SO SI n nwr/scl RS ncs TESTO4 TESTO FMARK TESTO TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS TS UMMY2 IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC V V V V V V V V V V V UMMY3 GN GN GN GN GN GN GN GN VGS VGS GN GN GN GN GN GN GN GN GN GN UMMY4 UMMY5 UMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH Face Up (Bump View) UMMY27 G39 G3 G3 G3 G3 G39 G37 G35 G33 G G G G G9 G7 G5 G3 G UMMY26 UMMY25 S S2 S3 S4 S5 S6 S7 S8 S9 S353 S354 S355 S356 S357 S358 S359 S36 UMMY24 Alignment Mark: A VCOML VCOML VCOML VCOML VREGOUT VREGOUT VREGOUT UMMY7 UMMY8 UMMY9 VCL VCL VCL VCL VCL VH VH VH VH VH x y UMMY23 S36 S362 S363 S364 S365 S366 S367 S368 S369 VH VCI VCI VCI VCI VCI VCI VCI VCI VCI 2 2 VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI UMMY UMMY C- C- C- C- C- C+ C+ C+ C+ C+ C- C- C- C- C- C+ C+ C+ C+ C+ VGL VGL VGL VGL VGL VGL Alignment Mark: A2 VGL VGL VGL VGL GN GN GN VGH VGH VGH VGH VGH VGH UMMY UMMY C- C- C- C- C+ C+ C+ C+ C2- C2- C2- C2- C2- C2- C2- C2+ C2+ C2+ C2+ C2+ C2+ C2+ C22- C22- C22- S7 S7 S74 S7 S7 S7 S78 S79 S72 UMMY22 UMMY2 G2 G4 G6 G8 G G G4 G G8 Bump View C22- C22- C22- C22- C22+ C22+ C22+ C22+ C22+ C22+ C22+ UMMY4 UMMY G34 G36 G38 G3 G3 G34 G3 G38 G32 UMMY2 Page 4 of Version: 43

15 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y UMMY TS VCOML C C TEST TS VCOML C UMMY IOGNUM TS VCOML C UMMY TESTO TS VCOML C UMMY TESTO TS VREGOUT VGL G TESTO UMMY VREGOUT VGL G IM/I IOVCC VREGOUT VGL G IM IOVCC UMMY VGL G IM IOVCC UMMY VGL G IM IOVCC UMMY VGL G TEST IOVCC VCL VGL G TESTO IOVCC VCL VGL G TESTO V VCL VGL G TESTO V VCL VGL G TESTO V VCL GN G TESTO V VH GN G TESTO V VH GN G TESTO V VH VGH G nreset V VH VGH G nreset V VH VGH G VSYNC V VH VGH G HSYNC V VCI VGH G OTCLK V VCI VGH G ENABLE UMMY VCI UMMY G GN VCI UMMY G GN VCI C G GN VCI C G GN VCI C G GN VCI C G TESTO GN VCI C G GN VCI C G GN VCI C G VGS VCI C G VGS VCI C G GN VCI C G TEST GN VCI C G TESTO GN VCI C G GN VCI C G GN VCI C G GN VCI C G GN VCI C G GN VCI C G GN UMMY C G GN UMMY C G UMMY C C G TESTO UMMY C C G SO UMMY C C G SI VCOM C C G n VCOM C C G nwr/scl VCOM C C G RS VCOM C C G ncs VCOM C C G TESTO VCOM C C G TESTO VCOM C C G FMARK VCOMH C C G TESTO VCOMH C C G TS VCOMH C C G TS VCOMH C C G TS VCOMH C C G TS VCOMH C C G No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y Page of Version: 43

16 3 G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G UMMY S S S G UMMY S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S Page of Version: 43

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 6 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S UMMY S S S S UMMY S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page of Version: 43

18 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 9 S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S UMMY G S S S UMMY G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G Page 8 of Version: 43

19 No Name X Y No Name X Y G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G UMMY G Alignment mark X Y 33 G a G b G G G G G G G G G G G G G G G G G G G G G G G G G G Page 9 of Version: 43

20 S ~ S72 G ~ G32 UMMY2~27 (No 244 ~ 9) Unit: um 5 x 5 I/O Pads (No ~ 243) Pad Pump Pad Pump 8 y X=2, 3, 35 Y=7, 8, 85 Unit: um Page 2 of Version: 43

21 5 Block escription MPU System Interface supports three system high-speed interfaces: i8-system high-speed interfaces to 8-, 9-, -, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a -bit index register (IR), an 8-bit write-data register (R), and an 8-bit read-data register (R) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The R is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the R from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time Registers selection by system interface (8-/9-/-/8-bit bus width) I8 Function RS nwr n Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Registers selection by the SPI system interface Function R/W RS Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB Page 2 of Version: 43

22 interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of 2,82 (24 x 32x 8/8) bytes with 8 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 262,44 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an internal oscillation resistor The frame rate is adjusted by the register setting LC river Circuit The LC driver circuit of consists of a 72-output source driver (S ~ S72) and a 32-output gate driver (G~G32) isplay pattern data are latched when the 72 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 72 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREGOUT, VGH, VGL and Vcom for driving an LC Page 22 of Version: 43

23 6 System Interface 6 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [:] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface (2) (Rewriting still pictures while displaying moving pictures) VSYNC interface (isplaying moving pictures) RAM Access Setting (RM) System interface (RM = ) RGB interface (RM = ) System interface (RM = ) System interface (RM = ) isplay Operation Mode (M[:]) Internal operating clock (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) VSYNC interface (M[:] = ) Note ) Registers are set only via the system interface Note 2) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 23 of Version: 43

24 System System Interface 8//6 ncs RS nwr n [:] RGB Interface ENABLE VSYNC HSYNC OTCLK Figure System Interface and RGB Interface connection 62 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting registers and GRAM access IM3 IM2 IM IM/I Interface Mode Pin Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO * Setting invalid Setting invalid Setting invalid i8-system8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid Page 24 of Version: 43

25 62 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as levels System ncs A2 nwr n [3:] 8 ncs RS nwr n [:] 8-bit System Interface (262K colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure2 8-bit System Interface ata Format Page 25 of Version: 43

26 622 i8/-bit System Interface The i8/-bit system interface is selected by setting the IM[3:] as levels The 262K or 65K color can be display through the -bit MPU interface When the 262K color is displayed, two transfers ( st transfer: 2 bits, 2 nd transfer: bits or st transfer: bits, 2 nd transfer: 2 bits) are necessary for the -bit CPU interface TRI FM -bit MPU System Interface ata Format system -bit interface ( transfers/pixel) 65,536 colors * 4 st Transfer R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system -bit interface (2 transfers/pixel) 262,44 colors 4 st Transfer nd Transfer R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system -bit interface (2 transfers/pixel) 262,44 colors st Transfer 2 4 2nd Transfer R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure3 -bit System Interface ata Format Page 26 of Version: 43

27 623 i8/9-bit System Interface The i8/9-bit system interface is selected by setting the IM[3:] as and the ~9 pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:] pins must be tied to GN System ncs A nwr n [8:] 9 ncs RS nwr n [:9] 9-bit System Interface (262K colors) TRI=, FM[:]= Input ata st Transfer (Upper bits) 4 9 2nd Transfer (Lower bits) 4 9 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure4 9-bit System Interface ata Format 624 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as and the ~ pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:] pins must be tied to GN Page 27 of Version: 43

28 TRI FM 8-bit MPU System Interface ata Format system 8-bit interface (2 transfers/pixel) 65,536 colors * st Transfer 4 2nd Transfer 4 R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system 8-bit interface (3 transfers/pixel) 262,44 colors st Transfer 2nd Transfer 4 3rd Transfer 4 R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system 8-bit interface (3 transfers/pixel) 262,44 colors st Transfer 4 2nd Transfer 4 3rd Transfer 4 R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure5 8-bit System Interface ata Format ata transfer synchronization in 8/9-bit bus interface mode supports a data transfer synchronization function to reset upper and lower counters which count the transfers numbers of upper and lower byte in 8/9-bit interface mode If a mismatch arises in the numbers of transfers between the upper and lower byte counters due to noise and so on, the h register is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of upper byte This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset RS nwr [:9] Upper/ Lowe r "h "h "h "h Uppe r Lowe r 8-/9-bit transfe r synchronization Figure6 ata Transfer Synchronization in 8/9-bit System Interface 63 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:] pins as x level The chip select pin Page 28 of Version: 43

29 (ncs), the serial transfer clock pin (SCL), the serial data input pin (SI) and the serial data output pin (SO) are used in SPI mode The I pin sets the least significant bit of the identification code The [:] pins, which are not used, must be tied to GN The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS =, either index write operation or status read operation is executed When RS =, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) ata is written when the R/W bit is and read back when the R/W bit is After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are -bit format and receive the first and the second byte datat as the upper and the lower eight bits of the -bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start evice I code RS R/W I / / Note: I bit is selected by setting the IM/I pin RS and R/W Bit Function RS R/W Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data Page 29 of Version: 43

30 Serial Peripheral Interface for register access SP I Input ata Register ata IB IB 4 IB IB IB IB IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB IB Serial Peripheral Interface 65K colors Input ata Write ata Register GRAM ata RGB mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure 7 ata Format of SPI Interface Page 3 of Version: 43

31 (a) Basic data transmission through SPI Start End ncs (Input) SCL (Input) SI (Input) I RS RW Start Byte Index register, registers setting, and GRAM write SO (Output) Status, registers read and GRAM read (b) Consecutive data transmission through SPI Start ncs (Input) SCL (Input) SI (Input) Start Byte Register upper eight bits Register lower eight bits Register 2 upper eight bits Register 2 lower eight bits Note: The first byte after the start byte is always the upper eight bits Register execution time (c) GRAM data read transmission ncs (Input) Start End SCL (Input) SI (Input) Start Byte RS=, RW= SO (Output) ummy read ummy read 2 ummy read 3 ummy read 4 ummy read 5 RAM read upper byte RAM read lower byte Note: Five bytes of invalid dummy data read after the start byte (d) Status/registers read transmission Start ncs (Input) End SCL (Input) SI (Input) SO (Output) Start Byte Register upper eight bits Register lower eight bits Note: One byte of invalid dummy data read after the start byte Figure8 ata transmission through serial peripheral interface (SPI) Page 3 of Version: 43

32 (e) Basic data transmission through SPI ncs (Input) Start End SCL (Input) SI (Input) I RS RW Start Byte GRAM data write SO (Output) GRAM data read (f) GRAM data write transmission Start ncs (Input) End SCL (Input) SI (Input) Start Byte RAM data st transfer RAM data 2nd transfer RAM data 3rd transfer RAM data 2 st transfer RAM data 2 2nd transfer RAM data 2 3rd transfer SO (Output) Note: Five bytes of invalid dummy data read after the start byte GRAM ata () execution time GRAM ata (2) execution time (g) GRAM data read transmission Start ncs (Input) End SCL (Input) SI (Input) Start Byte RS=, RW= SO (Output) ummy read ummy read 2 ummy read 3 ummy read 4 ummy read 5 RAM read st byte RAM read 2nd byte RAM read 3rd byte Note: Five bytes of invalid dummy data read after the start byte RAM data transfer in SPI mode when TRI= and FM[:]= Figure9 ata transmission through serial peripheral interface (SPI), TRI= and FM= ) Page 32 of Version: 43

33 64 VSYNC Interface supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i8 system interface When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting M[:] = and RM = VSYNC MPU ncs RS nwr [:] Figure ata transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal All display data are stored in GRAM to minimize total data transfer required for moving picture display VSYNC Write data to RAM through system interface isplay operation synchronized with internal clocks Rewriting screen data Rewriting screen data Figure Moving picture data transmission through VSYNC interface Page 33 of Version: 43

34 VSYNC Back porch (4 lines) RAM Write isplay operation isplay (32 lines) Front porch (2 lines) Black period Figure Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula Internal clock frequency (fosc) [Hz] = FrameFrequency x (isplayline (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation Minimum RAM write speed (HZ ) 24 x isplaylines (NL ) [( BackPorch(BP)+isplayLines(NL) - margins ] x ( clocks ) x /fosc Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below [Example] isplay size: 24 RGB 32 lines Lines: 32 lines (NL = ) Back porch: 4 lines (BP = ) Front porch: 2 lines (FP = ) Frame frequency: 6 Hz Frequency fluctuation: % Page 34 of Version: 43

35 Internal oscillator clock (fosc) [Hz] = 6 x [ ] x clocks x (/9) 394KHz When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration In the above example, the calculated internal clock frequency with ±% margin variation is considered and ensures to complete the display operation within one VSYNC cycle The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation Minimum speed for RAM writing [Hz] > 24 x 32 x 394K / [ ( )lines x clocks] 57 MHz The above theoretical value is calculated based on the premise that the starts to write data into the internal GRAM on the falling edge of VSYNC There must at least be a margin of 2 lines between the physical display line and the GRAM line address where data writing operation is performed The GRAM write speed of 57MHz or more will guarantee the completion of GRAM write operation before the starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker Notes in using the VSYNC interface The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration 2 The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display 3 When switching from the internal clock operation mode (M[:] = ) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, ie after completing the display of the frame 4 The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to to transfer display data Page 35 of Version: 43

36 System Interface Mode to VSYNC interface mode System Interface VSYNC interface mode to System Interface Mode Opeartion through VSYNC interface Set AM= Set GRAM Address Set M[ : ]=, RM= for VSYNC interface mode Set index register to R 22h isplay operation in synchronization with internal clocks M [ :], RM become enable after completion of displaying frame Set M[:]=, RM= for system interface mode Wait more than frame System Interface isplay operation in synchronization with VSYNC M [ : ], RM become enable after completion of displaying frame isplay operation in synchronization with internal clocks Wait more than frame Write data to GRAM through VSYNC interface isplay operation in synchronization with VSYNC Note: input VSYNC for more than frame period after setting the M, RM register Opeartion through VSYNC interface Figure Transition flow between VSYNC and internal clock operation modes Page 36 of Version: 43

37 65 RGB Input Interface The RGB Interface mode is available for and the interface is selected by setting the RIM[:] bits as following table RIM RIM RGB Interface pins 8-bit RGB Interface [:] -bit RGB Interface [:], [:] 6-bit RGB Interface [:] Setting prohibited 8-bit RGB Interface (262K colors) Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B -bit RGB Interface (65K colors) Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 6-bit RGB Interface (262K colors) Input ata st Transfer 4 2nd Transfer 4 3rd Transfer 4 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure4 RGB Interface ata Format Page 37 of Version: 43

38 65 RGB Interface The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and OTCLK signals The RGB interface transfers the updated data to GRAM with the high-speed write function and the update area is defined by the window address function The back porch and front porch are used to set the RGB interface timing VSYNC Back porch period (BP[3:]) RAM data display area Moving picture display area isplay period (NL[4:] Front porch period (FP[3:]) HSYNC OTCLK ENABLE [:] Note : Front porch period continues until the next input of VSYNC Note 2: Input OTCLK throughout the operation Note 3: Supply the VSYNC, HSYNC and OTCLK with frequency that can meet the resolution requirement of panel Figure GRAM Access Area by RGB Interface Page 38 of Version: 43

39 652 RGB Interface Timing The timing chart of 8-/-bit RGB interface mode is shown as follows frame Back porch Front porch VSYNC VLW >= H HSYNC OTCLK ENABLE [:] HSYNC HLW >= 3 OTCLK // H OTCLK // TST >= HLW ENABLE // [:] Valid data VLW: VSYNC low period HLW: HSYNC low period TST: data transfer startup time Figure Timing Chart of Signals in 8-/-bit RGB Interface Mode Page 39 of Version: 43

40 The timing chart of 6-bit RGB interface mode is shown as follows frame Back porch Front porch VSYNC VLW >= H HSYNC OTCLK ENABLE [:] HSYNC HLW >= 3 OTCLK // H OTCLK // TST >= HLW ENABLE // [:] R G B R G B B R G B // Valid data VLW: VSYNC low period HLW: HSYNC low period TST: data transfer startup time Note ) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with OTCLKs Note 2) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of OTCLKs Figure Timing chart of signals in 6-bit RGB interface mode Page 4 of Version: 43

41 653 Moving Picture Mode has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture The window address function defined the update area of GRAM Only the moving picture area of GRAM is updated When display the moving picture in RGB interface mode, the [:] can be switched as system interface to update still picture area and registers, such as icons RAM access via a system interface in RGB-I/F mode allows GRAM access via the system interface in RGB interface mode In RGB interface mode, data are written to the internal GRAM in synchronization with OTCLK and ENABLE signals When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = ) and the still picture of GRAM When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = and the index register to R22h to start accessing RAM via the RGB interface If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM The following figure illustrates the operation of the when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface Still Picture Area Moving Picture Area Update a frame Update a frame VSYNC ENABLE OTCLK [:] Set IR to R22h Update moving picture area Set RM= Set A[:] Set IR to R22h Update display data in other than the moving picture area Set A[:] Set RM= Set IR to R22h Update moving picture area Figure8 Example of update the still and moving picture Page 4 of Version: 43

42 654 6-bit RGB Interface The 6-bit RGB interface is selected by setting the RIM[:] bits to The display operation is synchronized with VSYNC, HSYNC, and OTCLK signals isplay data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus ([:]) according to the data enable signal (ENABLE) Unused pins ([:]) must be fixed at GN level Registers can be set by the system interface (i8/spi) RGB interface with 6-bit data bus st Transfer 2 nd Transfer 3 rd Transfer Input a ta RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B ata transfer synchronization in 6-bit RGB interface mode has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (ie on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of OTCLK) Accordingly, the number of OTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly Otherwise it will affect the display of that frame as well as the next frame HSYNC ENABLE OTCLK [:] st 2 nd 3 rd st 2 nd 3 rd st 2 nd 3 rd st 2 nd 3 rd Transfer synchronization Page 42 of Version: 43

43 655 -bit RGB Interface The -bit RGB interface is selected by setting the RIM[:] bits to The display operation is synchronized with VSYNC, HSYNC, and OTCLK signals isplay data are transferred to the internal RAM in synchronization with the display operation via -bit RGB data bus (-, -) according to the data enable signal (ENABLE) Registers are set only via the system interface -bit RGB Interface (65K colors) Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B bit RGB Interface The 8-bit RGB interface is selected by setting the RIM[:] bits to The display operation is synchronized with VSYNC, HSYNC, and OTCLK signals isplay data are transferred to the internal RAM in synchronization with the display operation via 8-bit RGB data bus ([:]) according to the data enable signal (ENABLE) Registers are set only via the system interface RGB interface with 8-bit data bus Input ata RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Notes in using the RGB Input Interface The following are the functions not available in RGB Input Interface mode Function RGB interface I8 system interface Partial display Not available Available Scroll function Not available Available Interlaced scan Not available Available 2 VSYNC, HSYNC, and OTCLK signals must be supplied throughout a display operation period 3 The periods set with the NO[:] bits (gate output non-overlap period), ST[:] bits (source output delay period) and EQ[:] bits (equalization period) are not based on the internal clock but based on OTCLK in Page 43 of Version: 43

44 RGB interface mode 4 In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a OTCLK input In other words, it takes 3 OTCLK inputs to transfer one pixel Be sure to complete data transfer in units of 3 OTCLK inputs in 6-bit RGB interface mode 5 In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of 3 OTCLK Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE, [:]) to contain OTCLK inputs of a multiple of 3 to complete data transfer in units of pixels 6 When switching from the internal operation mode to the RGB Input Interface mode, or the other way around, follow the sequence below 7 In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame 8 In RGB interface mode, a RAM address (A[:]) is set in the address counter every frame on the falling edge of VSYNC Internal clock operation to RGB I/F RGB I/F to Internal clock operation Internal clock operation AM= Set A[:] Set RGB Interface mode M[:]= and RM= Set IR to R22h (GRAM data write) Note Internal clock operation * SPI interface can be used to set the registers and data * M[:] and RM become enable after completion of display frame RGB Interface Operation Set Internal Clock Operation mode M[:]= and RM= Wait for more than frame Internal clock operation RGB Interface (isplay operation in synchronization with VSYNC, HSYNC, OTCLK) * M[:] and RM become enable after completion of display frame isplay operation in synchronization with internal clock Wait for more than frame Write data through RGB I/F RGB Interface (isplay operation in synchronization with VSYNC, HSYNC, OTCLK) RGB Interface Operation Note: Input RGB Interface signals (VSYNC, HSYNC, OTCLK) before setting M[;] and RM to the RGB interface mode Figure9 Internal clock operation/rgb interface mode switching Page 44 of Version: 43

45 Write data through RGB interface to write da ta through syste m interface RGB Interface operation Set M=, RM= with RGB interface mode Write data through system interface to write data through RGB interface System Interface operation Write data to GRAM through system interface S et A[;] Set A[;] Set IR to R22h (G RAM data write) Set M=, RM= with RGB interface mode Write data to GRAM through syste m interface Syste m Interfa ce operation Set IR to R22h (GRAM data write) RGB Interface operation Figure2 GRAM access between system interface and RGB interface Page 45 of Version: 43

46 66 Interface Timing The following are diagrams of interfacing timing with LC panel control signals in internal operation and RGB interface modes VS YNC // HSYNC // OTCLK // ENABLE [:] // // FLM G G2 G32 S[72:] // VCOM Figure2 Relationship between RGB I/F signals and LC riving Signals for Panel Page 46 of Version: 43

47 7 Register escriptions 7 Registers Access adopts 8-bit bus interface architecture for high-performance microprocessor All the functional blocks of starts to work after receiving the correct instruction from the external microprocessor by the 8-, -, 9-, 8-bit interface The index register (IR) stores the register address to which the instructions and display data will be written The register selection signal (RS), the read/write signals (n/nwr) and data bus - are used to read/write the instructions and data of The registers of the are categorized into the following groups Specify the index of register (IR) 2 Read a status 3 isplay control 4 Power management Control 5 Graphics data processing 6 Set internal GRAM address (AC) 7 Transfer data to/from the internal GRAM (R22) 8 Internal grayscale γ-correction (R3 ~ R39) Normally, the display data (GRAM) is most often updated, and in order since the can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function, there are fewer loads on the program in the microprocessor As the following figure shows, the way of assigning data to the register bits ([:]) varies for each interface Send registers in accordance with the following data transfer format S erial P eripheral Interface for register access SPI Input ata Register ata Figure22 Register Setting with Serial Peripheral Interface (SPI) Page 47 of Version: 43

48 i8/m68 system 8-bit data bus interface ata Bus ([:]) Register Bit ([:]) i8/m68 system -bit data bus interface ata Bus ([:]), ([8:]) Register Bit ([:]) i8/m68 system 9-bit data bus interface ata Bus ([:9]) 4 st Transfer nd Transfer 9 Register Bit ([:]) i8/m68 system 8-bit data bus interface/serial peripheral interface (2/3 transmission) ata Bus ([:]) st Tra nsfe r 4 2 nd Tra nsfe r 4 Register Bit ([:]) Figure23 Register setting with i8 System Interface Page 48 of Version: 43

49 i8 8-/-bit System Bus Interface Timing (a) Write to register ncs RS n nwr [:] Write register inde x" Write re gis te r data" (b) Read from register ncs RS n nwr [:] Write register index" R e a d re gis te r data" i8 9-/8-bit System Bus Interface Timing (a) Write to register ncs RS n nwr [:] h" Write register inde x" Write register high byte data" Write register low byte data " (b) Read from register ncs RS n nwr [:] h" Write register inde x" Read register high byte data" Read register low byte data " Figure 24 Register Read/Write Timing of i8 System Interface Page 49 of Version: 43

50 72 Instruction escriptions No Registers Name R/W RS IR Index Register W I7 I6 I5 I4 I3 I2 I I h river Code Read RO h river Output Control W SM SS 2h LC riving Control W BC EOR 3h Entry Mode W TRI FM BGR ORG I/ I/ AM 4h Resize Control W RCV RCV RCH RCH RSZ RSZ 7h isplay Control W PTE PTE BASEE GON TE CL 8h isplay Control 2 W FP3 FP2 FP FP BP3 BP2 BP BP 9h isplay Control 3 W PTS2 PTS PTS PTG PTG ISC3 ISC2 ISC ISC Ah isplay Control 4 W FMARKOE FMI2 FMI FMI Ch RGB isplay Interface Control W ENC2 ENC ENC RM M M RIM RIM h Frame Maker Position W FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP FMP Fh RGB isplay Interface Control 2 W VSPL HSPL PL EPL h Power Control W SAP BT2 BT BT APE AP2 AP AP SLP STB h Power Control 2 W C C C C2 C C VC2 VC VC h Power Control 3 W VCIRE PON VRH3 VRH2 VRH VRH h Power Control 4 W VV4 VV3 VV2 VV VV 2h Horizontal GRAM Address Set W A7 A6 A5 A4 A3 A2 A A 2h Vertical GRAM Address Set W A A A4 A A A A A9 A8 22h Write ata to GRAM W RAM write data (-) / read data (-) bits are transferred via different data bus lines according to the selected interfaces 29h Power Control 7 W VCM5 VCM4 VCM3 VCM2 VCM VCM 2Bh Frame Rate and Color Control W FRS[3] FRS[2] FRS[] FRS[] 3h Gamma Control W KP[2] KP[] KP[] KP[2] KP[] KP[] 3h Gamma Control 2 W KP3[2] KP3[] KP3[] KP2[2] KP2[] KP2[] 32h Gamma Control 3 W KP5[2] KP5[] KP5[] KP4[2] KP4[] KP4[] 35h Gamma Control 4 W RP[2] RP[] RP[] RP[2] RP[] RP[] 36h Gamma Control 5 W VRP[4] VRP[3] VRP[2] VRP[] VRP[] VRP[3] VRP[2] VRP[] VRP[] 37h Gamma Control 6 W KN[2] KN[] KN[] KN[2] KN[] KN[] 38h Gamma Control 7 W KN3[2] KN3[] KN3[] KN2[2] KN2[] KN2[] 39h Gamma Control 8 W KN5[2] KN5[] KN5[] KN4[2] KN4[] KN4[] 3Ch Gamma Control 9 W RN[2] RN[] RN[] RN[2] RN[] RN[] 3h Gamma Control W VRN[4] VRN[3] VRN[2] VRN[] VRN[] VRN[3] VRN[2] VRN[] VRN[] 5h Horizontal Address Start W HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA HSA reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 5 of Version: 43

51 No Registers Name R/W RS Position 5h Horizontal Address End Position W HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA HEA 52h Vertical Address Start Position W VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA VSA 53h Vertical Address End Position W VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA VEA 6h river Output Control 2 W GS NL5 NL4 NL3 NL2 NL NL SCN5 SCN4 SCN3 SCN2 SCN SCN 6h Base Image isplay Control W NL VLE REV 6Ah Vertical Scroll Control W VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL VL 8h Partial Image isplay Position W PTP8 PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP PTP 8h Partial Image Area (Start Line) W PTSA8 PTSA7 PTSA6 PTSA5 PTSA4 PTSA3 PTSA2 PTSA PTSA 82h Partial Image Area (End Line) W PTEA8 PTEA7 PTEA6 PTEA5 PTEA4 PTEA3 PTEA2 PTEA PTEA 83h Partial Image 2 isplay Position W PTP8 PTP PTP PTP PTP4 PTP PTP PTP PTP 84h Partial Image 2 Area (Start Line) W PTSA8 PTSA PTSA PTSA PTSA4 PTSA PTSA PTSA PTSA 85h Partial Image 2 Area (End Line) W PTEA8 PTEA PTEA PTEA PTEA4 PTEA PTEA PTEA PTEA 9h Panel Interface Control W IVI IVI RTNI3 RTNI2 RTNI RTNI 92h Panel Interface Control 2 W NOWI2 NOWI NOWI 95h Panel Interface Control 4 W IVE IVE RTNE5 RTNE4 RTNE3 RTNE2 RTNE RTNE Ah OTP VCM Programming Control W OTP_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ PGM_EN OTP5 OTP4 OTP3 OTP2 OTP OTP A2h OTP VCM Status and Enable W PGM_ PGM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ CNT CNT EN A5h OTP Programming I Key W KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY reproduced, or disclosed in whole or in part without prior written permission of ILI Technology Corp Page 5 of Version: 43

52 72 Index (IR) R/W RS W I7 I6 I5 I4 I3 I2 I I The index register specifies the address of register (Rh ~ RFFh) or RAM which will be accessed 722 I code (Rh) R/W RS RO The device code 9325 h is read out when read this register 723 river Output Control (Rh) R/W RS W SM SS SS: Select the shift direction of outputs from the source driver When SS =, the shift direction of outputs is from S to S72 When SS =, the shift direction of outputs is from S72 to S In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins To assign R, G, B dots to the source driver pins from S to S72, set SS = To assign R, G, B dots to the source driver pins from S72 to S, set SS = When changing SS or BGR bits, RAM data must be rewritten SM: Sets the gate driver pin arrangement in combination with the GS bit (R6h) to select the optimal scan mode for the module Page 52 of Version: 43

53 SM GS Scan irection Gate Output Sequence G32 G38 G39 G3 Even-number TFT Panel Odd-number G2 to G32 G4 G2 G3 G G to G39 G, G2, G3, G4,,G3 G3, G38, G39, G32 G32 G38 G39 G3 Even-number TFT Panel Odd-number G2 to G32 G4 G2 G3 G G to G39 G32, G39, G38,, G6, G5, G4, G3, G2, G Even-number G32 G2 to G32 G2 TFT Panel G39 G Odd-number G to G39 G, G3, G5, G7,,G3 G3, G3, G3, G39 G2, G4, G6, G8,,G3 G34, G3, G38, G32 Page 53 of Version: 43

54 Even-number G32 TFT Panel G32, G38, G3,, G2 G, G8, G6, G4, G2 G2 to G32 G39 G Odd-number G to G39 G39, G3, G3,, G9, G78, G5, G3, G 724 LC riving Wave Control (R2h) R/W RS W B/C EOR B/C : Frame/Field inversion : Line inversion EOR: EOR = and B/C= to set the line inversion 725 Entry Mode (R3h) R/W RS W TRI FM BGR ORG I/ I/ AM AM Control the GRAM update direction When AM =, the address is updated in horizontal writing direction When AM =, the address is updated in vertical writing direction When a window area is set by registers R5h ~R53h, only the addressed GRAM area is updated based on I/[:] and AM bits setting I/[:] Control the address counter (AC) to automatically increase or decrease by when update one pixel display data Refer to the following figure for the details Page 54 of Version: 43

55 I/[:] = Horizontal : decrement Vertical : decreme nt I/[:] = Horizontal : increment Vertical : decreme nt I/[:] = Horizontal : decrement Vertical : increment I/[:] = Horizontal : increment Ve rtical : increment AM = E E B B Horizontal B B E E AM = E E B B Ve rtica l B B E E Figure25 GRAM Access irection Setting ORG Moves the origin address according to the I setting when a window address area is made This function is enabled when writing data with the window address area using high-speed RAM write ORG = : The origin address is not moved In this case, specify the address to start write operation according to the GRAM address map within the window address area ORG = : The original address h moves according to the I/[:] setting Notes: When ORG=, only the origin address address h can be set in the RAM address set registers R2h, and R2h 2 In RAM read operation, make sure to set ORG= BGR Swap the R and B order of written data BGR= : Follow the RGB order to write the pixel data BGR= : Swap the RGB data to BGR in writing into GRAM TRI When TRI =, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface It is also possible to send data via the -bit interface or SPI in the transfer mode that realizes display in 262k colors in combination with FM bits When not using these interface modes, be sure to set TRI = FM Set the mode of transferring data to the internal RAM when TRI = See the following figures for details Page 55 of Version: 43

56 TRI FM -bit MPU System Interface ata Format system -bit interface ( transfers/pixel) 65,536 colors * 4 st Transfer R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system -bit interface (2 transfers/pixel) 262,44 colors 4 st Transfer nd Transfer R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system -bit interface (2 transfers/pixel) 262,44 colors st Transfer 2 4 2nd Transfer R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure26 -bit MPU System Interface ata Format TRI FM 8-bit MPU System Interface ata Format system 8-bit interface (2 transfers/pixel) 65,536 colors * st Transfer 4 2nd Transfer 4 R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system 8-bit interface (3 transfers/pixel) 262,44 colors st Transfer 2nd Transfer 4 3rd Transfer 4 R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B 8-system 8-bit interface (3 transfers/pixel) 262,44 colors st Transfer 4 2nd Transfer 4 3rd Transfer 4 R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Figure27 8-bit MPU System Interface ata Format 726 Resizing Control Register (R4h) R/W RS W RCV RCV RCH RCH RSZ RSZ RSZ[:] Sets the resizing factor When the RSZ bits are set for resizing, the writes the data according to the resizing factor so that the original image is displayed in horizontal and vertical dimensions, which are contracted Page 56 of Version: 43

57 according to the factor respectively See Resizing function RCH[:] Sets the number of remainder pixels in horizontal direction when resizing a picture By specifying the number of remainder pixels by RCH bits, the data can be transferred without taking the reminder pixels into consideration Make sure that RCH = 2 h when not using the resizing function (RSZ = 2 h) or there are no remainder pixels RCV[:] Sets the number of remainder pixels in vertical direction when resizing a picture By specifying the number of remainder pixels by RCV bits, the data can be transferred without taking the reminder pixels into consideration Make sure that RCV = 2 h when not using the resizing function (RSZ = 2 h) or there are no remainder pixels RSZ[:] Resizing factor No resizing (x) x /2 Setting prohibited x /4 RCH[:] Number of remainder Pixels in Horizontal irection pixel* pixel 2 pixel 3 pixel RCV[:] Number of remainder Pixels in Vertical irection pixel* pixel 2 pixel 3 pixel * pixel = RGB 727 isplay Control (R7h) R/W RS W PTE PTE BASEE GON TE CL [:] Set [:]= to turn on the display panel, and [:]= to turn off the display panel A graphics display is turned on the panel when writing =, and is turned off when writing = When writing =, the graphics display data is retained in the internal GRAM and the displays the data when writing = When =, ie while no display is shown on the panel, all source outputs becomes the GN level to reduce charging/discharging current, which is generated within the LC while driving liquid crystal with AC voltage When the display is turned off by setting [:] =, the continues internal display operation When the display is turned off by setting [:] =, the internal display operation is halted completely In combination with the GON, TE setting, the [:] setting controls display ON/OFF Page 57 of Version: 43

58 BASEE Source, VCOM Output internal operation GN Halt GN Operate Non-lit display Operate Non-lit display Operate Base image display Operate Note: data write operation from the microcontroller is performed irrespective of the setting of [:] bits 2 The [:] setting is valid on both st and 2 nd displays 3 The non-lit display level from the source output pins is determined by instruction (PTS) CL When CL =, the 8-color display mode is selected CL Colors 262,44 8 GON and TE Set the output level of gate driver G ~ G32 as follows GON TE G ~G32 Gate Output VGH VGH VGL Normal isplay BASEE Base image display enable bit When BASEE =, no base image is displayed The drives liquid crystal at non-lit display level or displays only partial images When BASEE =, the base image is displayed The [:] setting has higher priority over the BASEE setting PTE[:] Partial image 2 and Partial image enable bits PTE/ = : turns off partial image Only base image is displayed PTE/ = : turns on partial image Set the base image display enable bit to (BASEE = ) 728 isplay Control 2 (R8h) R/W RS W FP3 FP2 FP FP BP3 BP2 BP BP FP[3:]/BP[3:] The FP[3:] and BP[3:] bits specify the line number of front and back porch periods respectively When setting the FP[3:] and BP[3:] value, the following conditions shall be met: BP + FP lines FP 2 lines BP 2 lines Page 58 of Version: 43

59 Set the BP[3:] and FP[3:] bits as below for each operation modes Operation Mode BP FP BP+FP I8 System Interface Operation Mode BP 2 lines FP 2 lines FP +BP lines RGB interface Operation BP 2 lines FP 2 lines FP +BP lines VSYNC interface Operation BP 2 lines FP 2 lines FP +BP = lines FP[3:] Number of lines for Front Porch BP[3:] Number of lines for Back Porch Setting Prohibited Setting Prohibited 2 lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines lines lines lines lines 4 lines Setting Prohibited VSYNC Back Porch isplay Area Front Porch Note: The output timing to the LC is delayed by 2 lines period from the input of synchronizing signal 729 isplay Control 3 (R9h) R/W RS W PTS2 PTS PTS PTG PTG ISC3 ISC2 ISC ISC ISC[3:]: Specify the scan cycle interval of gate driver in non-display area when PTG[:]= to select interval scan Then scan cycle is set as odd number from ~29 frame periods The polarity is inverted every scan cycle ISC3 ISC3 ISC3 ISC3 Scan Cycle f FLM =6 Hz frame - frame ms 3 frame 5ms 5 frame 84ms 7 frame ms 9 frame ms frame 84ms frame 2ms frame 25ms frame 284ms 9 frame 3ms 2 frame 35ms 23 frame 384ms 25 frame 48ms 27 frame 45ms 29 frame 484ms Page 59 of Version: 43

60 PTG[:] Set the scan mode in non-display area PTG PTG Gate outputs in non-display area Source outputs in non-display area Vcom output Normal scan Set with the PTS[2:] bits VcomH/VcomL Setting Prohibited - - Interval scan Set with the PTS[2:] bits VcomH/VcomL Setting Prohibited - - PTS[2:] Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays) When PTS[2] =, the operation of amplifiers which generates the grayscales other than V and V63 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption PTS[2:] Source output level Grayscale amplifier Positive polarity Negative polarity in operation Step-up clock frequency V63 V V63 to V Register Setting (C, C) Setting Prohibited Setting Prohibited - - GN GN V63 to V Register Setting (C, C) Hi-Z Hi-Z V63 to V Register Setting (C, C) V63 V V63 and V frequency setting by C, C Setting Prohibited Setting Prohibited - - GN GN V63 and V frequency setting by C, C Hi-Z Hi-Z V63 and V frequency setting by C, C Notes: The power efficiency can be improved by halting grayscale amplifiers and slowing down the step-up clock frequency only in non-display drive period 2 The gate output level in non-lit display area drive period is determined by PTG[:] 72 isplay Control 4 (RAh) R/W RS W FMARKOE FMI2 FMI FMI FMI[2:] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate FMARKOE When FMARKOE=, starts to output FMARK signal in the output interval set by FMI[2:] bits FMI[2:] Output Interval frame 2 frame 4 frame 6 frame Others Setting disabled Page 6 of Version: 43

61 72 RGB isplay Interface Control (RCh) R/W RS W ENC2 ENC ENC RM M M RIM RIM RIM[:] Select the RGB interface data width RIM RIM RGB Interface Mode 8-bit RGB interface ( transfer/pixel), [:] -bit RGB interface ( transfer/pixel), [:] and [:] 6-bit RGB interface (3 transfers/pixel), [:] Setting disabled Note: Registers are set only by the system interface Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch M[:] Select the display operation mode M M isplay Interface Internal system clock RGB interface VSYNC interface Setting disabled The M[:] setting allows switching between internal clock operation mode and external display interface operation mode However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited RM Select the interface to access the GRAM Set RM to when writing display data by the RGB interface RM Interface for RAM Access System interface/vsync interface RGB interface isplay State Operation Mode RAM Access (RM) isplay Operation Mode (M[:] Still pictures Internal clock operation Moving pictures RGB interface () Rewrite still picture area while RGB interface isplaying moving pictures Moving pictures VSYNC interface System interface (RM = ) RGB interface (RM = ) System interface (RM = ) System interface (RM = ) Note : Registers are set only via the system interface or SPI interface Note 2: Refer to the flowcharts of RGB Input Interface section for the mode switch Internal clock operation (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) VSYNC interface (M[:] = ) ENC[2:] Set the GRAM write cycle through the RGB interface ENC[2:] GRAM Write Cycle (Frame periods) Frame 2 Frames 3 Frames 4 Frames Page 6 of Version: 43

62 5 Frames 6 Frames 7 Frames 8 Frames 72 Frame Marker Position (h) R/W RS W FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP2 FMP FMP FMP[8:] Sets the output position of frame cycle (frame marker) When FMP[8:]=, a high-active pulse FMARK is output at the start of back porch period for one display line period (H) Make sure the 9 h FMP BP+NL+FP FMP[8:] FMARK Output Position 9 h th line 9 h st line 9 h2 2 nd line 9 h3 3 rd line 9 h5 373 rd line 9 h6 374 th line 9 h7 375 th line 72 RGB isplay Interface Control 2 (RFh) R/W RS W VSPL HSPL EPL PL PL: Sets the signal polarity of the OTCLK pin PL = The data is input on the rising edge of OTCLK PL = The data is input on the falling edge of OTCLK EPL: Sets the signal polarity of the ENABLE pin EPL = The data - is written when ENABLE = isable data write operation when ENABLE = EPL = The data - is written when ENABLE = isable data write operation when ENABLE = HSPL: Sets the signal polarity of the HSYNC pin HSPL = Low active HSPL = High active VSPL: Sets the signal polarity of the VSYNC pin VSPL = Low active VSPL = High active Page 62 of Version: 43

63 724 Power Control (Rh) R/W RS W SAP BT2 BT BT APE AP2 AP AP SLP STB SLP: When SLP =, enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption In the sleep mode, the GRAM data and instructions cannot be updated except the following two instructions a Exit sleep mode (SLP = ) b Start oscillation STB: When STB =, enters the standby mode and the display operation stops except the GRAM power supply to reduce the power consumption In the STB mode, the GRAM data and instructions cannot be updated except the following two instructions a Exit standby mode (STB = ) b Start oscillation AP[2:]: Adjusts the constant current in the operational amplifier circuit in the LC power supply circuit The larger constant current enhances the drivability of the LC, but it also increases the current consumption Adjust the constant current taking the trade-off into account between the display quality and the current consumption In no-display period, set AP[2:] = to halt the operational amplifier circuits and the step-up circuits to reduce current consumption AP[2:] Gamma driver amplifiers Source driver amplifiers Halt Halt SAP: Source river output control SAP=, Source driver is disabled SAP=, Source driver is enabled When starting the charge-pump of LC in the Power ON stage, make sure that SAP=, and set the SAP=, after starting up the LC power supply circuit APE: Power supply enable bit Set APE = to start the generation of power supply according to the power supply startup sequence BT[3:]: Sets the factor used in the step-up circuits Select the optimal step-up factor for the operating voltage To reduce power consumption, set a smaller factor Page 63 of Version: 43

64 BT[2:] VH VCL VGH VGL 3 h Vci x 2 - Vci - Vci x 5 3 h Vci x 6 - Vci x 4 Vci x 2 - Vci 3 h2 - Vci x 3 3 h3 - Vci x 5 3 h4 Vci x 2 - Vci Vci x 5 - Vci x 4 3 h5 - Vci x 3 3 h6 - Vci x 4 Vci x 2 - Vci Vci x 4 3 h7 - Vci x 3 Notes: Connect capacitors to the capacitor connection pins when generating VH, VGH, VGL and VCL levels 2 Make sure VH = 6V (max), VGH = V (max), VGL = 5V (max) and VCL= -3V (max) 72 Power Control 2 (Rh) R/W RS W C C C C2 C C VC2 VC VC VC[2:] Sets the ratio factor of Vci to generate the reference voltages Vci VC2 VC VC Vci voltage 95 x Vci 9 x Vci 85 x Vci 8 x Vci 75 x Vci 7 x Vci isabled x Vci C[2:]: Selects the operating frequency of the step-up circuit The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption Adjust the frequency taking the trade-off between the display quality and the current consumption into account C[2:]: Selects the operating frequency of the step-up circuit 2 The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption Adjust the frequency taking the trade-off between the display quality and the current consumption into account C2 C C Step-up circuit step-up frequency (f CC ) C C C Step-up circuit2 step-up frequency (f CC2 ) Fosc Fosc / 4 Fosc / 2 Fosc / 8 Fosc / 4 Fosc / Fosc / 8 Fosc / 32 Fosc / Fosc / 64 Fosc / 32 Fosc / 8 Fosc / 64 Fosc / 256 Halt step-up circuit Halt step-up circuit 2 Page 64 of Version: 43

65 Note: Be sure f CC f CC2 when setting C[2:] and C[2:] 72 Power Control 3 (Rh) R/W RS W VCIRE PON VRH3 VRH2 VRH VRH VRH[3:] Set the amplifying rate ( ~ 9) of Vci applied to output the VREGOUT level, which is a reference level for the VCOM level and the grayscale voltage level VCIRE: Select the external reference voltage Vci or internal reference voltage VCIR VCIRE= External reference voltage Vci (default) VCIRE = Internal reference voltage 25V VCIRE = VCIRE = VRH3 VRH2 VRH VRH VREGOUT VRH3 VRH2 VRH VRH VREGOUT Halt Halt Vci x 2 25V x 2 = 5V Vci x 25 25V x 25 = 55V Vci x 2 25V x 2 = 525V Vci x 22 25V x 22 = 55V Vci x 23 25V x 23 = 575V Vci x 24 25V x 24 = 6V Vci x 24 25V x 24 = 6V Vci x 25V x = 4V Vci x 5 25V x 5 = 45V Vci x 25V x = 425V Vci x 5 25V x 5 = 4375V Vci x 8 25V x 8 = 45V Vci x 85 25V x 85 = 4625V Vci x 9 25V x 9 = 475V Vci x 95 25V x 95 = 4875V When VCI<25V, Internal reference voltage will be same as VCI Make sure that VC and VRH setting restriction: VREGOUT (VH - 2)V PON: Control ON/OFF of circuit3 (VGL) output PON= VGL output is disable PON= VGL output is enable 72 Power Control 4 (Rh) R/W RS W VV4 VV3 VV2 VV VV VV[4:] Select the factor of VREGOUT to set the amplitude of Vcom alternating voltage from 7 to 4 x VREGOUT VV4 VV3 VV2 VV VV VCOM amplitude VV4 VV3 VV2 VV VV VCOM amplitude Page 65 of Version: 43

66 Set VV[4:] to let Vcom amplitude less than 6V 728 GRAM Horizontal/Vertical Address Set (R2h, R2h) R/W RS W A7 A6 A5 A4 A3 A2 A A W A A A4 A A A A A9 A8 A[:] Set the initial value of address counter (AC) The address counter (AC) is automatically updated in accordance to the setting of the AM, I/ bits as data is written to the internal GRAM The address counter is not automatically updated when read data from the internal GRAM A[:] GRAM ata Map h ~ hef st line GRAM ata h ~ hef 2 nd line GRAM ata h2 ~ h2ef 3 rd line GRAM ata h3 ~ h3ef 4 th line GRAM ata h ~ hef 38 th line GRAM ata he ~ heef 39 th line GRAM ata hf ~ hfef 32 th line GRAM ata Note: When the RGB interface is selected (RM = ), the address A[:] is set to the address counter every frame on the falling edge of VSYNC Note2: When the internal clock operation or the VSYNC interface mode is selected (RM = ), the address A[:] is set to address counter when update register R2 729 Write ata to GRAM (R22h) R/W RS W RAM write data ([:], the [:] pin assignment differs for each interface This register is the GRAM access port When update the display data through this register, the address counter (AC) is increased/decreased automatically 722 Read ata from GRAM (R22h) R/W RS Page 66 of Version: 43

67 R RAM Read ata ([:], the [:] pin assignment differs for each interface [:] Read 8-bit data from GRAM through the read data register (R) 8-bit System Interface GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Write ata Register Output ata bit System Interface GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Write ata Register Output ata bit System Interface GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Write ata Register Output ata 4 st Transfer 9 4 2nd Transfer 9 8-bit System Interface / Serial ata Transfer Interface GRAM ata & RGB Mapping R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Write ata Register Output ata 4 st Transfer 4 2nd Transfer Figure 28 ata Read from GRAM through Read ata Register in 8-/-/9-/8-bit Interface Mode Page 67 of Version: 43

68 Set I/ AM, HAS/HEA, VSA/VEA Set address M ummy read (invalid data) GRAM -> Read data latch Read Output (data of address M) Read datalatch -> [:] Read Output (data of address M+) Read datalatch -> [:] Set address N ummy read (invalid data) GRAM -> Read data latch Read Output (data of address N) Read datalatch -> [:] Figure 29 GRAM ata Read Back Flow Chart 722 Power Control 7 (R29h) R/W RS W VCM5 VCM4 VCM3 VCM2 VCM VCM VCM[5:] Set the internal VcomH voltage VCM5 VCM4 VCM3 VCM2 VCM VCM VCOMH VCM5 VCM4 VCM3 VCM2 VCM VCM VCOMH Page 68 of Version: 43

69 Frame Rate and Color Control (R2Bh) R/W RS W FRS3 FRS2 FRS FRS FRS[4:] Set the frame rate when the internal resistor is used for oscillator circuit FRS[3:] FRS[3:] Frame Rate 4 h 3 Page 69 of Version: 43

70 4 h 3 4 h h h h5 4 4 h h h8 5 4 h ha 62 4 hb 7 4 hc 8 4 h 93 4 he 4 hf Setting Prohibited 7223 Gamma Control (R3h ~ R3h) R/W RS R3h W KP[2] KP[] KP[] KP[2] KP[] KP[] R3h W KP3[2] KP3[] KP3[] KP2[2] KP2[] KP2[] R32h W KP5[2] KP5[] KP5[] KP4[2] KP4[] KP4[] R35h W RP[2] RP[] RP[] RP[2] RP[] RP[] R36h W VRP[4] VRP[3] VRP[2] VRP[] VRP[] VRP[3] VRP[2] VRP[] VRP[] R37h W KN[2] KN[] KN[] KN[2] KN[] KN[] R38h W KN3[2] KN3[] KN3[] KN2[2] KN2[] KN2[] R39h W KN5[2] KN5[] KN5[] KN4[2] KN4[] KN4[] R3Ch W RN[2] RN[] RN[] RN[2] RN[] RN[] R3h W VRN[4] VRN[3] VRN[2] VRN[] VRN[] VRN[3] VRN[2] VRN[] VRN[] KP5-[2:] : γfine adjustment register for positive polarity RP-[2:] : γgradient adjustment register for positive polarity VRP-[4:] : γamplitude adjustment register for positive polarity KN5-[2:] : γfine adjustment register for negative polarity RN-[2:] : γgradient adjustment register for negative polarity VRN-[4:] : γamplitude adjustment register for negative polarity For details γ-correction Function section 7224 Horizontal and Vertical RAM Address Position (R5h, R5h, R52h, R53h) R/W RS R5h W HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA HSA R5h W HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA HEA R52h W VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA VSA R53h W VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA VEA Page 7 of Version: 43

71 HSA[7:]/HEA[7:] HSA[7:] and HEA[7:] represent the respective addresses at the start and end of the window address area in horizontal direction By setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data The HSA and HEA bits must be set before starting RAM write operation In setting these bits, be sure h HSA[7:]< HEA[7:] EF h and 4 h HEA-HAS VSA[8:]/VEA[8:] VSA[8:] and VEA[8:] represent the respective addresses at the start and end of the window address area in vertical direction By setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data The VSA and VEA bits must be set before starting RAM write operation In setting, be sure h VSA[8:]< VEA[8:] F h h HSA HEA VS A Window Address Are a VEA GRAM Addre s s Are a FEFh Figure 3 GRAM Access Range Configuration h HAS[7:] HEA[7:] EF h h VSA[7:] VEA[7:] F h Note The window address range must be within the GRAM address space Note2 ata are written to GRAM in four-words when operating in high speed mode, the dummy write operations should be inserted depending on the window address area For details, see the High-Speed RAM Write Function section 7225 Gate Scan Control (R6h, R6h, R6Ah) R/W RS R6h W GS NL5 NL4 NL3 NL2 NL NL SCN5 SCN4 SCN3 SCN2 SCN SCN R6h W NL VLE REV R6Ah W VL8 VL7 VL6 VL5 VL4 VL3 VL2 VL VL Page 7 of Version: 43

72 SCN[5:] The allows to specify the gate line from which the gate driver starts to scan by setting the SCN[5:] bits Scanning Start Position SCN[5:] SM= SM= GS= GS= GS= GS= h G G32 G G32 h G9 G3 G G34 2h G G34 G33 G288 3h G25 G296 G49 G272 4h G33 G288 G65 G256 5h G4 G28 G8 G24 6h G49 G272 G97 G224 7h G57 G264 G G28 8h G65 G256 G9 G92 9h G73 G248 G45 G6 Ah G8 G24 G G Bh G89 G232 G7 G44 Ch G97 G224 G93 G8 h G G2 G29 G Eh G G28 G2 G96 Fh G G2 G8 G8 h G9 G92 G34 G64 h G7 G84 G5 G48 h G45 G6 G66 G32 h G3 G8 G82 G 4h G G G98 G39 h G9 G2 G4 G33 h G7 G44 G G287 h G85 G6 G46 G27 8h G93 G8 G2 G255 9h G2 G G8 G239 Ah G29 G G94 G223 Bh G2 G4 G4 G27 Ch G225 G96 G G9 h G233 G88 G46 G5 Eh G24 G8 G2 G9 Fh G249 G72 G8 G43 2h G257 G64 G94 G7 2h G265 G56 G2 G 22h G273 G48 G226 G95 23h G28 G4 G242 G79 24h G289 G32 G258 G63 25h G297 G24 G274 G47 26h G35 G G29 G3 27h G3 G8 G36 G 28h ~ 3Fh Setting disabled Setting disabled Setting disabled Setting disabled NL[5:]: Sets the number of lines to drive the LC at an interval of 8 lines The GRAM address mapping is not affected by the number of lines set by NL[5:] The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel Page 72 of Version: 43

73 NL[5:] LC rive Line 6 h 8 lines 6 h lines 6 h2 24lines 6 h 24 lines 6 he 248 lines 6 hf 256 lines 6 h2 264 lines 6 h2 272 lines 6 h22 28 lines 6 h lines 6 h lines 6 h25 34 lines 6 h26 3 line 6 h27 32 line Others Setting inhibited NL: Sets the source driver output level in the non-display area NL Non-isplay Area Positive Polarity Negative Polarity V63 V V V63 GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:] and NL[4:] The scan direction determined by GS = can be reversed by setting GS = When GS =, the scan direction is from G to G32 When GS =, the scan direction is from G32 to G REV: Enables the grayscale inversion of the image by setting REV= Source Output in isplay Area REV GRAM ata Positive polarity negative polarity 8 h 8 h3ffff 8 h 8 h3ffff V63 V V V63 V V63 V63 V VLE: Vertical scroll display enable bit When VLE =, the starts displaying the base image from the line (of the physical display) determined by VL[8:] bits VL[8:] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display Note that the partial image display position is not affected by the base image scrolling The vertical scrolling is not available in external display interface operation In this case, make sure to Page 73 of Version: 43

74 set VLE = VLE Base Image isplay Fixed Enable Scrolling VL[8:]: Sets the scrolling amount of base image The base image is scrolled in vertical direction and displayed from the line determined by VL[8:] Make sure that VL[8:] Partial Image isplay Position (R8h) R/W RS W PT P[8] PTP[8:]: Sets the display start position of partial image The display areas of the partial images and 2 must not overlap each another PT P[7] PT P[6] PT P[5] PT P[4] PT P[3] PT P[2] PT P[] PT P[] 7227 Partial Image RAM Start/End Address (R8h, R82h) R/W RS W PTS A[8] PTS A[7] PTS A[6] PTS A[5] PTS A[4] PTS A[3] PTS A[2] PTS A[] PTS A[] W PTE PTE PTE PTE PTE PTE PTE PTE PTE A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[] A[] PTSA[8:] PTEA[8:]: Sets the start line address and the end line address of the RAM area storing the data of partial image Make sure PTSA[8:] PTEA[8:] 7228 Partial Image 2 isplay Position (R83h) R/W RS W PT P[8] PTP[8:]: Sets the display start position of partial image 2 The display areas of the partial images and 2 must not overlap each another PT P[7] PT P[6] PT P[5] PT P[4] PT P[3] PT P[2] PT P[] PT P[] 7229 Partial Image 2 RAM Start/End Address (R84h, R85h) R/W RS W PTS A[8] PTS A[7] PTS A[6] PTS A[5] PTS A[4] PTS A[3] PTS A[2] PTS A[] PTS A[] W PTE PTE PTE PTE PTE PTE PTE PTE PTE A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[] A[] PTSA[8:] PTEA[8:]: Sets the start line address and the end line address of the RAM area storing the data of partial image 2 Make sure PTSA[8:] PTEA[8:] Page 74 of Version: 43

75 723 Panel Interface Control (R9h) R/W RS W IVI IVI RTNI4 RTNI3 RTNI2 RTNI RTNI RTNI[4:]: Sets H (line) clock number of internal clock operating mode In this mode, display operation is synchronized with internal clock signal RTNI[4:] Clocks/Line RTNI[4:] Clocks/Line ~ Setting isabled 24 clocks clocks 25 clocks clocks 26 clocks 8 clocks 27 clocks 9 clocks 28 clocks 2 clocks 29 clocks 2 clocks 3 clocks 22 clocks 3 clocks 23 clocks IVI[:]: Sets the division ratio of internal clock frequency IVI IVI ivision Ratio Internal Operation Clock Frequency fosc / 2 fosc / 2 4 fosc / 4 8 fosc / Panel Interface Control 2 (R92h) R/W RS W NOWI[2] NOWI[] NOWI[] NOWI[2:]: Sets the gate output non-overlap period when display operation is synchronized with internal clock signal NOWI[2:] Gate Non-overlap Period clocks clocks 2 clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (IVI), from the reference point 7232 Panel Interface Control 4 (R95h) R/W RS W IVE IVE RTNE5 RTNE4 RTNE3 RTNE2 RTNE RTNE RTNE[5:]: Sets H (line) clock number of RGB interface mode In this mode, display operation is Page 75 of Version: 43

76 synchronized with RGB interface signals IVE (division ratio) x RTNE (OTCLKs) OTCLKs in H period RTNE[5:] Clocks per line period Clocks per line period Clocks per line period Clocks per line period RTNE[5:] RTNE[5:] RTNE[5:] (H) (H) (H) (H) h Setting Prohibited h clocks 2h 32 clocks 3h 48 clocks h Setting Prohibited h clocks 2h 33 clocks 3h 49 clocks 2h Setting Prohibited h 8 clocks 22h 34 clocks 32h 5 clocks 3h Setting Prohibited h 9 clocks 23h 35 clocks 33h 5 clocks 4h Setting Prohibited 4h 2 clocks 24h 36 clocks 34h 52 clocks 5h Setting Prohibited h 2 clocks 25h 37 clocks 35h 53 clocks 6h Setting Prohibited h 22 clocks 26h 38 clocks 36h 54 clocks 7h Setting Prohibited h 23 clocks 27h 39 clocks 37h 55 clocks 8h Setting Prohibited 8h 24 clocks 28h 4 clocks 38h 56 clocks 9h Setting Prohibited 9h 25 clocks 29h 4 clocks 39h 57 clocks ah Setting Prohibited ah 26 clocks 2ah 42 clocks 3ah 58 clocks bh Setting Prohibited bh 27 clocks 2bh 43 clocks 3bh 59 clocks ch Setting Prohibited ch 28 clocks 2ch 44 clocks 3ch 6 clocks dh Setting Prohibited dh 29 clocks 2dh 45 clocks 3dh 6 clocks eh Setting Prohibited eh 3 clocks 2eh 46 clocks 3eh 62 clocks fh Setting Prohibited fh 3 clocks 2fh 47 clocks 3fh 63 clocks IVE[:]: Sets the division ratio of OTCLK when display operation is synchronized with RGB interface signals IVE[:] ivision Ratio 8/-bit RGB Interface OTCLK=5MHz 6-bit x 3 Transfers RGB Interface OTCLK=5MHz Setting Prohibited Setting Prohibited - Setting Prohibited - /4 4 OTCLKS 8 μs OTCLKS 8 μs /8 8 OTCLKS μs 24 OTCLKS μs / OTCLKS 32 μs 48 OTCLKS 32 μs 7233 Panel Interface Control 5 (R97h) R/W RS W NOWE3 NOWE2 NOWE NOWE NOWE[2:]: Sets the gate output non-overlap period when the ILI932 display operation is synchronized with RGB interface signals NOWE[3:] Gate Non-overlap Period NOWE[3:] Gate Non-overlap Period clocks 8 clocks clocks 9 clocks 2 clocks clocks 3 clocks clocks 4 clocks clocks 5 clocks clocks 6 clocks 4 clocks 7 clocks clocks Note: clock = (number of data transfer/pixel) x IVE (division ratio) [OTCLK] 7234 OTP VCM Programming Control (RAh) R/W RS OTP_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ W PGM_EN OTP5 OTP4 OTP3 OTP2 OTP OTP OTP_PGM_EN: OTP programming enable When program OTP, must set this bit OTP data can be Page 76 of Version: 43

77 programmed 3 times VCM_OTP[5:]: OTP programming data for VCOMH voltage, the voltage refer to VCM[5:] value 7235 OTP VCM Status and Enable (RA2h) R/W RS PGM_ PGM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ VCM_ W CNT CNT EN PGM_CNT[:]: OTP programmed record These bits are read only OTP_PGM_CNT[:] escription OTP clean OTP programmed time OTP programmed 2 times OTP programmed 3 times VCM_[5:]: OTP VCM data read value These bits are read only VCM_EN: OTP VCM data enable : Set this bit to enable OTP VCM data to replace R29h VCM value : efault value, use R29h VCM value 7236 OTP Programming I Key (RA5h) R/W RS KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY KEY W KEY[:]: OTP Programming I key protection Before writing OTP programming data RAh, it must write RA5h with xaa55 value first to make OTP programming successfully If RA5h is not written with xaa55, OTP programming will be fail See OTP Programming flow Page 77 of Version: 43

78 8 OTP Programming Flow a-si TFT LC Single Chip river Start Power On Check OTP_PGM_CNT=? Y N Supply External 7V to VH Wait ms Set I Key RA5h=xAA55 Program OTP VCM ata RAh=x8xx (xx=6 bit VCM value) Wait ms Cut Off External 7V Power Reset End Page 78 of Version: 43

79 9 GRAM Address Map & Read/Write has an internal graphics RAM (GRAM) of 87, bytes to store the display data and one pixel is constructed of 8 bits The GRAM can be accessed through the i8 system, SPI and RGB interfaces i8 8-/-bit System Bus Interface Timing (a) Write to GRAM ncs RS n nwr [:] Write 22h"to index register Write GRAM data" Nth pixel Write GRAM data" (N+)th pixel Write GRAM data" (N+2)th pixel Write GRAM data" (N+3)th pixel (b) Re a d from GRAM ncs RS n nwr [:] Write 22h"to index register ummy Read st Read data" Nth pixel 2nd Read data" (N+)th pixel 3rd Read data" (N+2)th pixel i8 9-/8-bit S ystem Bus Interface Timing (a) Write to GRAM ncs RS n nwr [:9] h" 22h" st write high byte st write low byte 2nd write high byte 2nd write low byte 3rd write high byte 3rd write low byte Nth pixel (N+)th pixel (N+2)th pixel (b) Re a d from GRAM ncs RS n nwr [:9] h" 22h" ummy Read ummy Read 2 st read high byte st read low byte 2nd read high byte 2nd read low byte Nth pixel (N+)th pixel Figure3 GRAM Read/Write Timing of i8-system Interface Page 79 of Version: 43

80 GRAM address map table of SS=, BGR= SS=, BGR= S S3 S4 S6 S7 S9 S S S5 S59 S52 S522 S523 S525 S526 S72 GS= GS= G G32 h h 2h 3h ECh Eh EEh EFh G2 G39 h h h h ECh Eh EEh EFh G3 G38 2h 2h 22h 23h 2ECh 2Eh 2EEh 2EFh G4 G3 3h 3h 32h 33h 3ECh 3Eh 3EEh 3EFh G5 G3 4h 4h 42h 43h 4ECh 4Eh 4EEh 4EFh G6 G3 5h 5h 52h 53h 5ECh 5Eh 5EEh 5EFh G7 G34 6h 6h 62h 63h 6ECh 6Eh 6EEh 6EFh G8 G3 7h 7h 72h 73h 7ECh 7Eh 7EEh 7EFh G9 G3 8h 8h 82h 83h 8ECh 8Eh 8EEh 8EFh G G3 9h 9h 92h 93h 9ECh 9Eh 9EEh 9EFh G3 G 6h 6h 62h 63h 6ECh 6Eh 6EEh 6EFh G3 G9 7h 7h 72h 73h 7ECh 7Eh 7EEh 7EFh G3 G8 8h 8h 82h 83h 8ECh 8Eh 8EEh 8EFh G34 G7 9h 9h 92h 93h 9ECh 9Eh 9EEh 9EFh G3 G6 Ah Ah A2h A3h AECh AEh AEEh AEFh G3 G5 Bh Bh B2h B3h BECh BEh BEEh BEFh G3 G4 Ch Ch C2h C3h CECh CEh CEEh CEFh G38 G3 h h 2h 3h ECh Eh EEh EFh G39 G2 Eh Eh E2h E3h EECh EEh EEEh EEFh G32 G Fh Fh F2h F3h FECh FEh FEEh FEFh Page 8 of Version: 43

81 i8/m68 system 8-bit data bus interface GRAM ata RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (3n+) S (3n+2) S (3n+3) N= to 5 i8/m68 system -bit data bus interface GRAM ata RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (3n+) S (3n+2) S (3n+3) N= to 5 i8/m68 system 9-bit data bus interface st Transfer 2 nd Transfer GRAM ata RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (3n+) S (3n+2) S (3n+3) N= to 5 GRAM ata and display data of 8-/-/9-bit system interface (SS="", BGR="") Figure32 i8-system Interface with 8-/-/9-bit ata Bus (SS=, BGR= ) Page 8 of Version: 43

82 i8/m68 system 8-bit interface / SPI Interface (2 transfers/pixel) GRAM ata st tra nsfe r 4 2nd transfer 4 RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (3n+) S (3n+2) S (3n+3) N= to 5 i8/m68 system 8-bit interface (3 transfers/pixel, TRI="", FM[:]="") st Transfer 2 nd Transfer 3 rd Transfer GRAM ata 4 4 RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (3n+) S (3n+2) S (3n+3) N= to 5 i8/m68 system 8-bit interface (3 transfers/pixel, TRI="", FM[:]=") GRAM ata st Transfer 2 nd Transfer rd Transfer 4 RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (3n+) S (3n+2) S (3n+3) N= to 5 i8/m68 system 8-bit interface (SS="", BGR="") Figure33 i8-system Interface with 8-bit ata Bus (SS=, BGR= ) Page 82 of Version: 43

83 GRAM address map table of SS=, BGR= SS=, BGR= S72 S78 S7 S7 S74 S7 S7 S79 S S S9 S7 S6 S4 S3 S GS= GS= G G32 h h 2h 3h ECh Eh EEh EFh G2 G39 h h h h ECh Eh EEh EFh G3 G38 2h 2h 22h 23h 2ECh 2Eh 2EEh 2EFh G4 G3 3h 3h 32h 33h 3ECh 3Eh 3EEh 3EFh G5 G3 4h 4h 42h 43h 4ECh 4Eh 4EEh 4EFh G6 G3 5h 5h 52h 53h 5ECh 5Eh 5EEh 5EFh G7 G34 6h 6h 62h 63h 6ECh 6Eh 6EEh 6EFh G8 G3 7h 7h 72h 73h 7ECh 7Eh 7EEh 7EFh G9 G3 8h 8h 82h 83h 8ECh 8Eh 8EEh 8EFh G G3 9h 9h 92h 93h 9ECh 9Eh 9EEh 9EFh G3 G 6h 6h 62h 63h 6ECh 6Eh 6EEh 6EFh G3 G9 7h 7h 72h 73h 7ECh 7Eh 7EEh 7EFh G3 G8 8h 8h 82h 83h 8ECh 8Eh 8EEh 8EFh G34 G7 9h 9h 92h 93h 9ECh 9Eh 9EEh 9EFh G3 G6 Ah Ah A2h A3h AECh AEh AEEh AEFh G3 G5 Bh Bh B2h B3h BECh BEh BEEh BEFh G3 G4 Ch Ch C2h C3h CECh CEh CEEh CEFh G38 G3 h h 2h 3h ECh Eh EEh EFh G39 G2 Eh Eh E2h E3h EECh EEh EEEh EEFh G32 G Fh Fh F2h F3h FECh FEh FEEh FEFh Page 83 of Version: 43

84 i8/m68 system 8-bit data bus interface GRAM ata RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (528-3n) S (527-3n) S (526-3n) N= to 5 i8/m68 system 9-bit data bus interface st Transfer 2 nd Transfer GRAM ata RGB Assignment R5 R4 R3 R2 R R G5 G4 G3 G2 G G B5 B4 B3 B2 B B Source Output Pin S (528-3n) S (527-3n) S (526-3n) N= to 5 GRAM ata and display data of 8-/9-bit system interface (SS="", BGR="") Figure 34 i8-system Interface with 8-/9-bit ata Bus (SS=, BGR= ) Page 84 of Version: 43

85 Window Address Function a-si TFT LC Single Chip river The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM The window address area is made by setting the horizontal address register (start: HSA[7:], end: HEA[7:] bits) and the vertical address register (start: VSA[8:], end: VEA[8:] bits) The AM bit sets the transition direction of RAM address (either increment or decrement) These bits enable the to write data including image data consecutively not taking data wrap positions into account The window address area must be made within the GRAM address map area Also, the GRAM address bits (RAM address set register) must be an address within the window address area [Window address setting area] (Horizontal direction) H HSA[7:] HEA[7:] EF H (Vertical direction) H VSA[8:] VEA[8:] F H [RAM address, A (an address within a window address area)]] (RAM address) HSA[7:] A[7:] HEA[7:] VSA[8:] A[:8] VEA[8:] GRAM Address Map "h EF"h Window Address Area 2h 2h 23Fh 2Fh 4Fh 4F3Fh F"h FEF"h Window address setting area HSA[7:] = h, HSA[7:] = 3Fh, VSA[8:] = 2h, VSA[8:] = 4Fh, I/ = (increment) AM = (horizontal writing) Figure 35 GRAM Access Window Map Page 85 of Version: 43

86 Gamma Correction incorporates the γ-correction function to display 262,44 colors for the LC panel The γ-correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers for positive and negative polarities, to make available with liquid crystal panels of various characteristics VREGOUT PRP/N Gradient Adjus tme nt Register Fine Adjustme nt Re giste rs (6 x 3 bits) PRP/N PKP/N5 PKP/N4 PKP/N3 PKP/N2 PKP/N PKP/N VRP /N Amplitude Adjus tme nt Register VRP /N VgP /VgN V 8 to selection VgP /VgN V V2 8 to s e le ction VgP 8/VgN8 V7 V8 8 to selection VgP 2/VgN2 V2 8 to s e le ction VgP 43/VgN43 V43 8 to s e le ction VgP 55/VgN55 V55 V56 8 to selection VgP 62/VgN62 V6 V62 VgP 63/VgN63 V63 VGS Figure 36 Grayscale Voltage Generation Page 86 of Version: 43

87 VREGOUT uf/v VROP ~ 3R VRP [4:] VgP VRON ~ 3R VRN[4:] VgN 5R 4R{ RP RP RP2 RP3 RP4 RP5 RP6 RP7 VP VP 2 VP 3 VP 4 VP 5 VP 6 VP 7 VP 8 8 to Selection PKP[2:] VgP 5R 4R{ RN RN RN2 RN3 RN4 RN5 RN6 RN7 VN VN2 VN3 VN4 VN5 VN6 VN7 VN8 8 to Selection PKN[2:] VgN VRCP ~ 28R R{ RP8 RP9 RP RP RP RP RP4 PRP[2:] VP 9 VP VP VP VP VP 4 VP VP 8 to S e le ction PKP[2:] VgP 8 VRCP ~ 28R R{ RN8 RN9 RN RN RN RN RN4 PRN[2:] VN9 VN VN VN VN VN4 VN VN 8 to S e le ction PKN[2:] VgN8 R{ RP RP RP RP8 RP9 RP2 RP2 RP22 VP VP 8 VP 9 VP 2 VP 2 VP 22 VP 23 VP 24 8 to S e le ction PKP2[2:] VgP 2 R{ RN RN RN RN8 RN9 RN2 RN2 RN22 VN VN8 VN9 VN2 VN2 VN22 VN23 VN24 8 to S e le ction PKN2[2:] VgN2 R{ RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP3 VP 25 VP 26 VP 27 VP 28 VP 29 VP 3 VP 3 VP 32 8 to Selection PKP3[2:] VgP 43 R{ RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN3 VN25 VN26 VN27 VN28 VN29 VN3 VN3 VN32 8 to Selection PKN3[2:] VgN43 R{ RP3 RP32 RP33 RP34 RP35 RP36 RP37 RP38 VP 33 VP 34 VP 35 VP 36 VP 37 VP 38 VP 39 VP 4 8 to Selection PKP4[2:] VgP 55 R{ RN3 RN32 RN33 RN34 RN35 RN36 RN37 RN38 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN4 8 to Selection PKN4[2:] VgN55 VRCP ~ 28R 4R{ RP39 RP4 RP4 RP42 RP43 RP44 RP45 PRP[2:] VP 4 VP 42 VP 43 VP 44 VP 45 VP 46 VP 47 VP 48 8 to S e le ction PKP5[2:] VgP 62 VRCN ~ 28R 4R{ RN39 RN4 RN4 RN42 RN43 RN44 RN45 PRN[2:] VN4 VN42 VN43 VN44 VN45 VN46 VN47 VN48 8 to S e le ction PKN5[2:] VgN62 5R RP46 VP 49 VgP 63 5R RN46 VN49 VgN63 VROP ~ 3R VRP [4:] VRON ~ 3R VRN[4:] VGS 8R RP47 8R RN47 Figure 37 Grayscale Voltage Adjustment Page 87 of Version: 43

88 Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level To adjust the gradient, the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP[2:]/PRN[2:], PRP[2:]/PRN[2:] The registers consist of positive and negative polarity registers, allowing asymmetric drive 2 Amplitude adjustment registers The amplitude adjustment registers, VRP[3:]/VRN[3:], VRP[4:]/VRN[4:], are used to adjust the amplitude of grayscale voltages To adjust the amplitude, the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted Same as the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers 3 Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor, in respective 8-to- selectors Same with other registers, the fine adjustment registers consist of positive and negative polarity registers Grayscale voltage Grayscale voltage Grayscale voltage Gradient adjustment Amplitude adjustment Fine adjustment Figure 38 Gamma Curve Adjustment Register Groups Positive Polarity Negative Polarity escription Gradient PRP [2:] PRN [2:] Variable resistor VRCP, VRCN adjustment PRP [2:] PRN [2:] Variable resistor VRCP, VRCN Amplitude VRP [3:] VRN [3:] Variable resistor VROP, VRON adjustment VRP [4:] VRN [4:] Variable resistor VROP, VRON KP [2:] KN [2:] 8-to- selector (voltage level of grayscale ) KP [2:] KN [2:] 8-to- selector (voltage level of grayscale 8) Fine adjustment KP2 [2:] KN2 [2:] 8-to- selector (voltage level of grayscale 2) KP3 [2:] KN3 [2:] 8-to- selector (voltage level of grayscale 43) KP4 [2:] KN4 [2:] 8-to- selector (voltage level of grayscale 55) KP5 [2:] KN5 [2:] 8-to- selector (voltage level of grayscale 62) Page 88 of Version: 43

89 Ladder resistors and 8-to- selector Block configuration The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to- selectors Each 8-to- selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage Both variable resistors and 8-to- selectors are controlled according to the γ-correction registers This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels Variable resistors uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)/VRCP(N)); amplitude adjustment () (VROP(N)); and the amplitude adjustment (2) (VROP(N)) The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows Gradient adjustment Amplitude adjustment () Amplitude adjustment (2) PRP(N)/[2:] Register VRCP(N) Resistance VRP(N)[3:] Register VROP(N) Resistance VRP(N)[4:] Register VROP(N) Resistance R R R 4R 2R R 8R 4R 2R R : : : : R : : : : 2R 26R 29R 24R 28R 3R 28R 3R 3R 8-to- selectors The 8-to- selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)~6) The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages Fine adjustment registers and selected voltage Register Selected Voltage KP(N)[2:] VgP(N) VgP(N)8 VgP(N)2 VgP(N)43 VgP(N)55 VgP(N)62 VP(N) VP(N)9 VP(N) VP(N)25 VP(N)33 VP(N)4 VP(N)2 VP(N) VP(N)8 VP(N)26 VP(N)34 VP(N)42 VP(N)3 VP(N) VP(N)9 VP(N)27 VP(N)35 VP(N)43 VP(N)4 VP(N) VP(N)2 VP(N)28 VP(N)36 VP(N)44 VP(N)5 VP(N) VP(N)2 VP(N)29 VP(N)37 VP(N)45 VP(N)6 VP(N)4 VP(N)22 VP(N)3 VP(N)38 VP(N)46 VP(N)7 VP(N) VP(N)23 VP(N)3 VP(N)39 VP(N)47 VP(N)8 VP(N) VP(N)24 VP(N)32 VP(N)4 VP(N)48 Page 89 of Version: 43

90 Source river Output (S[384:]) VCOM Negative polarity Postive polarity Figure 39 Relationship between Source Output and VCOM V Negative Polarity Source Output Levels Positive Polarity V63 GRAM ata Figure 4 Relationship between GRAM ata and Output Level Page 9 of Version: 43

91 Application a-si TFT LC Single Chip river Configuration of Power Supply Circuit To Panel IM IM3 IM IM2 < ohm < ohm ohm < ohm UMMY TEST IOGNUM TESTO TESTO2 TESTO3 IM/I IM IM2 IM3 UMMY27 G39 G3 G3 G3 G3 G39 G37 G35 G33 nreset HSYNC ENABLE SI nwr ncs Fmark VS YNC OTCLK SO n RS < ohm < ohm ohm < ohm ohm < ohm ohm < ohm < ohm ohm ohm ohm ohm < ohm < ohm < ohm < ohm ohm < ohm < ohm < ohm < ohm < ohm < ohm ohm < ohm < ohm < ohm ohm < ohm < ohm < ohm TEST2 TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO nreset nreset VSYNC HSYNC OTCLK ENABLE 4 TESTO 9 8 TEST3 TESTO TESTO S O SI n nwr/scl RS ncs TESTO4 TESTO FMARK TESTO TS8 TS7 TS6 TS5 G G G G G9 G7 G5 G3 G UMMY26 UMMY25 S S2 S3 S4 S5 S6 S7 S8 S9 IOVCC uf/63v uf/63v < ohm < ohm < 5 ohm < 5 ohm < 5 ohm < ohm < 2 ohm TS4 TS3 TS2 TS TS UMMY2 IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC V V V V V V V V V V V UMMY3 GN GN GN GN GN GN GN GN VG S VG S GN GN GN GN GN GN GN GN GN GN UMMY4 UMMY5 UMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH Face Up (Bump View) S353 S354 S355 S356 S357 S358 S359 S36 UMMY24 uf/63v < 2 ohm uf/63v < 2 ohm uf/63v VCL < 2 ohm uf/v VH < ohm VCOML VCOML VCOML VCOML VREGOUT VREGOUT VREGOUT UMMY7 UMMY8 UMMY9 VCL VCL VCL VCL VCL VH VH VH VH VH x y UMMY23 S36 S362 S363 S364 S365 S366 S367 S368 S369 uf/63v < ohm VH VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI uf/63v uf/63v < 5 ohm < ohm < ohm < ohm VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI UMMY UMMY C- C- C- C- C- C+ C+ C+ C+ C+ C- C- C- C- C- C+ X VCL uf/25v uf/25v uf/63v uf/v uf/v < ohm < ohm < 4 ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm C+ C+ C+ C+ VG L VG L VG L VG L VG L VG L VG L VG L VG L VG L GN GN GN VGH VGH VGH VG H VG H VG H UMMY UMMY C- C- C- C- C+ C+ C+ C+ C2- C2- C2- C2- C2- C2- C2- C2+ C2+ C2+ C2+ C2+ C2+ C2+ C22- C22- C22- C22- C22- C22- C22- C22+ C22+ C22+ C22+ C22+ C22+ C22+ UMMY4 UMMY S7 S7 S74 S7 S7 S7 S78 S79 S72 UMMY22 UMMY2 G2 G4 G6 G8 G G G4 G G8 G34 G36 G38 G3 G3 G34 G3 G38 G32 UMMY2 To Panel Figure 4 Power Supply Circuit Block Page 9 of Version: 43

92 The following table shows specifications of external elements connected to the s power supply circuit Items Recommended Specification Pin connection Capacity µf (B characteristics) Schottky diode 63V V 25V VF<4V/2mA at 25 C, VR 3V (Recommended diode: HSC226) VREGOUT, VCI, V, VCL, VCOMH, VCOML, C+/-, C+/-, C+/-, VH, C2+/-, C22+/- VGH, VGL (VCL VGL), (VH VGH), (Vci VH) Page 92 of Version: 43

93 2 isplay ON/OFF Sequence Figure 42 isplay On/Off Register Setting Sequence Page 93 of Version: 43

94 3 Standby and Sleep Mode Standby Sleep isplay Off Sequence isplay Off Sequence Set Standby (STB = ) Set Sleep (SLP = ) Release from Standby (STB = ) Release from standby Release from Sleep (SLP = ) Release from Sleep R 9h R 9h 8ms or more Stabilizing time 8ms or more Stabilizing time isplay On Sequence isplay On Sequence Figure 43 Standby/Sleep Mode Register Setting Sequence Page 94 of Version: 43

95 4 Power Supply Configuration When supplying and cutting off power, follow the sequence below The setting time for step-up circuits and operational amplifiers depends on external resistance and capacitance Power Supply ON (V CC, V CI, IOV CC) VCI IOV CC Normal isplay isplay ON Setting TE= [:]= GON= GN VCI IOV CC or VCI, IOV CC Simultaneously isplay OFF Sequence Power On Reset and isplay OFF isplay OFF Setting TE = [:] = GON = PON = isplay OFF LC Power Supply ON Sequence Registers setting before power supply startup Power supply initial setting Set VC[2:], VRH[3:], VCM[5;], VV[5:], PON=,BT[2:] = Power Supply Halt Setting SAP= AP[2:] = PON = 5ms or more Stabilizing time Power Supply OFF (V CC, V CI, IOV CC) IOV CC VCI 8ms or more Step-up circuit stabilizing time Registers setting for power supply startup Power supply operation setting Set BT[2:],PON =, Set AP[2:],APE=, Set C[2:], C[2:] GN IOV CC VCI Or IOV CC, VCI Simultaneously Operational Amplifier stabilizing time Set the other registers isplay ON Sequence Set SAP= isplay ON TE= [:]= GON= Figure 44 Power Supply ON/OFF Sequence Page 95 of Version: 43

96 5 Voltage Generation The pattern diagram for setting the voltages and the waveforms of the voltages of the are as follows VGH (+9 ~ 5V) VLC (45 ~ 55V) VREGOUT (3 ~ (VLC-2)V ) VCOMH (3 ~ (VLC-2)V ) Vci (25 ~ 33V) VCOML (VCL+5) ~ -V ) VCL ( ~ -33V) VGL (-4 ~ -5V) Figure 45 Voltage Configuration iagram Note: The VH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs The voltage levels in the following relationships (VH VREGOUT ) > 2V and (VCOML VCL) > 5V are the actual voltage levels When the alternating cycles of VCOM are set high (eg the polarity inverts every line cycle), current consumption is large In this case, check the voltage before use Page 96 of Version: 43

97 6 Applied Voltage to the TFT panel VGH Gate Output VCOM Source output VGL Figure 46 Voltage Output to TFT LC Panel 7 Partial isplay Function The allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers The following example shows the setting for partial display function: Base Image isplay Setting BASEE NL[5:] 6 h27 Partial Image isplay Setting PTE PTSA[8:] 9 h PTEA[8:] 9 hf PTP[8:] 9 h8 Partial Image 2 isplay Setting PTE PTSA[8:] 9 h2 PTEA[8:] 9 h2f PTP[8:] 9 hc Page 97 of Version: 43

98 PTSA=9'h GRAM MAP Partial Image GRAM Area LC Panel (st line) (2nd line) 2 (3rd line) PTEA=9'hF PTSA=9'h2 PTEA=9'h2F Partial Image 2 GRAM Area Partial Image isplay Area PTP=9'h8 PTP=9'hC Partial Image isplay Area 39 (32th line) Figure 47 Partial isplay Example 8 Resizing Function supports resizing function (x/2, x/4), which is performed when writing image data to GRAM The resizing function is enabled by setting a window address area and the RSZ bit which represents the resizing factor (x/2, x/4) of image The resizing function allows the system to transfer the original-size image data into the GRAM with resized image data Page 98 of Version: 43

99 Original Image ata GRAM ata (,) (,) (2,) (3,) (4,) (5,) (,) (,) (2,) (3,) (4,) (5,) (,2) (,2) (2,2) (3,2) (4,2) (5,2) (,3) (,3) (2,3) (3,3) (4,3) (5,3) (,4) (,4) (2,4) (3,4) (4,4) (5,4) (,5) (,5) (2,5) (3,5) (4,5) (5,5) (,6) (,6) (2,6) (3,6) (4,6) (5,6) (6,) (6,) (6,2) (6,3) (6,4) (6,5) (6,6)? resizing (,) (2,) (4,) (,2) (2,2) (4,2) (,4) (2,4) (4,4) (6,) (6,2) (6,4) (,6) (2,6) (4,6) (6,6) Figure 48 ata transfer in resizing Origina l a ta 24 Panel isplay RSZ=2'h 32 Write to GRAM Figure 49 Resizing Example Original Image Size (X Y) Resized Image Resolution /2 (RSZ=2 h) /4 (RSZ=2 h3) The RSZ bit sets the resizing factor of an image When setting a window address area in the internal GRAM, the GRAM window address area must fit the size of resized image The following example show the resizing setting Page 99 of Version: 43

100 X GRAM Address (X, Y) dx dx= (X-H)/N, H=X mod N dy= (Y-V)/N, V=Y mod N Y Original Image Size dy (X+dx-, Y+dy-) Original image data number in horizontal direction X Original image data number in Vertical direction Y Resizing Ration /N Resizing Setting RSZ N- Remainder pixels in horizontal direction RCH H Remainder pixels in vertical direction RCV V GRAM writing start address A (x, y) HSA x GRAM window setting HEA x+dx- VSA y VEA y+dy- Page of Version: 43

101 Electrical Characteristics Absolute Maximum Ratings The absolute maximum rating is listed on following table When is used out of the absolute maximum ratings, the may be permanently damaged To use the within the following electrical characteristics limit is strongly recommended for normal operation If these electrical characteristic conditions are exceeded during normal operation, the will malfunction and cause poor reliability Item Symbol Unit Value Note Power supply voltage () IOVCC V -3 ~ + 46, 2 Power supply voltage () VCI - GN V -3 ~ + 46, 4 Power supply voltage () VH - GN V -3 ~ + 6, 4 Power supply voltage () GN -VCL V -3 ~ + 46 Power supply voltage () VH - VCL V -3 ~ + 9, 5 Power supply voltage () VGH - GN V -3 ~ + 85, 5 Power supply voltage () GN - VGL V -3 ~ + 85, 6 Input voltage Vt V -3 ~ VCC+ 3 Operating temperature Topr C -4 ~ , 9 Storage temperature Tstg C -55 ~ + 8, 9 Notes: GN must be maintained 2 (High) (VCC = VCC) GN (Low), (High) IOVCC GN (Low) 3 Make sure (High) VCI GN (Low) 4 Make sure (High) VH GN (Low) 5 Make sure (High) VH VCL (Low) 6 Make sure (High) VGH GN (Low) 7 Make sure (High) GN VGL (Low) 8 For die and wafer products, specified up to 85 C 9 This temperature specifications apply to the TCP package Page of Version: 43

102 2 C Characteristics (VCC = VCI=24 ~ 3V, IOVCC = 5 ~ 33V, Ta= -4 ~ 85 C) Item Symbol Unit Test Condition Min Typ Max Note Input high voltage V IH V IOVCC= 8 ~ 33V 8*IOV CC - IOVCC - Input low voltage V IL V IOVCC= 8 ~ 33V -3-2*IOVCC - Output high voltage() ( - Pins) Output low voltage ( - Pins) V OH V IOH = - ma 8*IOV CC V OL V IOVCC=5~33V - - 2*IOVCC - I/O leakage current I LI µa Vin = ~ VCC Current consumption during normal operation (V CC GN ) Current consumption during standby mode (V CC GN ) LC rive Power Supply Current ( VH-GN ) LC riving Voltage ( VH-GN ) I OP µa VCC=28V, Ta=25 C, fosc = 5KHz ( Line) GRAM data = h - (VCC) - - I ST µa VCI=28V, Ta=25 C ILC ma VCI=28V, VREGOUT =48V VH=52V, Frame Rate: 7Hz, line-inversion, Ta=25 C, GRAM data = h, VH V Output deviation voltage V EV mv Output offset voltage V OFFSET mv Note Note: The Max value is between with measure point and Gamma setting value 3 Reset Timing Characteristics Reset Timing Characteristics (IOVCC = 5 ~ 33 V) Item Symbol Unit Min Typ Max Reset low-level width t RES_L ms - - Reset rise time t rres µs - - Reset high-level width t RES_H ms AC Characteristics 4 i8-system Interface Timing Characteristics Normal Write Mode (IOVCC = 5~33V) Item Symbol Unit Min Typ Max Test Condition Bus cycle time Write t CYCW ns Page of Version: 43

103 Read t CYCR ns Write low-level pulse width PW LW ns Write high-level pulse width PW HW ns Read low-level pulse width PW LR ns Read high-level pulse width PW HR ns - - Write / Read rise / fall time t WRr /t WRf ns Setup time Write ( RS to ncs, E/nWR ) - - t AS ns Read ( RS to ncs, RW/n ) Address hold time t AH ns Write data set up time t SW ns - - Write data hold time t H ns - - Read data delay time t R ns - - Read data hold time t HR ns RS V IH V IL V IH V IL t AS t AH ncs PW LW, PW LR PW HW, PW HR nwr, n V IH V IL V IL V IH V IH t WRf t WRr t CYCW, t CYCR t SW t H Write ata [:] V IH V IL Va lid a ta V IH V IL t R t HR Read ata [:] V OH V OL Va lid a ta V OH V OL Figure 5 i8-system Bus Timing 42 Serial ata Transfer Interface Timing Characteristics (IOVCC= 5 ~ 33V) Serial clock cycle time Item Symbol Unit Min Typ Max Test Condition Write ( received ) t SCYC ns - - Read ( transmitted ) t SCYC ns Serial clock high level Write ( received ) t SCH ns pulse width Read ( transmitted ) t SCH ns - - Serial clock low level Write ( received ) t SCL ns pulse width Read ( transmitted ) t SCL ns - - Serial clock rise / fall time t SCr, t SCf ns Page of Version: 43

104 Item Symbol Unit Min Typ Max Test Condition Chip select set up time t CSU ns - - Chip select hold time t CH ns Serial input data set up time t SISU ns Serial input data hold time t SIH ns Serial output data set up time t SO ns - - Serial output data hold time t SOH ns ncs V IL V IH t CSU t SCYC t SCH t SCr t SCf t SCL t CH SCL V IH V IL V IH V IL V IH V IL V IH V IL t SISU t SIH SI V IH V IL Input ata V IH V IL Input ata t SO SO V OH V OH V OL V OL Output ata Output ata V OH V OL Figure 5 SPI System Bus Timing 43 RGB Interface Timing Characteristics 8/-bit Bus RGB Interface Mode (IOVCC = 5 ~ 33V) Item Symbol Unit Min Typ Max Test Condition VSYNC/HSYNC setup time t SYNCS ns ENABLE setup time t ENS ns ENABLE hold time t ENH ns P ata setup time t PS ns P ata hold time t PH ns OTCLK high-level pulse width PH ns OTCLK low-level pulse width PL ns OTCLK cycle time t CYC ns OTCLK, VSYNC, HSYNC, rise/fall time t rghr, t rghf ns bit Bus RGB Interface Mode (IOVCC = 5 ~ 33V) Item Symbol Unit Min Typ Max Test Condition VSYNC/HSYNC setup time t SYNCS ns ENABLE setup time t ENS ns ENABLE hold time t ENH ns P ata setup time t PS ns P ata hold time t PH ns OTCLK high-level pulse width PH ns OTCLK low-level pulse width PL ns OTCLK cycle time t CYC ns Page 4 of Version: 43

105 OTCLK, VSYNC, HSYNC, rise/fall time t rghr, t rghf ns t rgbf t rgbr t SYNCS V IH V IL tase t ENS t ENH V IH V IL V IH V IL t t rgbr rgbf PL PH V IH V IL V IL V IH V IH t CYC t PS t PH V IH V IL Write ata V IH V IL Figure52 RGB Interface Timing Page of Version: 43

106 4 Revision History a-si TFT LC Single Chip river Version No ate Page escription V28 27/7/5 96 Modify the FPC circuit V29 27/7/ Modify the alignment mark pattern V3 27/9/7 55 Modify the frame rate setting of R2Bh register V3 27//29 57 Add the high speed write function V32 27// Modify Frame rate value by register setting V33 27//8 Modify Output Voltage deviation item V34 27//27 96 Modify the pin recommend resistance V35 27//3 96 Remove the TEST and TEST2 output to FPC V36 28// 98 5, Modify isplay OFF register setting Remove the deep standby mode function (STB) 2 Modify the NL[5:] setting of R6h 3 Modify the source output deviation and offset 4 Modify the diode connection description (VCL VGL), (VH VGH), (Vci VH) V37 28// 99 Modify the VH VREGOUT > 3Volt V38 28// Modify the VH VREGOUT > 2Volt 2 Remove the register Rh V39 28// Add Reg 97h Modify Fig45 STB mode register setting sequence Modify the Fig 53 power supply ON/OFF sequence Modify the reset timing characteristics V4 28//24 53 Modify the register Rh V4 28/2/5 67 Modify the register Rh statement VH VREGOUT > 2Volt V42 28/3/ 22 elete Bit Operation function V43 28/9/ 36,39,4, 44,45,5, 54,55 Remove R3h HWM bit and its statement Page of Version: 43

107 Page of Version: 43