ILI9320. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K color. Datasheet Preliminary

Transcription

1 a-si TFT LC Single Chip river atasheet Preliminary Version: V55 ocument No: S_V55pdf ILI TECHNOLOGY CORP 4F, No, Tech 5 th Rd, Hsinchu Science Park, Taiwan 3, ROC Tel ; Fax

2 Table of Contents Section Page Introduction 7 Features 7 3 Block iagram 9 4 Pin escriptions 5 Pad Arrangement and Coordination 6 Block escription 3 7 System Interface 6 7 Interface Specifications 6 7 Input Interfaces 7 7 i8/8-bit System Interface 8 7 i8/-bit System Interface 9 73 i8/9-bit System Interface 3 74 i8/8-bit System Interface 3 73 Serial Peripheral Interface (SPI) 3 74 VSYNC Interface RGB Input Interface RGB Interface 4 75 RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface45 76 Interface Timing 48 8 Register escriptions 49 8 Registers Access 49 8 Instruction escriptions 5 8 Index (IR) 54 8 Status Read (RS) Start Oscillation (Rh)54 84 river Output Control (Rh) LC riving Wave Control (Rh) Entry Mode (R3h) Resizing Control Register (R4h) isplay Control (R7h) isplay Control (R8h) 6 8 isplay Control 3 (R9h) 6 8 isplay Control 4 (RAh) 6 Page of 9 Version: 54

3 8 RGB isplay Interface Control (RCh) 6 8 Frame Marker Position (h) 63 8 RGB isplay Interface Control (RFh) 64 8 Power Control (Rh) 64 8 Power Control (Rh) 66 8 Power Control 3 (Rh) Power Control 4 (Rh) GRAM Horizontal/Vertical Address Set (Rh, Rh) 67 8 Write ata to GRAM (Rh) 68 8 Read ata from GRAM (Rh) 68 8 Power Control 7 (R9h) 7 83 Frame Rate and Color Control (RBh) 7 84 Gamma Control (R3h ~ R3h) 7 85 Horizontal and Vertical RAM Address Position (R5h, R5h, R5h, R53h) 7 86 Gate Scan Control (R6h, R6h, R6Ah) Partial Image isplay Position (R8h) Partial Image RAM Start/End Address (R8h, R8h) Partial Image isplay Position (R83h) Partial Image RAM Start/End Address (R84h, R85h) Panel Interface Control (R9h) Panel Interface Control (R9h) Panel Interface Control 3 (R93h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) Panel Interface Control 6 (R98h) 78 9 GRAM Address Map & Read/Write 8 Window Address Function 86 Gamma Correction 88 Application 93 Configuration of Power Supply Circuit 93 isplay ON/OFF Sequence 95 3 eep Standby and Sleep Mode 96 4 Power Supply Configuration 97 5 Voltage Generation 98 6 Applied Voltage to the TFT panel 99 7 Oscillator 99 8 Frame Rate Adjustment 9 Partial isplay Function Resizing Function Page 3 of 9 Version: 54

4 Electrical Characteristics Absolute Maximum Ratings C Characteristics 3 Clock Characteristics 4 Reset Timing Characteristics 5 LC river Output Characteristics 錯 誤! 尚 未 定 義 書 籤 6 AC Characteristics 6 i8-system Interface Timing Characteristics 6 Serial ata Transfer Interface Timing Characteristics 63 RGB Interface Timing Characteristics Revision History 9 Page 4 of 9 Version: 54

5 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 7 FIGURE 8-BIT SYSTEM INTERFACE ATA FORMAT 8 FIGURE3 -BIT SYSTEM INTERFACE ATA FORMAT 9 FIGURE4 9-BIT SYSTEM INTERFACE ATA FORMAT 3 FIGURE5 8-BIT SYSTEM INTERFACE ATA FORMAT 3 FIGURE6 ATA TRANSFER SYNCHRONIZATION IN 8/9-BIT SYSTEM INTERFACE 3 FIGURE 7 ATA FORMAT OF SPI INTERFACE 33 FIGURE8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 34 FIGURE9 ATA TRANSMISSION THROUGH VSYNC INTERFACE) 35 FIGURE MOVING PICTURE ATA TRANSMISSION THROUGH VSYNC INTERFACE 35 FIGURE OPERATION THROUGH VSYNC INTERFACE 36 FIGURE TRANSITION FLOW BETWEEN VSYNC AN INTERNAL CLOCK OPERATION MOES 38 FIGURE RGB INTERFACE ATA FORMAT 39 FIGURE GRAM ACCESS AREA BY RGB INTERFACE 4 FIGURE TIMING CHART OF SIGNALS IN 8-/-BIT RGB INTERFACE MOE 4 FIGURE TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 4 FIGURE EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 43 FIGURE8 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 46 FIGURE9 GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 47 FIGURE RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 48 FIGURE REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 49 FIGURE REGISTER SETTING WITH I8 SYSTEM INTERFACE 5 FIGURE 3 REGISTER REA/WRITE TIMING OF I8 SYSTEM INTERFACE 5 FIGURE4 GRAM ACCESS IRECTION SETTING 56 FIGURE5 -BIT MPU SYSTEM INTERFACE ATA FORMAT 57 FIGURE6 8-BIT MPU SYSTEM INTERFACE ATA FORMAT 58 FIGURE 7 ATA REA FROM GRAM THROUGH REA ATA REGISTER IN 8-/-/9-/8-BIT INTERFACE MOE 69 FIGURE 8 GRAM ATA REA BACK FLOW CHART 7 FIGURE 9 GRAM ACCESS RANGE CONFIGURATION 7 FIGURE3 GRAM REA/WRITE TIMING OF I8-SYSTEM INTERFACE 8 FIGURE3 I8-SYSTEM INTERFACE WITH 8-/-/9-BIT ATA BUS (SS=, BGR= ) 8 FIGURE3 I8-SYSTEM INTERFACE WITH 8-BIT ATA BUS (SS=, BGR= ) 83 FIGURE 33 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) 85 FIGURE 34 GRAM ACCESS WINOW MAP 86 FIGURE 35 GRAYSCALE VOLTAGE GENERATION 88 FIGURE 36 GRAYSCALE VOLTAGE AJUSTMENT 89 FIGURE 37 GAMMA CURVE AJUSTMENT 9 FIGURE 38 RELATIONSHIP BETWEEN SOURCE OUTPUT AN VCOM 9 Page 5 of 9 Version: 54

6 FIGURE 39 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL 9 FIGURE 4 POWER SUPPLY CIRCUIT BLOCK 95 FIGURE 4 ISPLAY ON/OFF REGISTER SETTING SEQUENCE 96 FIGURE 4 EEP STANY/SLEEP MOE REGISTER SETTING SEQUENCE 96 FIGURE 43 POWER SUPPLY ON/OFF SEQUENCE 97 FIGURE 44 VOLTAGE CONFIGURATION IAGRAM 98 FIGURE 45 VOLTAGE OUTPUT TO TFT LC PANEL 99 FIGURE 46 OSCILLATION CONNECTION 99 FIGURE 47 PARTIAL ISPLAY EXAMPLE FIGURE 48 ATA TRANSFER IN RESIZING FIGURE 49 RESIZING EXAMPLE FIGURE 5 I8-SYSTEM BUS TIMING FIGURE 5 SPI SYSTEM BUS TIMING FIGURE5 RGB INTERFACE TIMING8 Page 6 of 9 Version: 54

7 Introduction a-si TFT LC Single Chip river is a 6,4-color one-chip SoC driver for a-tft liquid crystal display with resolution of 4RGBx3 dots, comprising a 7-channel source driver, a 3-channel gate driver,,8 bytes RAM for graphic data of 4RGBx3 dots, and power supply circuit has four kinds of system interfaces which are i8-system MPU interface (8-/9-/-/8-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [:]), serial data transfer interface (SPI) and RGB 6-/-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [:]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 5V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LC driver for medium or small size portable products such as digital cellular phones, smart phone, PA and PMP where long battery life is a major concern Features Single chip solution for a liquid crystal QVGA TFT LC display 4RGBx3-dot resolution capable with real 6,4 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 7-channel source driver and 3-channel gate driver Internal,8 bytes graphic RAM High-speed RAM burst write function System interfaces i8 system interface with 8-/ 9-/-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [:]) VSYNC interface (System interface + VSYNC) n-line liquid crystal AC drive: invert polarity at an interval of arbitrarily n lines (n: ~ 64) Internal oscillator and hardware reset Resizing function ( /, /4) Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Page 7 of 9 Version: 54

8 Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 6,4 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 5V ~ 33 V (interface I/O) Vcc = 4V ~ 33 V (internal logic) Vci = 5V ~ 33 V (analog) LC Voltage drive: Source/VCOM power supply voltage VH - GN = 45V ~ 6V VCL GN = -V ~ -3V VCI VCL 6V Gate driver output voltage VGH - GN = V ~ V VGL GN = -5V ~ -V VGH VGL 3V VCOM driver output voltage VCOMH = 3V ~ (VH-5)V VCOML = (VCL+5)V ~ V VCOMH-VCOML 6V a-tft LC storage capacitor: Cst only Page 8 of 9 Version: 54

9 3 Block iagram IOVCC IM[3:] nreset ncs nwr/scl n RS SI SO [:] HSYNC VSYNC OTCLK ENABLE TEST TEST TS[7:] MPU I/F 8-bit -bit 9-bit 8-bit SPI I/F RGB I/F 8-bit -bit 6-bit VSYNC I/F Index Register (IR) 7 Control Register (CR) Graphics Operation Read Latch 7 8 Write Latch 7 Address Counter (AC) V63 ~ LC Source river Grayscale Reference Voltage S[7:] VREGOUT VGS VCC V GN Regulator Graphics RAM (GRAM) OSC OSC RC-OSC Timing Controller LC Gate river G[3:] VCI VCI VCILVL AGN Charge-pump Power Circuit VCOM Generator VCOM VLOUT C+ VH C+ C+ VCL VLOUT VLOUT3 C+ C3- C- C- C+ C3+ C- C- C- VGH VGL VCOMR VCOMH VCOML Page 9 of 9 Version: 54

10 4 Pin escriptions a-si TFT LC Single Chip river Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3, IM, IM, IM/I ncs RS nwr/scl n nreset SI SO [:] I I I I I I I O I/O IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc IM3 IM IM IM MPU-Interface Mode Pin in use Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO * Setting invalid Setting invalid Setting invalid i8-system 8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid When the serial peripheral interface is selected, IM pin is used for the device code I setting A chip select signal Low: the is selected and accessible High: the is not selected and not accessible Fix to the GN level when not in use A register select signal Low: select an index or status register High: select a control register Fix to GN level when not in use A write strobe signal and enables an operation to write data when the signal is low Fix to IOVCC level when not in use SPI Mode: Synchronizing clock signal in SPI mode A read strobe signal and enables an operation to read out data when the signal is low Fix to IOVCC level when not in use A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SPI interface input pin The data is latched on the rising edge of the SCL signal Fix to GN level when not in use SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SO as open when not in use An 8-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: [:] is used 9-bit I/F: [:9] is used -bit I/F: [:] and [8:] is used 8-bit I/F: [:] is used 8-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: [:] are used Page of 9 Version: 54

11 Pin Name I/O Type escriptions -bit RGB I/F: [:] and [:] are used 8-bit RGB I/F: [:] are used ENABLE I MPU IOVcc Unused pins must be fixed GN level ata ENEABLE signal for RGB interface operation Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal OTCLK VSYNC HSYNC FMARK OSC OSC I I I O I O MPU IOVcc MPU IOVcc MPU IOVcc MPU IOVcc Oscillation resistor S7~S O LC G3~G O LC VCOM VCOMH VCOML VCOMR VGS O O O I I TFT common electrode Stabilizing capacitor Stabilizing capacitor Variable resistor or open AGN or external resistor Fix to GN level when not in use ot clock signal for RGB interface operation PL = : Input data on the rising edge of OTCLK PL = : Input data on the falling edge of OTCLK Fix to GN level when not in use Frame synchronizing signal for RGB interface operation VSPL = : Active low VSPL = : Active high Fix to GN level when not in use Line synchronizing signal for RGB interface operation HSPL = : Active low HSPL = : Active high Fix to GN level when not in use Output a frame head pulse signal The FMARK signal is used when writing RAM data in synchronization with frame Leave the pin open when not in use Connect an external resistor for generating internal clock by internal R-C oscillation, or an external clock signal is supplied through OSC LC riving signals Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S SS =, the data in the RAM address h is output from S7 S, S4, S7, display red (R), S, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels The high level of VCOM AC voltage Connect to a stabilizing capacitor The low level of VCOM AC voltage Adjust the VCOML level with the VV bits Connect to a stabilizing capacitor A reference level to generate the VCOMH level either with an externally connected variable resistor or by setting the register of the When using a variable resistor, halt the internal VCOMH adjusting circuit by setting the register and place the resister between VREGOUT and AGN When generating the VCOMH level by setting the register, leave this pin open Reference level for the grayscale voltage generating circuit The VGS level can be changed by connecting to an external resistor Charge-pump and Regulator Circuit Page of 9 Version: 54

12 Pin Name I/O Type escriptions Vci I Power A supply voltage to the analog circuit Connect to an external power supply supply of 5 ~ 33V AGN I Power AGN for the analog side: AGN = V In case of COG, connect to supply GN on the FPC to prevent noise VciLVL I VciLVL must be at the same voltage level as Vci noise Power VciLVL=5V ~ 33V Connect to the external power supply supply In COG case, connect the VciLVL with Vci on the FPC to prevent VciOUT Vci VLOUT O I O Stabilizing capacitor Vci Stabilizing capacitor Vci Stabilizing capacitor, VH VH O VLOUT VLOUT O Stabilizing capacitor, VGH An internal reference voltage generated between Vci and AGN The amplitude between Vci and GN is determined by the VC[:] bits An internal reference voltage for the step-up circuit The amplitude between Vci and GN is determined by the VC[:] bits Make sure to set the Vci voltage so that the VLOUT, VLOUT and VLOUT3 voltages are set within the respective specification Output voltage from the step-up circuit, which is generated from Vci The step-up factor is set by BT bits VLOUT= 45 ~ 6V Place a stabilizing capacitor between AGN Power supply for the source driver and Vcom drive Connect to VLOUT and VH = 45 ~ 6V Output voltage from the step-up circuit, which is generated from Vci and VH The step-up factor is set by BT bits VLOUT= maxv VGH I VLOUT Power supply for the gate driver, connect to VLOUT VLOUT3 O Stabilizing capacitor, VGL Output voltage from the step-up circuit, which is generated from Vci and VH The step-up factor is set by BT bits VLOUT3= max -5V Place a stabilizing capacitor and shottkey diode between AGN VGL I VLOUT3 Power supply for the gate driver, connect to VLOUT3 VCL O Stabilizing capacitor, VCL VcomL driver power supply VCLC = ~ 33V Place a stabilizing capacitor between AGN C+, C- Step-up I/O C+, C- capacitor Capacitor connection pins for the step-up circuit C+, C- C+, C- Step-up I/O C+, C- capacitor Capacitor connection pins for the step-up circuit C3+, C3- Output voltage generated from the reference voltage VREGOUT Vcc IOVcc I/O I I Stabilizing capacitor or power supply Power supply Power supply V O Power igital core power pad The voltage level is set with the VRH bits VREGOUT is () a source driver grayscale reference voltage, () VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREGOUT = 3 ~ (VH 5)V Power Pads A supply voltage to the internal logic: Vcc = 4~33V A supply voltage to the interface pins: IM[3:], nreset, ncs, nwr, n, RS, [:], VSYNC, HSYNC, OTCLK, ENABLE, SCL, SI, SO IOVcc = 5 ~ 33V and Vcc IOVcc In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise Page of 9 Version: 54

13 Pin Name I/O Type escriptions Connect them with the uf capacitor GN I Power supply GN for the logic side: GN = V IOGN I IOGN for the interface pins Power IOGN = V In case of COG, connect to GN on the FPC to supply prevent noise Test Pads VT, V3T - Open ummy pads Connect to IOVcc, GN or leave these pins as open VTEST - Open ummy pad Connect to IOVcc, GN or leave this pin as open VREFC - Open ummy pad Connect to IOVcc, GN or leave this pin as open VREF - Open ummy pad Connect to IOVcc, GN or leave this pin as open VTEST - Open ummy pad Connect to IOVcc, GN or leave this pin as open VREF - Open ummy pad Connect to IOVcc, GN or leave this pin as open VMON - Open ummy pad Connect to IOVcc, GN or leave this pin as open TESTA5 - Open ummy pad Connect to IOVcc, GN or leave this pin as open IOVCCUM~ O Power Output the IOVcc voltage level These pins are internally shorted to IOVCC VCCUM - Power ummy pin Connect to VCC or leave this pin as open IOGNUM~3 O Power Output the GN voltage level These pins are internally shorted to GN When adjacent pins are needed to pull low, tie these pins to IOGNUM~3 OSCUM~4 - Open ummy pads Connect to GN or leave these pins as open OSCUM~ - Open ummy pads Connect to GN or leave these pins as open AGNUM - Power ummy pad Leave this pin as open AGNUM~4 O Power Output the GN voltage level These pins are internally shorted to GN UMMYR~ - - ummy pads Leave these pins as open VGLMY~4 O Open ummy pads Connect to IOVcc, GN or leave these pins as open TESTO~38 O Open Test pins Leave them open TEST,, 5 I IOGN Test pins (internal pull low) Connect to GN TEST3 I Open ummy pin Connect to IOVcc or leave these pins as open TEST4 I Open ummy pin Connect to IOVcc or leave these pins as open TSC I Open ummy pin Connect to GN or leave these pins as open TS~8 I Open Test pins (internal pull low) Leave them open VPP - Open Test pins Must let these pads as open VPP - Open Test pins Must let these pads as open VPP3 - - Test pins Must let these pads as open or connect to GN Liquid crystal power supply specifications Table No Item escription TFT Source river 7 pins (4 x RGB) TFT Gate river 3 pins 3 TFT isplay s Capacitor Structure Cst structure only (Common VCOM) 4 Liquid Crystal rive Output 5 Input Voltage S ~ S7 V ~ V63 grayscales G ~ G3 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes VCOMH=VCOMR: Adjusted with an external resistor IOVcc 5 ~ 33V Vcc 4 ~ 33V Vci 5 ~ 33V Page of 9 Version: 54

14 6 Liquid Crystal rive Voltages 7 Internal Step-up Circuits VH 45V ~ 6V VGH V ~ V VGL -5V ~ -V VCL -9V ~ -3V VGH - VGL Max 3V Vci - VCL Max 6V VLOUT (VH) Vci x, x3 VLOUT (VGH) Vci x6, x7, x8 VLOUT3 (VGL) Vci x-3, x-4, x-5 VCL Vci x- Page of 9 Version: 54

15 5 Pad Arrangement and Coordination Page of 9 Version: 54

16 a-si TFT LC Single Chip river Chip Size: um x 67um (including scribe line) Chip thickness : 4um (typ) or 5um (customer order) Pad Location: Pad Center Coordinate Origin: Chip center UMMYR UMMYR TESTO VCCUM VPP VPP VPP VPP VPP VPP VPP VPP VPP3 VPP3 VPP3 TESTO IOGNUM TESTO3 TEST TEST TEST4 TEST5 TEST3 IM/I IM IM IM3 TESTO4 IOVCCUM TESTO5 (-a) TESTO38 TESTO37 UMMYR UMMYR9 VGLMY4 G G4 G6 G8 G Au bump height: um (typ) Au Bump Size: um x um (No 99 ~ 54) Gate: G ~ G3 Source: S ~ S7 5um x 8um (No ~ 98) Input Pads Pad to 98 nreset VSYNC HSYNC OTCLK ENABLE 9 8 TESTO6 IOGNUM TESTO SO SI n nwr/scl RS ncs TESTO8 IOVCCUM TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS TS TS TSC TESTO IOGNUM3 TESTO TESTO 6um G3 G3 G3 G38 G3 VGLMY3 TESTO36 TESTO35 S S S3 S4 S5 S6 S7 S8 S9 Alignment Marks Alignment Mark: -a, -b um Bump View Face Up (Bump View) TESTO3 (-b) Page of 9 Version: 54 OSCUM OSCUM OSC OSCUM3 OSCUM4 OSC OSCUM OSCUM UMMYR3 UMMYR4 IOGN IOGN IOGN IOGN IOGN IOGN IOGN IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC V V V V V V V V V V V V V TESTO VREF TESTO VREF TESTO VREFC TESTO VTEST AGN AGN AGN AGN AGN AGN AGN AGN AGN AGN AGN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN TESTO VTEST TESTO8 VGS TESTO9 VT TESTO VMON TESTO V3T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO TESTO3 VREGOUT TESTO4 TESTA5 TESTO5 VCOMR TESTO6 VCL VCL VCL VLOUT VLOUT VLOUT VH VH VH VH VH VH VH VCIOUT VCIOUT VCIOUT VCI VCI VCI VCI VCI VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C- C- C- C- C- C+ C+ C+ C+ C+ C- C- C- C- C- C+ C+ C+ C+ C+ AGNUM VLOUT3 VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNUM AGNUM3 AGNUM4 VLOUT VLOUT VGH VGH VGH VGH TESTO7 C- C- C- TESTO8 C+ C+ C+ TESTO9 C- C- C- C+ C+ C+ C- C- C- C+ C+ C+ C3- C3- C3- C3+ C3+ C3+ TESTO3 UMMYR5 UMMYR6 X Y um S7 S7 S7 S7 S7 S7 S78 S79 S7 TESTO34 TESTO33 VGLMY G39 G3 G3 G3 G3 G9 G7 G5 G3 G VGLMY UMMYR8 UMMYR7 TESTO3

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y UMMYR RS V VCOMH C UMMYR CS* V VCOMH C TESTO TESTO V VCOML C VCCUM IOVCCUM V VCOML C VPP TESTO V VCOML C VPP FMARK TESTO VCOML C VPP TS VREF VCOML AGNUM VPP TS TESTO VCOML VLOUT VPP TS VREF TESTO VLOUT VPP TS TESTO TESTO VGL VPP TS VREFC VREGOUT VGL 7-55 VPP TS TESTO TESTO VGL VPP TS VTEST TESTA VGL VPP TS AGN TESTO VGL VPP TS AGN VCOMR VGL TESTO TSC AGN TESTO VGL IOGNUM TESTO AGN VCL VGL TESTO IOGNUM AGN VCL VGL TEST TESTO AGN VCL VGL TEST TESTO AGN VLOUT AGNUM TEST OSCUM AGN VLOUT AGNUM TEST OSCUM AGN VLOUT AGNUM TEST OSC AGN VH VLOUT IM/I OSCUM AGN VH VLOUT IM OSCUM GN VH VGH IM OSC GN VH VGH IM OSCUM GN VH VGH TESTO OSCUM GN VH VGH IOVCCUM UMMYR GN VH TESTO TESTO UMMYR GN VCIOUT C RESET* IOGN GN -55 VCIOUT C VSYNC IOGN GN 5-55 VCIOUT C HSYNC IOGN GN VCI TESTO OTCLK IOGN GN 3-55 VCI C ENABLE IOGN GN VCI C IOGN GN VCI C IOGN GN VCI TESTO IOVCC GN VCILVL C IOVCC GN VCI C IOVCC GN VCI C IOVCC TESTO VCI C IOVCC VTEST VCI C IOVCC TESTO VCI C IOVCC VGS VCI C VCC TESTO VCI C TESTO VCC VT VCI C IOGNUM VCC TESTO C C TESTO VCC VMON C C VCC TESTO C C VCC V3T C C VCC VCOM C C VCC VCOM C C V VCOM C C V VCOM C C V VCOM C C V VCOM C TESTO SO V VCOMH C UMMYR SI V VCOMH C UMMYR * V VCOMH C TESTO WR*/SCL V VCOMH C TESTO Page of 9 Version: 54

18 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 3 UMMYR G G S S UMMYR G G S S VGLMY G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G G S S G G VGLMY S S G G TESTO S S G G TESTO S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S Page 8 of 9 Version: 54

19 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 6 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 9 of 9 Version: 54

20 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 9 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S7-3 5 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S TESTO S S S S TESTO S S S S VGLMY S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G Page of 9 Version: 54

21 No Name X Y No Name X Y No Name X Y G G G G G G G G G G G G5-5 5 G G G G G G G G G G G G G G G G G G4-9 5 G G G G G G G G G G G G3-7 5 G G G G G G8-5 G G G G G G G G G G G G -9 5 G G G G G G G G G G G G G G G G G G8-5 7 G G G G G G G G G G G VGLMY G G UMMYR G G UMMYR G G TESTO G G TESTO G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Alignment mark X Y 59 G G a G G b -468 Page of 9 Version: 54

22 S ~ S7 G ~ G3 UMMY UMMYR TESTO VGLMY (No 99 ~ 54) 5 Unit: um 5 5 I/O Pads (No ~ 98) Pad Pump Pad Pump 8 7 Page of 9 Version: 54

23 6 Block escription MPU System Interface supports three system high-speed interfaces: i8-system high-speed interfaces to 8-, 9-, -, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a -bit index register (IR), an 8-bit write-data register (R), and an 8-bit read-data register (R) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The R is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the R from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time except starting oscillator takes clock cycle Registers selection by system interface (8-/9-/-/8-bit bus width) I8 Function RS nwr n Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Registers selection by the SPI system interface Function R/W RS Write an index to IR register Read an internal status Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is Page 3 of 9 Version: 54

24 selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Bit Operation The supports a write data mask function for selectively writing data to the internal RAM in units of bits and a logical/compare operation to write data to the GRAM only when a condition is met as a result of comparing the data and the compare register bits For details, see Graphics Operation Functions Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of,8 (4 x 3x 8/8) bytes with 8 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 6,4 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) implements internal/external resistor to generate the oscillation frequency and internal resistor will be used in the default setting User can adjust the frame rate by the Rbh and R9h registers when internal resistor is used or adjust the frame rate by the external resistor which is placed between the OSC and OSC pins LC river Circuit The LC driver circuit of consists of a 7-output source driver (S ~ S7) and a 3-output gate driver (G~G3) isplay pattern data are latched when the 7 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH Page 4 of 9 Version: 54

25 or VGL level The shift direction of 7 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREGOUT, VGH, VGL and Vcom for driving an LC Page 5 of 9 Version: 54

26 7 System Interface 7 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [:] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface () (Rewriting still pictures while displaying moving pictures) VSYNC interface (isplaying moving pictures) RAM Access Setting (RM) System interface (RM = ) RGB interface (RM = ) System interface (RM = ) System interface (RM = ) isplay Operation Mode (M[:]) Internal operating clock (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) VSYNC interface (M[:] = ) Note ) Registers are set only via the system interface Note ) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 6 of 9 Version: 54

27 System System Interface 8//6 ncs RS nwr n [:] RGB Interface ENABLE VSYNC HSYNC OTCLK Figure System Interface and RGB Interface connection 7 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting registers and GRAM access IM3 IM IM IM/I Interface Mode Pin Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO * Setting invalid Setting invalid Setting invalid i8-system8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid Page 7 of 9 Version: 54

28 7 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as levels System ncs A nwr n [3:] 8 ncs RS nwr n [:] 8-bit System Interface (6K colors) TRI=, FM[:]= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 8-bit System Interface ata Format Page 8 of 9 Version: 54

29 7 i8/-bit System Interface The i8/-bit system interface is selected by setting the IM[3:] as levels The 6K or 65K color can be display through the -bit MPU interface When the 6K color is displayed, two transfers ( st transfer: bits, nd transfer: bits or st transfer: bits, nd transfer: bits) are necessary for the -bit CPU interface TRI FM -bit MPU System Interface ata Format system -bit interface ( transfers/pixel) 65,536 colors * st Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,4 colors st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,4 colors st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure3 -bit System Interface ata Format Page 9 of 9 Version: 54

30 73 i8/9-bit System Interface The i8/9-bit system interface is selected by setting the IM[3:] as and the ~9 pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:] pins must be tied to AGN System ncs A nwr n [8:] 9 ncs RS nwr n [:9] 9-bit System Interface (6K colors) TRI=, FM[:]= Input ata st Transfer (Upper bits) 9 nd Transfer (Lower bits) 9 Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure4 9-bit System Interface ata Format 74 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as and the ~ pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:] pins must be tied to AGN Page 3 of 9 Version: 54

31 TRI FM 8-bit MPU System Interface ata Format system 8-bit interface ( transfers/pixel) 65,536 colors * st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system 8-bit interface (3 transfers/pixel) 6,4 colors st Transfer nd Transfer 3rd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system 8-bit interface (3 transfers/pixel) 6,4 colors st Transfer nd Transfer 3rd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure5 8-bit System Interface ata Format ata transfer synchronization in 8/9-bit bus interface mode supports a data transfer synchronization function to reset upper and lower counters which count the transfers numbers of upper and lower byte in 8/9-bit interface mode If a mismatch arises in the numbers of transfers between the upper and lower byte counters due to noise and so on, the h register is written 4 times consecutively to reset the upper and lower counters so that data transfer will restart with a transfer of upper byte This synchronization function can effectively prevent display error if the upper/lower counters are periodically reset RS nwr [:9] Upper/ Lower h h h h Upper Lower 8-/9-bit transfer synchronization Figure6 ata Transfer Synchronization in 8/9-bit System Interface 73 Serial Peripheral Interface (SPI) The Serial Peripheral Interface (SPI) is selected by setting the IM[3:] pins as x level The chip select pin Page 3 of 9 Version: 54

32 (ncs), the serial transfer clock pin (SCL), the serial data input pin (SI) and the serial data output pin (SO) are used in SPI mode The I pin sets the least significant bit of the identification code The [:] pins, which are not used, must be tied to GN The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS =, either index write operation or status read operation is executed When RS =, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) ata is written when the R/W bit is and read back when the R/W bit is After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are -bit format and receive the first and the second byte datat as the upper and the lower eight bits of the -bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start evice I code RS R/W I / / Note: I bit is selected by setting the IM/I pin RS and R/W Bit Function RS R/W Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data Page 3 of 9 Version: 54

33 Serial Peripheral Interface for register access SPI Input ata Register ata IB IB IB IB IB IB IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB IB IB Serial Peripheral Interface 65K colors Input ata Write ata Register GRAM ata RGB mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 7 ata Format of SPI Interface Page 33 of 9 Version: 54

34 (a) Basic data transmission through SPI Start End ncs (Input) SCL (Input) SI (Input) I RS RW Start Byte Index register, registers setting, and GRAM write SO (Output) Status, registers read and GRAM read (b) GRAM data read transmission Start ncs (Input) End SCL (Input) SI (Input) Start Byte RS=, RW= SO (Output) ummy read ummy read ummy read 3 ummy read 4 ummy read 5 RAM read upper byte RAM read lower byte Note: Five bytes of invalid dummy data read after the start byte (c) Status/registers read transmission Start ncs (Input) End SCL (Input) SI (Input) Start Byte SO (Output) Register ummy read upper eight bits Note: One byte of invalid dummy data read after the start byte Register lower eight bits Figure8 ata transmission through serial peripheral interface (SPI) Page 34 of 9 Version: 54

35 74 VSYNC Interface supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i8 system interface When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting M[:] = and RM = VSYNC MPU ncs RS nwr [:] Figure9 ata transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal All display data are stored in GRAM to minimize total data transfer required for moving picture display VSYNC Write data to RAM through system interface isplay operation synchronized with internal clocks Rewriting screen data Rewriting screen data Figure Moving picture data transmission through VSYNC interface Page 35 of 9 Version: 54

36 VSYNC Back porch ( lines) RAM Write isplay operation isplay (3 lines) Front porch ( lines) Black period Figure Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula Internal clock frequency (fosc) [Hz] = FrameFrequency x (isplayline (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation Minimum RAM write speed (HZ) 3 x isplaylines (NL) [(BackPorch(BP)+isplayLines(NL) - margins] x (clocks) x /fosc Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below [Example] isplay size: 4 RGB 3 lines Lines: 3 lines (NL = ) Back porch: lines (BP = ) Front porch: lines (FP = ) Frame frequency: 6 Hz Frequency fluctuation: % Internal oscillator clock (fosc) [Hz] = 6 x [3+ + ] x clocks x (/9) 394KHz Page 36 of 9 Version: 54

37 When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration In the above example, the calculated internal clock frequency with ±% margin variation is considered and ensures to complete the display operation within one VSYNC cycle The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation Minimum speed for RAM writing [Hz] > 4 x 3 x 394K / [ ( + 3 )lines x clocks] 57 MHz The above theoretical value is calculated based on the premise that the starts to write data into the internal GRAM on the falling edge of VSYNC There must at least be a margin of lines between the physical display line and the GRAM line address where data writing operation is performed The GRAM write speed of 57MHz or more will guarantee the completion of GRAM write operation before the starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker Notes in using the VSYNC interface The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display 3 When switching from the internal clock operation mode (M[:] = ) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, ie after completing the display of the frame 4 The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to to transfer display data Page 37 of 9 Version: 54

38 System Interface Mode to VSYNC interface mode System Interface VSYNC interface mode to System Interface Mode Opeartion through VSYNC interface Set HWM=, AM= Set GRAM Address Set M[:]=, RM= for VSYNC interface mode Set index register to Rh isplay operation in synchronization with internal clocks M[:], RM become enable after completion of displaying frame Set M[:]=, RM= for system interface mode Wait more than frame System Interface isplay operation in synchronization with VSYNC M[:], RM become enable after completion of displaying frame isplay operation in synchronization with internal clocks Wait more than frame Write data to GRAM through VSYNC interface isplay operation in synchronization with VSYNC Note: input VSYNC for more than frame period after setting the M, RM register Opeartion through VSYNC interface Figure Transition flow between VSYNC and internal clock operation modes Page 38 of 9 Version: 54

39 75 RGB Input Interface The RGB Interface mode is available for and the interface is selected by setting the RIM[:] bits as following table RIM RIM RGB Interface pins 8-bit RGB Interface [:] -bit RGB Interface [:], [:] 6-bit RGB Interface [:] Setting prohibited 8-bit RGB Interface (6K colors) Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B -bit RGB Interface (65K colors) Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 6-bit RGB Interface (6K colors) Input ata st Transfer nd Transfer 3rd Transfer Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure RGB Interface ata Format Page 39 of 9 Version: 54

40 75 RGB Interface The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and OTCLK signals The RGB interface transfers the updated data to GRAM with the high-speed write function and the update area is defined by the window address function The back porch and front porch are used to set the RGB interface timing VSYNC Back porch period (BP[3:]) RAM data display area Moving picture display area isplay period (NL[4:] Front porch period (FP[3:]) HSYNC OTCLK ENABLE [:] Note : Front porch period continues until the next input of VSYNC Note : Input OTCLK throughout the operation Note 3: Supply the VSYNC, HSYNC and OTCLK with frequency that can meet the resolution requirement of panel Figure GRAM Access Area by RGB Interface Page 4 of 9 Version: 54

41 75 RGB Interface Timing The timing chart of 8-/-bit RGB interface mode is shown as follows frame Back porch Front porch VSYNC VLW >= H HSYNC OTCLK ENABLE [:] HSYNC HLW >= 3 OTCLK // H OTCLK // TST >= HLW ENABLE // [:] Valid data VLW: VSYNC low period HLW: HSYNC low period TST: data transfer startup time Note : Use the high speed write mode (HWM=) to write data through the RGB interface Figure Timing Chart of Signals in 8-/-bit RGB Interface Mode Page 4 of 9 Version: 54

42 The timing chart of 6-bit RGB interface mode is shown as follows frame Back porch Front porch VSYNC VLW >= H HSYNC OTCLK ENABLE [:] HSYNC HLW >= 3 OTCLK // H OTCLK // TST >= HLW ENABLE // [:] R G B R G B B R G B // Valid data VLW: VSYNC low period HLW: HSYNC low period TST: data transfer startup time Note : Use the high speed write mode (HWM=) to write data through the RGB interface Note ) In 6-bit RGB interface mode, each dot of one pixel (R, G and B) is transferred in synchronization with OTCLKs Note 3) In 6-bit RGB interface mode, set the cycles of VSYNC, HSYNC and ENABLE to 3 multiples of OTCLKs Figure Timing chart of signals in 6-bit RGB interface mode Page 4 of 9 Version: 54

43 753 Moving Picture Mode has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture The window address function defined the update area of GRAM Only the moving picture area of GRAM is updated When display the moving picture in RGB interface mode, the [:] can be switched as system interface to update still picture area and registers, such as icons RAM access via a system interface in RGB-I/F mode allows GRAM access via the system interface in RGB interface mode In RGB interface mode, data are written to the internal GRAM in synchronization with OTCLK and ENABLE signals When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = ) and the still picture of GRAM When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = and the index register to Rh to start accessing RAM via the RGB interface If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM The following figure illustrates the operation of the when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface Still Picture Area Moving Picture Area Update a frame Update a frame VSYNC ENABLE OTCLK [:] Set IR to Rh Update moving picture area Set RM= Set A[:] Set IR to Rh Update display data in other than the moving picture area Set A[:] Set RM= Set IR to Rh Update moving picture area Figure Example of update the still and moving picture Page 43 of 9 Version: 54

44 754 6-bit RGB Interface The 6-bit RGB interface is selected by setting the RIM[:] bits to The display operation is synchronized with VSYNC, HSYNC, and OTCLK signals isplay data are transferred to the internal GRAM in synchronization with the display operation via 6-bit RGB data bus ([:]) according to the data enable signal (ENABLE) Unused pins ([:]) must be fixed at either IOVcc or GN level Registers can be set by the system interface (i8/spi) RGB interface with 6-bit data bus st Transfer nd Transfer 3 rd Transfer Input ata RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B ata transfer synchronization in 6-bit RGB interface mode has data transfer counters to count the first, second, third data transfers in 6-bit RGB interface mode The transfer counter is always reset to the state of first data transfer on the falling edge of VSYNC If a mismatch arises in the number of each data transfer, the counter is reset to the state of first data transfer at the start of the frame (ie on the falling edge of VSYNC) to restart data transfer in the correct order from the next frame This function is expedient for moving picture display, which requires consecutive data transfer in light of minimizing effects from failed data transfer and enabling the system to return to a normal state Note that internal display operation is performed in units of pixels (RGB: taking 3 inputs of OTCLK) Accordingly, the number of OTCLK inputs in one frame period must be a multiple of 3 to complete data transfer correctly Otherwise it will affect the display of that frame as well as the next frame HSYNC ENABLE OTCLK [:] st nd 3 rd st nd 3 rd st nd 3 rd st nd 3 rd Transfer synchronization Page 44 of 9 Version: 54

45 755 -bit RGB Interface The -bit RGB interface is selected by setting the RIM[:] bits to The display operation is synchronized with VSYNC, HSYNC, and OTCLK signals isplay data are transferred to the internal RAM in synchronization with the display operation via -bit RGB data bus (-, -) according to the data enable signal (ENABLE) Registers are set only via the system interface -bit RGB Interface (65K colors) Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B bit RGB Interface The 8-bit RGB interface is selected by setting the RIM[:] bits to The display operation is synchronized with VSYNC, HSYNC, and OTCLK signals isplay data are transferred to the internal RAM in synchronization with the display operation via 8-bit RGB data bus ([:]) according to the data enable signal (ENABLE) Registers are set only via the system interface RGB interface with 8-bit data bus Input ata RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Notes in using the RGB Input Interface The following are the functions not available in RGB Input Interface mode Function RGB interface I8 system interface Partial display Not available Available Scroll function Not available Available Interlaced scan Not available Available Graphics operation function Not available Available VSYNC, HSYNC, and OTCLK signals must be supplied throughout a display operation period 3 The periods set with the NO[:] bits (gate output non-overlap period), ST[:] bits (source output delay period) and EQ[:] bits (equalization period) are not based on the internal clock but based on OTCLK in Page 45 of 9 Version: 54

46 RGB interface mode 4 In 6-bit RGB interface mode, each of RGB dots is transferred in synchronization with a OTCLK input In other words, it takes 3 OTCLK inputs to transfer one pixel Be sure to complete data transfer in units of 3 OTCLK inputs in 6-bit RGB interface mode 5 In 6-bit RGB interface mode, data of one pixel, which consists of RGB dots, are transferred in units of 3 OTCLK Accordingly, set the cycle of each signal in 6-bit interface mode (VSYNC, HSYNC, ENABLE, [:]) to contain OTCLK inputs of a multiple of 3 to complete data transfer in units of pixels 6 When switching from the internal operation mode to the RGB Input Interface mode, or the other way around, follow the sequence below 7 In RGB interface mode, the front porch period continues until the next VSYNC input is detected after drawing one frame 8 In RGB interface mode, a RAM address (A[:]) is set in the address counter every frame on the falling edge of VSYNC Internal clock operation to RGB I/F RGB I/F to Internal clock operation Internal clock operation HWM =, AM= Set A[:] Set RGB Interface mode M[:]= and RM= Set IR to Rh (GRAM data write) Note Internal clock operation * SPI interface can be used to set the registers and data * M[:] and RM become enable after completion of display frame RGB Interface Operation Set Internal Clock Operation mode M[:]= and RM= Wait for more than frame Internal clock operation RGB Interface (isplay operation in synchronization with VSYNC, HSYNC, OTCLK) * M[:] and RM become enable after completion of display frame isplay operation in synchronization with internal clock Wait for more than frame Write data through RGB I/F RGB Interface (isplay operation in synchronization with VSYNC, HSYNC, OTCLK) RGB Interface Operation Note: Input RGB Interface signals (VSYNC, HSYNC, OTCLK) before setting M[;] and RM to the RGB interface mode Figure8 Internal clock operation/rgb interface mode switching Page 46 of 9 Version: 54

47 Write data through RGB interface to write data through system interface RGB Interface operation Set M[:]=, RM= with RGB interface mode Write data through system interface to write data through RGB interface System Interface operation Write data to GRAM through system interface HWM=/ HWM=/ Set A[;] Set A[;] Set IR to Rh (GRAM data write) Set M[:]=, RM= with RGB interface mode Write data to GRAM through system interface System Interface operation Set IR to Rh (GRAM data write) RGB Interface operation Figure9 GRAM access between system interface and RGB interface Page 47 of 9 Version: 54

48 76 Interface Timing The following are diagrams of interfacing timing with LC panel control signals in internal operation and RGB interface modes VSYNC // HSYNC // OTCLK // ENABLE [:] // // FLM G G G3 S[7:] // VCOM Figure Relationship between RGB I/F signals and LC riving Signals for Panel Page 48 of 9 Version: 54

49 8 Register escriptions 8 Registers Access adopts 8-bit bus interface architecture for high-performance microprocessor All the functional blocks of starts to work after receiving the correct instruction from the external microprocessor by the 8-, -, 9-, 8-bit interface The index register (IR) stores the register address to which the instructions and display data will be written The register selection signal (RS), the read/write signals (n/nwr) and data bus - are used to read/write the instructions and data of The registers of the are categorized into the following groups Specify the index of register (IR) Read a status 3 isplay control 4 Power management Control 5 Graphics data processing 6 Set internal GRAM address (AC) 7 Transfer data to/from the internal GRAM (R) 8 Internal grayscale γ-correction (R3 ~ R39) Normally, the display data (GRAM) is most often updated, and in order since the can update internal GRAM address automatically as it writes data to the internal GRAM and minimize data transfer by using the window address function, there are fewer loads on the program in the microprocessor As the following figure shows, the way of assigning data to the register bits ([:]) varies for each interface Send registers in accordance with the following data transfer format Serial Peripheral Interface for register access SPI Input ata Register ata Figure Register Setting with Serial Peripheral Interface (SPI) Page 49 of 9 Version: 54

50 i8/m68 system 8-bit data bus interface ata Bus ([:]) Register Bit ([:]) i8/m68 system -bit data bus interface ata Bus ([:]), ([8:]) Register Bit ([:]) i8/m68 system 9-bit data bus interface ata Bus ([:9]) st Transfer 9 nd Transfer 9 Register Bit ([:]) i8/m68 system 8-bit data bus interface/serial peripheral interface (/3 transmission) ata Bus ([:]) st Transfer nd Transfer Register Bit ([:]) Figure Register setting with i8 System Interface Page 5 of 9 Version: 54

51 i8 8-/-bit System Bus Interface Timing (a) Write to register ncs RS n nwr [:] Write register index Write register data (b) Read from register ncs RS n nwr [:] Write register index Read register data i8 9-/8-bit System Bus Interface Timing (a) Write to register ncs RS n nwr [:] h Write register index Write register high byte data Write register low byte data (b) Read from register ncs RS n nwr [:] h Write register index Read register high byte data Read register low byte data Figure 3 Register Read/Write Timing of i8 System Interface Page 5 of 9 Version: 54

52 8 Instruction escriptions No Registers Name R/W RS IR Index Register W I7 I6 I5 I4 I3 I I I SR Status Read R L7 L6 L5 L4 L3 L L L h river Code Read R h Start Oscillation W OSC h river Output Control W SM SS h LC riving Control W B/C EOR 3h Entry Mode W TRI FM BGR HWM ORG I/ I/ AM 4h Resize Control W RCV RCV RCH RCH RSZ RSZ 7h isplay Control W PTE PTE BASEE GON TE CL 8h isplay Control W FP3 FP FP FP BP3 BP BP BP 9h isplay Control 3 W PTS PTS PTS PTG PTG ISC3 ISC ISC ISC Ah isplay Control 4 W FMARKOE FMI FMI FMI Ch RGB isplay Interface Control W ENC ENC ENC RM M M RIM RIM h Frame Maker Position W FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP FMP FMP Fh RGB isplay Interface Control W VSPL HSPL EPL PL h Power Control W SAP BT3 BT BT BT APE AP AP AP STB SLP h Power Control W C C C C C C VC VC VC h Power Control 3 W VCMR PON VRH3 VRH VRH VRH h Power Control 4 W VV4 VV3 VV VV VV h Horizontal GRAM Address Set W A7 A6 A5 A4 A3 A A A h Vertical GRAM Address Set W A A A A A A A A9 A8 h Write ata to GRAM W RAM write data (-) / read data (-) bits are transferred via different data bus lines according to the selected interfaces 9h Power Control 7 W VCM4 VCM3 VCM VCM VCM Bh Frame Rate and Color Control W EXT_R FR_SEL FR_SEL 3h Gamma Control W KP[] KP[] KP[] KP[] KP[] KP[] 3h Gamma Control W KP3[] KP3[] KP3[] KP[] KP[] KP[] 3h Gamma Control 3 W KP5[] KP5[] KP5[] KP4[] KP4[] KP4[] 35h Gamma Control 4 W RP[] RP[] RP[] RP[] RP[] RP[] 36h Gamma Control 5 W VRP[4] VRP[3] VRP[] VRP[] VRP[] VRP[4] VRP[3] VRP[] VRP[] VRP[] 37h Gamma Control 6 W KN[] KN[] KN[] KN[] KN[] KN[] 38h Gamma Control 7 W KN3[] KN3[] KN3[] KN[] KN[] KN[] 39h Gamma Control 8 W KN5[] KN5[] KN5[] KN4[] KN4[] KN4[] 3Ch Gamma Control 9 W RN[] RN[] RN[] RN[] RN[] RN[] Page 5 of 9 Version: 54

53 No Registers Name R/W RS h Gamma Control W VRN[4] VRN[3] VRN[] VRN[] VRN[] VRN[4] VRN[3] VRN[] VRN[] VRN[] 5h Horizontal Address Start Position W HSA7 HSA6 HSA5 HSA4 HSA3 HSA HSA HSA 5h Horizontal Address End Position W HEA7 HEA6 HEA5 HEA4 HEA3 HEA HEA HEA 5h Vertical Address Start Position W VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA VSA VSA 53h Vertical Address End Position W VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA VEA VEA 6h river Output Control W GS NL5 NL4 NL3 NL NL NL SCN5 SCN4 SCN3 SCN SCN SCN 6h Base Image isplay Control W NL VLE REV 6Ah Vertical Scroll Control W VL8 VL7 VL6 VL5 VL4 VL3 VL VL VL 8h Partial Image isplay Position W PTP8 PTP7 PTP6 PTP5 PTP4 PTP3 PTP PTP PTP 8h Partial Image Area (Start Line) W PTSA8 PTSA7 PTSA6 PTSA5 PTSA4 PTSA3 PTSA PTSA PTSA 8h Partial Image Area (End Line) W PTEA8 PTEA7 PTEA6 PTEA5 PTEA4 PTEA3 PTEA PTEA PTEA 83h Partial Image isplay Position W PTP8 PTP PTP PTP PTP PTP PTP PTP PTP 84h Partial Image Area (Start Line) W PTSA8 PTSA PTSA PTSA PTSA PTSA PTSA PTSA PTSA 85h Partial Image Area (End Line) W PTEA8 PTEA PTEA PTEA PTEA PTEA PTEA PTEA PTEA 9h Panel Interface Control W IVI IVI RTNI3 RTNI RTNI RTNI 9h Panel Interface Control W NOWI NOWI NOWI 93h Panel Interface Control 3 W MCPI MCPI MCPI 95h Panel Interface Control 4 W IVE IVE RTNE5 RTNE4 RTNE3 RTNE RTNE RTNE 97h Panel Interface Control 5 W NOWE3 NOWE NOWE NOWE 98h Panel Interface Control 6 W MCPE MCPE MCPE Page 53 of 9 Version: 54

54 8 Index (IR) R/W RS W I7 I6 I5 I4 I3 I I I The index register specifies the address of register (Rh ~ RFFh) or RAM which will be accessed 8 Status Read (RS) R/W RS R L7 L6 L5 L4 L3 L L L The SR bits represent the internal status of the L[7:] Indicates the position of driving line which is driving the TFT panel currently 83 Start Oscillation (Rh) R/W RS W OSC R Set the OSC bit as to start the internal oscillator and as to stop the oscillator Wait at least ms to let the frequency of oscillator stable and then do the other function setting The device code 93 h is read out when read this register 84 river Output Control (Rh) R/W RS W SM SS SS: Select the shift direction of outputs from the source driver When SS =, the shift direction of outputs is from S to S7 When SS =, the shift direction of outputs is from S7 to S In addition to the shift direction, the settings for both SS and BGR bits are required to change the assignment of R, G, B dots to the source driver pins To assign R, G, B dots to the source driver pins from S to S7, set SS = To assign R, G, B dots to the source driver pins from S7 to S, set SS = When changing SS or BGR bits, RAM data must be rewritten SM: Sets the gate driver pin arrangement in combination with the GS bit (R6h) to select the optimal scan mode for the module Page 54 of 9 Version: 54

55 SM GS Scan irection Gate Output Sequence G G G3 G4 Odd-number TFT Panel Even-number G to G39 G3 G39 G38 G3 G to G3 G, G, G3, G4,,G3 G3, G38, G39, G3 G G G3 G4 Odd-number TFT Panel Even-number G39 to G G3 G39 G38 G3 G3 to G G3, G39, G38,, G6, G5, G4, G3, G, G Odd-number G G G to G39 G39 TFT Panel G G3 Even-number G to G3 G, G3, G5, G7,,G3 G3, G3, G3, G39 G, G4, G6, G8,,G3 G3, G3, G38, G3 Odd-number G G TFT Panel G3, G38, G3,, G39 to G G39 G Even-number G, G8, G6, G4, G G39, G3, G3,, G3 G3 to G G9, G78, G5, G3, G Page 55 of 9 Version: 54

56 85 LC riving Wave Control (Rh) R/W RS W B/C EOR B/C : Frame/Field inversion : Line inversion EOR: EOR = and B/C= to set the line inversion 86 Entry Mode (R3h) R/W RS W TRI FM BGR HWM ORG I/ I/ AM AM Control the GRAM update direction When AM =, the address is updated in horizontal writing direction When AM =, the address is updated in vertical writing direction When a window area is set by registers R5h,R5h, R5h and R53h, only the addressed GRAM area is updated based on I/[:] and AM bits setting I/[:] Control the address counter (AC) to automatically increase or decrease by when update one pixel display data Refer to the following figure for the details I/[:] = Horizontal : decrement Vertical : decrement I/[:] = Horizontal : increment Vertical : decrement I/[:] = Horizontal : decrement Vertical : increment I/[:] = Horizontal : increment Vertical : increment AM = E E B B Horizontal B B E E AM = E E B B Vertical B B E E Figure4 GRAM Access irection Setting ORG Moves the origin address according to the I/[:] setting when a window address area is made This function is enabled when writing data with the window address area using high-speed RAM write ORG = : The origin address is not moved In this case, specify the address to start write operation according to the GRAM address map within the window address area Page 56 of 9 Version: 54

57 ORG = : The original address h moves according to the I/[:] setting Notes: When ORG=, only the origin address address h can be set in the RAM address set registers Rh, and Rh In RAM read operation, make sure to set ORG= HWM GRAM high speed write function HWM= : High speed write function disabled HWM= : High speed write function enabled BGR Swap the R and B order of written data BGR= : Follow the RGB order to write the pixel data BGR= : Swap the RGB data to BGR in writing into GRAM TRI When TRI =, data are transferred to the internal RAM in 8-bit x 3 transfers mode via the 8-bit interface It is also possible to send data via the -bit interface or SPI in the transfer mode that realizes display in 6k colors in combination with FM bits When not using these interface modes, be sure to set TRI = FM Set the mode of transferring data to the internal RAM when TRI = See the following figures for details TRI FM -bit MPU System Interface ata Format system -bit interface ( transfers/pixel) 65,536 colors * st Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,4 colors st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,4 colors st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure5 -bit MPU System Interface ata Format Page 57 of 9 Version: 54

58 TRI FM 8-bit MPU System Interface ata Format system 8-bit interface ( transfers/pixel) 65,536 colors * st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system 8-bit interface (3 transfers/pixel) 6,4 colors st Transfer nd Transfer 3rd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system 8-bit interface (3 transfers/pixel) 6,4 colors st Transfer nd Transfer 3rd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure6 8-bit MPU System Interface ata Format 87 Resizing Control Register (R4h) R/W RS W RCV RCV RCH RCH RSZ RSZ RSZ[:] Sets the resizing factor When the RSZ bits are set for resizing, the writes the data according to the resizing factor so that the original image is displayed in horizontal and vertical dimensions, which are contracted according to the factor respectively See Resizing function RCH[:] Sets the number of remainder pixels in horizontal direction when resizing a picture By specifying the number of remainder pixels by RCH bits, the data can be transferred without taking the reminder pixels into consideration Make sure that RCH = h when not using the resizing function (RSZ = h) or there are no remainder pixels RCV[:] Sets the number of remainder pixels in vertical direction when resizing a picture By specifying the number of remainder pixels by RCV bits, the data can be transferred without taking the reminder pixels into consideration Make sure that RCV = h when not using the resizing function (RSZ = h) or there are no remainder pixels RSZ[:] Resizing factor No resizing (x) x / Setting prohibited x /4 RCH[:] Number of remainder Pixels in Horizontal irection pixel* Page 58 of 9 Version: 54

59 pixel pixel 3 pixel RCV[:] Number of remainder Pixels in Vertical irection pixel* pixel pixel 3 pixel * pixel = RGB 88 isplay Control (R7h) R/W RS W PTE PTE BASEE GON TE CL [:] Set [:]= to turn on the display panel, and [:]= to turn off the display panel A graphics display is turned on the panel when writing =, and is turned off when writing = When writing =, the graphics display data is retained in the internal GRAM and the displays the data when writing = When =, ie while no display is shown on the panel, all source outputs becomes the GN level to reduce charging/discharging current, which is generated within the LC while driving liquid crystal with AC voltage When the display is turned off by setting [:] =, the continues internal display operation When the display is turned off by setting [:] =, the internal display operation is halted completely In combination with the GON, TE setting, the [:] setting controls display ON/OFF BASEE Source, VCOM Output internal operation GN Halt GN Operate Non-lit display Operate Non-lit display Operate Base image display Operate Note: data write operation from the microcontroller is performed irrespective of the setting of [:] bits The internal state of the in standby mode become the same as when [:] = This does not mean the [:] setting is changed when setting the standby mode 3 The [:] setting is valid on both st and nd displays 4 The non-lit display level from the source output pins is determined by instruction (PTS) CL When CL =, the 8-color display mode is selected CL Colors 6,4 8 Page 59 of 9 Version: 54

60 GON and TE Set the output level of gate driver G ~ G3 as follows GON TE G ~G3 Gate Output VGH VGH VGL Normal isplay BASEE Base image display enable bit When BASEE =, no base image is displayed The drives liquid crystal at non-lit display level or displays only partial images When BASEE =, the base image is displayed The [:] setting has higher priority over the BASEE setting PTE[:] Partial image and Partial image enable bits PTE/ = : turns off partial image Only base image is displayed PTE/ = : turns on partial image Set the base image display enable bit to (BASEE = ) 89 isplay Control (R8h) R/W RS W FP3 FP FP FP BP3 BP BP BP FP[3:]/BP[3:] The FP[3:] and BP[3:] bits specify the line number of front and back porch periods respectively When setting the FP[3:] and BP[3:] value, the following conditions shall be met: BP + FP lines FP lines BP lines Set the BP[3:] and FP[3:] bits as below for each operation modes Operation Mode BP FP BP+FP I8 System Interface Operation Mode BP lines FP lines FP +BP lines RGB interface Operation BP lines FP lines FP +BP lines VSYNC interface Operation BP lines FP lines FP +BP = lines FP[3:] Number of lines for Front Porch BP[3:] Number of lines for Back Porch Setting Prohibited Setting Prohibited lines 3 lines 4 lines 5 lines 6 lines 7 lines 8 lines 9 lines VSYNC Back Porch isplay Area Front Porch Page 6 of 9 Version: 54

61 lines lines lines lines lines Setting Prohibited 8 isplay Control 3 (R9h) R/W RS W PTS PTS PTS PTG PTG ISC3 ISC ISC ISC ISC[3:]: Specify the scan cycle interval of gate driver in non-display area when PTG[:]= to select interval scan Then scan cycle is set as odd number from ~3 frame periods The polarity is inverted every scan cycle ISC3 ISC3 ISC3 ISC3 Scan Cycle f FLM =6 Hz frame - 3 frame 5ms 5 frame 84ms 7 frame ms 9 frame ms frame 84ms frame ms frame 5ms frame 84ms 9 frame 3ms frame 35ms 3 frame 384ms 5 frame 48ms 7 frame 45ms 9 frame 484ms 3 frame 58ms PTG[:] Set the scan mode in non-display area PTG PTG Gate outputs in non-display area Source outputs in non-display area Vcom output Normal scan Set with the PTS[:] bits VcomH/VcomL Setting isabled - - Interval scan Set with the PTS[:] bits VcomH/VcomL Setting isabled - - PTS[:] Set the source output level in non-display area drive period (front/back porch period and blank area between partial displays) When PTS[] =, the operation of amplifiers which generates the grayscales other than V and V63 are halted and the step-up clock frequency becomes half the normal frequency in non-display drive period in order to reduce power consumption PTS[:] Source output level Grayscale amplifier Step-up clock frequency Page 6 of 9 Version: 54

62 Positive polarity Negative polarity in operation V63 V V63 to V Register Setting(C, C) Setting Prohibited Setting Prohibited - - GN GN V63 to V Register Setting(C, C) Hi-Z Hi-Z V63 to V Register Setting(C, C) V63 V V63 and V / frequency setting by C, C Setting Prohibited Setting Prohibited - - GN GN V63 and V / frequency setting by C, C Hi-Z Hi-Z V63 and V / frequency setting by C, C Notes: The power efficiency can be improved by halting grayscale amplifiers and slowing down the step-up clock frequency only in non-display drive period The gate output level in non-lit display area drive period is determined by PTG[:] 8 isplay Control 4 (RAh) R/W RS W FMARKOE FMI FMI FMI FMI[:] Set the output interval of FMARK signal according to the display data rewrite cycle and data transfer rate FMARKOE When FMARKOE=, starts to output FMARK signal in the output interval set by FMI[:] bits FMI[:] Output Interval frame frame 4 frame 6 frame Others Setting disabled 8 RGB isplay Interface Control (RCh) R/W RS W ENC ENC ENC RM M M RIM RIM RIM[:] Select the RGB interface data width RIM RIM RGB Interface Mode 8-bit RGB interface ( transfer/pixel), [:] -bit RGB interface ( transfer/pixel), [:] and [:] 6-bit RGB interface (3 transfers/pixel), [:] Setting disabled Note: Registers are set only by the system interface Note: Be sure that one pixel (3 dots) data transfer finished when interface switch M[:] Select the display operation mode M M isplay Interface Internal system clock RGB interface VSYNC interface Page 6 of 9 Version: 54

63 Setting disabled The M[:] setting allows switching between internal clock operation mode and external display interface operation mode However, switching between the RGB interface operation mode and the VSYNC interface operation mode is prohibited RM Select the interface to access the GRAM Set RM to when writing display data by the RGB interface RM Interface for RAM Access System interface/vsync interface RGB interface isplay State Operation Mode RAM Access (RM) isplay Operation Mode (M[:] Still pictures Internal clock operation Moving pictures RGB interface () Rewrite still picture area while RGB interface isplaying moving pictures Moving pictures VSYNC interface System interface (RM = ) RGB interface (RM = ) System interface (RM = ) System interface (RM = ) Note : Registers are set only via the system interface or SPI interface Note : Refer to the flowcharts of RGB Input Interface section for the mode switch Internal clock operation (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) VSYNC interface (M[:] = ) ENC[:] Set the GRAM write cycle through the RGB interface ENC[:] GRAM Write Cycle (Frame periods) Frame Frames 3 Frames 4 Frames 5 Frames 6 Frames 7 Frames 8 Frames 8 Frame Marker Position (h) R/W RS W FMP8 FMP7 FMP6 FMP5 FMP4 FMP3 FMP FMP FMP EMP[8:] Sets the output position of frame cycle (frame marker) When FMP[8:]=, a high-active pulse FMARK is output at the start of back porch period for one display line period (H) Make sure the 9 h FMP BP+NL+FP FMP[8:] FMARK Output Position 9 h th line 9 h st line 9 h nd line Page 63 of 9 Version: 54

64 9 h3 3 rd line 9 h5 373 rd line 9 h6 374 th line 9 h7 375 th line 8 RGB isplay Interface Control (RFh) R/W RS W VSPL HSPL EPL PL PL: Sets the signal polarity of the OTCLK pin PL = The data is input on the rising edge of OTCLK PL = The data is input on the falling edge of OTCLK EPL: Sets the signal polarity of the ENABLE pin EPL = The data - is written when ENABLE = isable data write operation when ENABLE = EPL = The data - is written when ENABLE = isable data write operation when ENABLE = HSPL: Sets the signal polarity of the HSYNC pin HSPL = Low active HSPL = High active VSPL: Sets the signal polarity of the VSYNC pin VSPL = Low active VSPL = High active 8 Power Control (Rh) R/W RS W SAP BT3 BT BT BT APE AP AP AP STB SLP SLP: When SLP =, enters the sleep mode and the display operation stops except the RC oscillator to reduce the power consumption In the sleep mode, the GRAM data and instructions cannot be updated except the following two instructions a Exit sleep mode (SLP = ) b Start oscillation STB: When STB =, the enters the deep standby mode In deep standby mode, the internal logic power supply is turned off to reduce power consumption The GRAM data and instruction setting are not maintained when the enters the deep standby mode, and they must be reset after exiting deep standby mode AP[:]: Adjusts the constant current in the operational amplifier circuit in the LC power supply circuit The Page 64 of 9 Version: 54

65 larger constant current enhances the drivability of the LC, but it also increases the current consumption Adjust the constant current taking the trade-off into account between the display quality and the current consumption In no-display period, set AP[:] = to halt the operational amplifier circuits and the step-up circuits to reduce current consumption AP[:] In LC drive power supply amplifiers In Source driver amplifiers Halt Halt SAP: Source river output control SAP=, Source driver output is disabled SAP=, Source driver output is enabled When starting the charge-pump of LC in the Power ON stage, make sure that SAP=, and set the SAP=, after starting up the LC power supply circuit APE: Power supply enable bit Set APE = to start the generation of power supply according to the power supply startup sequence BT[3:]: Sets the factor used in the step-up circuits Select the optimal step-up factor for the operating voltage To reduce power consumption, set a smaller factor BT[3:] VH VCL VGH VGL 4 h Vci x - Vci Vci x 6 - Vci x 5 4 h - Vci x 4 Vci x - Vci Vci x 8 4 h - Vci x 3 4 h3 - Vci x 5 4 h4 Vci x - Vci Vci x 7 - Vci x 4 4 h5 - Vci x 3 4 h6 - Vci x 4 Vci x - Vci Vci x 6 4 h7 - Vci x 3 4 h8 Vci x 3 - Vci Vci x 9 - Vci x 7 4 h9 - Vci x 6 Vci x 3 - Vci Vci x 4 ha - Vci x 4 4 hb - Vci x 7 4 hc Vci x 3 - Vci Vci x - Vci x 6 4 h - Vci x 4 4 he - Vci x 6 Vci x 3 - Vci Vci x 9 4 hf - Vci x 4 Notes: Connect capacitors to the capacitor connection pins when generating VH, VGH, VGL and VCL levels Make sure VH = 6V (max), VGH = V (max), VGL = 5V (max) and VCL= -3V (max) Page 65 of 9 Version: 54

66 8 Power Control (Rh) R/W RS W C C C C C C VC VC VC VC[:] Sets the ratio factor of VciLVL to generate the reference voltages VciOUT and Vci VC VC VC VciOUT reference voltage Vci voltage 94 x Vci 89 x Vci Setting disabled Setting disabled 76 x Vci Setting disabled Setting disabled x Vci C[:]: Selects the operating frequency of the step-up circuit The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption Adjust the frequency taking the trade-off between the display quality and the current consumption into account C[:]: Selects the operating frequency of the step-up circuit The higher step-up operating frequency enhances the drivability of the step-up circuit and the quality of display but increases the current consumption Adjust the frequency taking the trade-off between the display quality and the current consumption into account C C C Step-up circuit step-up frequency (f CC ) C C C Step-up circuit step-up frequency (f CC ) Fosc Fosc / Fosc / Fosc / 3 Fosc / 4 Fosc / 64 Fosc / 8 Fosc / 8 Fosc / Fosc / 56 Setting disabled Setting disabled Halt step-up circuit Halt step-up circuit Setting disabled Setting disabled Note: Be sure f CC f CC when setting C[:] and C[:] 8 Power Control 3 (Rh) R/W RS W VCMR PON VRH3 VRH VRH VRH VRH[3:] Set the amplifying rate ( ~ 9) of VciLVL applied to output the VREGOUT level, which is a reference level for the VCOM level and the grayscale voltage level VRH3 VRH VRH VRH VREGOUT VRH3 VRH VRH VRH VREGOUT Halt VciLVL x Page 66 of 9 Version: 54

67 Setting inhibited VciLVL x 5 Setting inhibited VciLVL x Setting inhibited VciLVL x 5 Setting inhibited VciLVL x 8 Setting inhibited VciLVL x 85 Setting inhibited VciLVL x 9 Setting inhibited Setting inhibited Make sure that VC and VRH setting restriction: VREGOUT (VH - 5)V PON: Control ON/OFF of circuit3 (VGL) output PON= VGL output is disable PON= VGL output is enable VCMR: Selects either external resistor (VcomR) or internal electric volume (VCM) to set the electrical potential of VcomH (Vcom center voltage level) VCMR = Using the external variable resistor to adjust the VcomH voltage level VCMR = Using the Internal electronic volume (VCM[4:]) to adjust the VcomH voltage level 88 Power Control 4 (Rh) R/W RS W VV4 VV3 VV VV VV VV[4:] Select the factor of VREGOUT to set the amplitude of Vcom alternating voltage from 7 to 4 x VREGOUT VV4 VV3 VV VV VV VCOM amplitude VV4 VV3 VV VV VV VCOM amplitude VREGOUT x 7 VREGOUT x 87 VREGOUT x 7 VREGOUT x 89 VREGOUT x 74 VREGOUT x 9 VREGOUT x 76 VREGOUT x 94 VREGOUT x 78 VREGOUT x 96 VREGOUT x 8 VREGOUT x 99 VREGOUT x 8 VREGOUT x VREGOUT x 84 VREGOUT x VREGOUT x 86 VREGOUT x VREGOUT x 88 VREGOUT x 9 VREGOUT x 9 VREGOUT x VREGOUT x 9 VREGOUT x 4 VREGOUT x 94 VREGOUT x VREGOUT x 96 VREGOUT x 9 VREGOUT x 98 VREGOUT x VREGOUT x VREGOUT x 4 Set VV[4:] to let Vcom amplitude less than 6V 89 GRAM Horizontal/Vertical Address Set (Rh, Rh) R/W RS W A7 A6 A5 A4 A3 A A A W A A A A A A A A9 A8 A[:] Set the initial value of address counter (AC) The address counter (AC) is automatically updated in accordance to the setting of the AM, I/ bits Page 67 of 9 Version: 54

68 as data is written to the internal GRAM The address counter is not automatically updated when read data from the internal GRAM A[:] GRAM ata Map h ~ hef st line GRAM ata h ~ hef nd line GRAM ata h ~ hef 3 rd line GRAM ata h3 ~ h3ef 4 th line GRAM ata h ~ hef 38 th line GRAM ata he ~ heef 39 th line GRAM ata hf ~ hfef 3 th line GRAM ata Note: When the RGB interface is selected (RM = ), the address A[:] is set to the address counter every frame on the falling edge of VSYNC Note: When the internal clock operation or the VSYNC interface mode is selected (RM = ), the address A[:] is set to address counter when update register R 8 Write ata to GRAM (Rh) R/W RS W RAM write data ([:], the [:] pin assignment differs for each interface This register is the GRAM access port When update the display data through this register, the address counter (AC) is increased/decreased automatically 8 Read ata from GRAM (Rh) R/W RS R RAM Read ata ([:], the [:] pin assignment differs for each interface [:] Read 8-bit data from GRAM through the read data register (R) Page 68 of 9 Version: 54

69 8-bit System Interface GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Write ata Register Output ata bit System Interface GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Write ata Register Output ata bit System Interface GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Write ata Register Output ata st Transfer 9 nd Transfer 9 8-bit System Interface / Serial ata Transfer Interface GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Write ata Register Output ata st Transfer nd Transfer Figure 7 ata Read from GRAM through Read ata Register in 8-/-/9-/8-bit Interface Mode Page 69 of 9 Version: 54

70 Set I/ AM, HAS/HEA, VSA/VEA Set address M ummy read (invalid data) GRAM -> Read data latch Read Output (data of address M) Read datalatch -> [:] Read Output (data of address M+) Read datalatch -> [:] Set address N ummy read (invalid data) GRAM -> Read data latch Read Output (data of address N) Read datalatch -> [:] Figure 8 GRAM ata Read Back Flow Chart 8 Power Control 7 (R9h) R/W RS W VCM4 VCM3 VCM VCM VCM VCM[4:] Set the internal VcomH voltage VCMR =, the VcomH voltage is generated based on the VCM[4:] setting value VCMR =, the VcomH voltage is generated based on the external reference voltage VCOMR VCM4 VCM3 VCM VCM VCM VCOMH VCM4 VCM3 VCM VCM VCM VCOMH VREGOUT x 69 VREGOUT x 85 VREGOUT x 7 VREGOUT x 86 VREGOUT x 7 VREGOUT x 87 VREGOUT x 7 VREGOUT x 88 VREGOUT x 73 VREGOUT x 89 Page 7 of 9 Version: 54

71 VREGOUT x 74 VREGOUT x 9 VREGOUT x 75 VREGOUT x 9 VREGOUT x 76 VREGOUT x 9 VREGOUT x 77 VREGOUT x 93 VREGOUT x 78 VREGOUT x 94 VREGOUT x 79 VREGOUT x 95 VREGOUT x 8 VREGOUT x 96 VREGOUT x 8 VREGOUT x 97 VREGOUT x 8 VREGOUT x 98 VREGOUT x 83 VREGOUT x 99 VREGOUT x 84 VREGOUT x 83 Frame Rate and Color Control (RBh) R/W RS W EXT_R FR_SEL FR_SEL EXT_R: Select the external or internal resistor for oscillator circuit EXT_R Resistor Selection Internal Resistor (default) External Resistor FR_SEL[:] Set the frame rate when the internal resistor is used for oscillator circuit FR_SEL FR_SEL Frame Rate (Hz) (default) 9 84 Gamma Control (R3h ~ R3h) R/W RS R3h W KP[] KP[] KP[] KP[] KP[] KP[] R3h W KP3[] KP3[] KP3[] KP[] KP[] KP[] R3h W KP5[] KP5[] KP5[] KP4[] KP4[] KP4[] R35h W RP[] RP[] RP[] RP[] RP[] RP[] R36h W VRP[4] VRP[3] VRP[] VRP[] VRP[] VRP[4] VRP[3] VRP[] VRP[] VRP[] R37h W KN[] KN[] KN[] KN[] KN[] KN[] R38h W KN3[] KN3[] KN3[] KN[] KN[] KN[] R39h W KN5[] KN5[] KN5[] KN4[] KN4[] KN4[] R3Ch W RN[] RN[] RN[] RN[] RN[] RN[] R3h W VRN[4] VRN[3] VRN[] VRN[] VRN[] VRN[4] VRN[3] VRN[] VRN[] VRN[] KP5-[:] : γfine adjustment register for positive polarity RP-[:] : γgradient adjustment register for positive polarity VRP-[4:] : γamplitude adjustment register for positive polarity Page 7 of 9 Version: 54

72 KN5-[:] : γfine adjustment register for negative polarity RN-[:] : γgradient adjustment register for negative polarity VRN-[4:] : γamplitude adjustment register for negative polarity For details γ-correction Function section 85 Horizontal and Vertical RAM Address Position (R5h, R5h, R5h, R53h) R/W RS R5h W HSA7 HSA6 HSA5 HSA4 HSA3 HSA HSA HSA R5h W HEA7 HEA6 HEA5 HEA4 HEA3 HEA HEA HEA R5h W VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA VSA VSA R53h W VEA8 VEA7 VEA6 VEA5 VEA4 VEA3 VEA VEA VEA HSA[7:]/HEA[7:] HSA[7:] and HEA[7:] represent the respective addresses at the start and end of the window address area in horizontal direction By setting HSA and HEA bits, it is possible to limit the area on the GRAM horizontally for writing data The HSA and HEA bits must be set before starting RAM write operation In setting these bits, be sure h HSA[7:]< HEA[7:] EF h and 4 h HEA-HAS VSA[8:]/VEA[8:] VSA[8:] and VEA[8:] represent the respective addresses at the start and end of the window address area in vertical direction By setting VSA and VEA bits, it is possible to limit the area on the GRAM vertically for writing data The VSA and VEA bits must be set before starting RAM write operation In setting, be sure h VSA[8:]< VEA[8:] F h h HSA HEA VSA Window Address Area VEA GRAM Address Area FEFh Figure 9 GRAM Access Range Configuration Page 7 of 9 Version: 54

73 h HAS[7:] HEA[7:] EF h h VSA[7:] VEA[7:] F h Note The window address range must be within the GRAM address space Note ata are written to GRAM in four-words when operating in high speed mode, the dummy write operations should be inserted depending on the window address area For details, see the High-Speed RAM Write Function section 86 Gate Scan Control (R6h, R6h, R6Ah) R/W RS R6h W GS NL5 NL4 NL3 NL NL NL SCN5 SCN4 SCN3 SCN SCN SCN R6h W NL VLE REV R6Ah W VL8 VL7 VL6 VL5 VL4 VL3 VL VL VL SCN[5:] The allows to specify the gate line from which the gate driver starts to scan by setting the SCN[5:] bits Scanning Start Position SCN[5:] SM= SM= GS= GS= GS= GS= h G G3 G G3 h G9 G3 G G34 h G G34 G33 G88 3h G5 G96 G49 G7 4h G33 G88 G65 G56 5h G4 G8 G8 G4 6h G49 G7 G97 G4 7h G57 G64 G G8 8h G65 G56 G9 G9 9h G73 G48 G5 G6 Ah G8 G4 G G Bh G89 G3 G7 G4 Ch G97 G4 G93 G8 h G G G9 G Eh G G8 G5 G96 Fh G G G4 G8 h G9 G9 G57 G64 h G7 G84 G73 G48 h G5 G6 G89 G3 h G3 G8 G35 G h G G G G39 h G9 G G8 G33 h G7 G4 G34 G87 h G85 G6 G5 G7 8h G93 G8 G66 G55 9h G G G8 G39 Ah G9 G G98 G3 Bh G G G4 G7 Ch G5 G96 G G9 h G33 G88 G6 G5 Eh G4 G8 G G9 Fh G49 G7 G8 G3 Page 73 of 9 Version: 54

74 h G57 G64 G94 G7 h G65 G56 G G h G73 G48 G6 G95 3h G8 G4 G4 G79 4h G89 G3 G58 G63 5h G97 G4 G74 G47 6h G35 G G9 G3 7h G3 G8 G36 G 8h ~ 3Fh Setting disabled Setting disabled Setting disabled Setting disabled NL[5:]: Sets the number of lines to drive the LC at an interval of 8 lines The GRAM address mapping is not affected by the number of lines set by NL[5:] The number of lines must be the same or more than the number of lines necessary for the size of the liquid crystal panel NL[5:] LC rive Line 6 h 4 lines 6 he 48 lines 6 hf 56 lines 6 h 64 lines 6 h 7 lines 6 h 8 lines 6 h3 88 lines 6 h4 96 lines 6 h5 34 lines 6 h6 3 line 6 h7 3 line Others Setting inhibited NL: Sets the source driver output level in the non-display area NL Non-isplay Area Positive Polarity Negative Polarity V63 V V V63 GS: Sets the direction of scan by the gate driver in the range determined by SCN[4:] and NL[4:] The scan direction determined by GS = can be reversed by setting GS = When GS =, the scan direction is from G to G3 When GS =, the scan direction is from G3 to G REV: Enables the grayscale inversion of the image by setting REV= REV GRAM ata Source Output in isplay Area Positive polarity negative polarity 8 h 8 h3ffff V63 V V V63 8 h V V63 Page 74 of 9 Version: 54

75 8 h3ffff V63 V VLE: Vertical scroll display enable bit When VLE =, the starts displaying the base image from the line (of the physical display) determined by VL[8:] bits VL[8:] sets the amount of scrolling, which is the number of lines to shift the start line of the display from the first line of the physical display Note that the partial image display position is not affected by the base image scrolling The vertical scrolling is not available in external display interface operation In this case, make sure to set VLE = VLE Base Image isplay Fixed Enable Scrolling VL[8:]: Sets the scrolling amount of base image The base image is scrolled in vertical direction and displayed from the line determined by VL[8:] Make sure that VL[8:] 3 87 Partial Image isplay Position (R8h) R/W RS W PT P[8] PTP[8:]: Sets the display position of partial image The display areas of the partial images and must not overlap each another PT P[7] PT P[6] PT P[5] PT P[4] PT P[3] PT P[] PT P[] PT P[] 88 Partial Image RAM Start/End Address (R8h, R8h) R/W RS W PTS A[8] PTS A[7] PTS A[6] PTS A[5] PTS A[4] PTS A[3] PTS A[] PTS A[] PTS A[] W PTE PTE PTE PTE PTE PTE PTE PTE PTE A[8] A[7] A[6] A[5] A[4] A[3] A[] A[] A[] PTSA[8:] PTEA[8:]: Sets the start line address and the end line address of the RAM area storing the data of partial image Make sure PTSA[8:] PTEA[8:] 89 Partial Image isplay Position (R83h) R/W RS W PTS P[8] PTP[8:]: Sets the display position of partial image The display areas of the partial images and must not overlap each another Page 75 of 9 Version: 54 PT P[7] PT P[6] PT P[5] PT P[4] PT P[3] PT P[] PT P[] PT P[]

76 83 Partial Image RAM Start/End Address (R84h, R85h) R/W RS W PTS A[8] PTS A[7] PTS A[6] PTS A[5] PTS A[4] PTS A[3] PTS A[] PTS A[] PTS A[] W PTE PTE PTE PTE PTE PTE PTE PTE PTE A[8] A[7] A[6] A[5] A[4] A[3] A[] A[] A[] PTSA[8:] PTEA[8:]: Sets the start line address and the end line address of the RAM area storing the data of partial image Make sure PTSA[8:] PTEA[8:] 83 Panel Interface Control (R9h) R/W RS W IVI IVI RTNI4 RTNI3 RTNI RTNI RTNI RTNI[4:]: Sets H (line) clock number of internal clock operating mode In this mode, display operation is synchronized with internal clock signal RTNI[4:] Clocks/Line RTNI[4:] Clocks/Line ~ Setting isabled 4 clocks clocks 5 clocks clocks 6 clocks 8 clocks 7 clocks 9 clocks 8 clocks clocks 9 clocks clocks 3 clocks clocks 3 clocks 3 clocks IVI[:]: Sets the division ratio of internal clock frequency IVI IVI ivision Ratio Internal Operation Clock Frequency fosc / fosc / 4 fosc / 4 8 fosc / 8 Formula to calculate frame frequency Frame Rate = f osc Clock cycles per line x division ratio x (Lines +BP+FP) f osc : frequency if RC oscillation Clock cycles per line : RTN bits ivision ratio : IV bits Lines : number of lines for driving the LC panel FP: Front porch lines BP; Back porch lines Page 76 of 9 Version: 54

77 83 Panel Interface Control (R9h) R/W RS W NOWI[] NOWI[] NOWI[] NOWI[:]: Sets the gate output non-overlap period when display operation is synchronized with internal clock signal NOWI[:] Gate Non-overlap Period clocks clocks clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (IVI), from the reference point 833 Panel Interface Control 3 (R93h) R/W RS W MCPI MCPI MCPI MCPI[:]: Sets the source output position when display operation is synchronized with internal clock signal MCPI[:] Source Output Position Setting inhibited clocks clocks 3 clocks 4 clocks 5 clocks 6 clocks 7 clocks Note: The gate output non-overlap period is defined by the number of frequency-divided internal clocks, the frequency of which is determined by instruction (IVI[:]), from the reference point 834 Panel Interface Control 4 (R95h) R/W RS W IVE IVE RTNE5 RTNE4 RTNE3 RTNE RTNE RTNE RTNE[5:]: Sets H (line) clock number of RGB interface mode In this mode, display operation is synchronized with RGB interface signals IVE (division ratio) x RTNE (OTCLKs) OTCLKs in H period RTNE[5:] Clocks per line period Clocks per line period Clocks per line period Clocks per line period RTNE[5:] RTNE[5:] RTNE[5:] (H) (H) (H) (H) h Setting Prohibited h clocks h 3 clocks 3h 48 clocks h Setting Prohibited h clocks h 33 clocks 3h 49 clocks Page 77 of 9 Version: 54

78 h Setting Prohibited h 8 clocks h 34 clocks 3h 5 clocks 3h Setting Prohibited h 9 clocks 3h 35 clocks 33h 5 clocks 4h Setting Prohibited h clocks 4h 36 clocks 34h 5 clocks 5h Setting Prohibited h clocks 5h 37 clocks 35h 53 clocks 6h Setting Prohibited h clocks 6h 38 clocks 36h 54 clocks 7h Setting Prohibited h 3 clocks 7h 39 clocks 37h 55 clocks 8h Setting Prohibited 8h 4 clocks 8h 4 clocks 38h 56 clocks 9h Setting Prohibited 9h 5 clocks 9h 4 clocks 39h 57 clocks ah Setting Prohibited ah 6 clocks ah 4 clocks 3ah 58 clocks bh Setting Prohibited bh 7 clocks bh 43 clocks 3bh 59 clocks ch Setting Prohibited ch 8 clocks ch 44 clocks 3ch 6 clocks dh Setting Prohibited dh 9 clocks dh 45 clocks 3dh 6 clocks eh Setting Prohibited eh 3 clocks eh 46 clocks 3eh 6 clocks fh Setting Prohibited fh 3 clocks fh 47 clocks 3fh 63 clocks IVE[:]: Sets the division ratio of OTCLK when display operation is synchronized with RGB interface signals IVE[:] ivision Ratio 8/-bit RGB Interface OTCLK=5MHz 6-bit x 3 Transfers RGB Interface OTCLK=5MHz Setting Prohibited Setting Prohibited - Setting Prohibited - /4 4 OTCLKS 8 μs OTCLKS 8 μs /8 8 OTCLKS μs 4 OTCLKS μs / OTCLKS 3 μs 48 OTCLKS 3 μs 835 Panel Interface Control 5 (R97h) R/W RS W NOWE3 NOWE NOWE NOWE NOWE[:]: Sets the gate output non-overlap period when the display operation is synchronized with RGB interface signals NOWE[3:] Gate Non-overlap Period NOWE[3:] Gate Non-overlap Period clocks 8 clocks clocks 9 clocks clocks clocks 3 clocks clocks 4 clocks clocks 5 clocks clocks 6 clocks clocks 7 clocks clocks Note: clock = (number of data transfer/pixel) x IVE (division ratio) [OTCLK] 836 Panel Interface Control 6 (R98h) R/W RS W MCPE MCPE MCPE MCPE[:]: Sets the source output position when the display operation is synchronized with RGB interface signals MCPE[:] Source Output Position clocks clocks clocks 3 clocks Page 78 of 9 Version: 54

79 4 clocks 5 clocks 6 clocks 7 clocks Note: clock = (number of data transfer/pixel) x IVE (division ratio) [OTCLK] Page 79 of 9 Version: 54

80 9 GRAM Address Map & Read/Write has an internal graphics RAM (GRAM) of 87, bytes to store the display data and one pixel is constructed of 8 bits The GRAM can be accessed through the i8 system, SPI and RGB interfaces i8 8-/-bit System Bus Interface Timing (a) Write to GRAM ncs RS n nwr [:] Write h to index register Write GRAM data Nth pixel Write GRAM data (N+)th pixel Write GRAM data (N+)th pixel Write GRAM data (N+3)th pixel (b) Read from GRAM ncs RS n nwr [:] Write h to index register ummy Read st Read data Nth pixel nd Read data (N+)th pixel 3rd Read data (N+)th pixel i8 9-/8-bit System Bus Interface Timing (a) Write to GRAM ncs RS n nwr [:9] h h st write high byte st write low byte nd write high byte nd write low byte 3rd write high byte 3rd write low byte Nth pixel (N+)th pixel (N+)th pixel (b) Read from GRAM ncs RS n nwr [:9] h h ummy Read ummy Read st read high byte st read low byte nd read high byte nd read low byte Nth pixel (N+)th pixel Figure3 GRAM Read/Write Timing of i8-system Interface Page 8 of 9 Version: 54

81 GRAM address map table of SS=, BGR= SS=, BGR= S S3 S4 S6 S7 S9 S S S5 S59 S5 S5 S53 S55 S56 S7 GS= GS= G G3 h h h 3h ECh Eh EEh EFh G G39 h h h h ECh Eh EEh EFh G3 G38 h h h 3h ECh Eh EEh EFh G4 G3 3h 3h 3h 33h 3ECh 3Eh 3EEh 3EFh G5 G3 4h 4h 4h 43h 4ECh 4Eh 4EEh 4EFh G6 G3 5h 5h 5h 53h 5ECh 5Eh 5EEh 5EFh G7 G3 6h 6h 6h 63h 6ECh 6Eh 6EEh 6EFh G8 G3 7h 7h 7h 73h 7ECh 7Eh 7EEh 7EFh G9 G3 8h 8h 8h 83h 8ECh 8Eh 8EEh 8EFh G G3 9h 9h 9h 93h 9ECh 9Eh 9EEh 9EFh G3 G 6h 6h 6h 63h 6ECh 6Eh 6EEh 6EFh G3 G9 7h 7h 7h 73h 7ECh 7Eh 7EEh 7EFh G3 G8 8h 8h 8h 83h 8ECh 8Eh 8EEh 8EFh G3 G7 9h 9h 9h 93h 9ECh 9Eh 9EEh 9EFh G3 G6 Ah Ah Ah A3h AECh AEh AEEh AEFh G3 G5 Bh Bh Bh B3h BECh BEh BEEh BEFh G3 G4 Ch Ch Ch C3h CECh CEh CEEh CEFh G38 G3 h h h 3h ECh Eh EEh EFh G39 G Eh Eh Eh E3h EECh EEh EEEh EEFh G3 G Fh Fh Fh F3h FECh FEh FEEh FEFh Page 8 of 9 Version: 54

82 i8/m68 system 8-bit data bus interface GRAM ata RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (3n+) S (3n+) S (3n+3) N= to 5 i8/m68 system -bit data bus interface GRAM ata RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (3n+) S (3n+) S (3n+3) N= to 5 i8/m68 system 9-bit data bus interface st Transfer nd Transfer GRAM ata 9 9 RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (3n+) S (3n+) S (3n+3) N= to 5 GRAM ata and display data of 8-/-/9-bit system interface (SS= ", BGR= ") Figure3 i8-system Interface with 8-/-/9-bit ata Bus (SS=, BGR= ) Page 8 of 9 Version: 54

83 i8/m68 system 8-bit interface / SPI Interface ( transfers/pixel) GRAM ata st transfer nd transfer RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (3n+) S (3n+) S (3n+3) N= to 5 i8/m68 system 8-bit interface (3 transfers/pixel, TRI= ", FM[:]= ") st Transfer nd Transfer 3 rd Transfer GRAM ata RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (3n+) S (3n+) S (3n+3) N= to 5 i8/m68 system 8-bit interface (3 transfers/pixel, TRI= ", FM[:]= ) GRAM ata st Transfer nd Transfer 3 rd Transfer RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (3n+) S (3n+) S (3n+3) N= to 5 i8/m68 system 8-bit interface (SS= ", BGR= ") Figure3 i8-system Interface with 8-bit ata Bus (SS=, BGR= ) Page 83 of 9 Version: 54

84 GRAM address map table of SS=, BGR= SS=, BGR= S7 S78 S7 S7 S7 S7 S7 S79 S S S9 S7 S6 S4 S3 S GS= GS= G G3 h h h 3h ECh Eh EEh EFh G G39 h h h h ECh Eh EEh EFh G3 G38 h h h 3h ECh Eh EEh EFh G4 G3 3h 3h 3h 33h 3ECh 3Eh 3EEh 3EFh G5 G3 4h 4h 4h 43h 4ECh 4Eh 4EEh 4EFh G6 G3 5h 5h 5h 53h 5ECh 5Eh 5EEh 5EFh G7 G3 6h 6h 6h 63h 6ECh 6Eh 6EEh 6EFh G8 G3 7h 7h 7h 73h 7ECh 7Eh 7EEh 7EFh G9 G3 8h 8h 8h 83h 8ECh 8Eh 8EEh 8EFh G G3 9h 9h 9h 93h 9ECh 9Eh 9EEh 9EFh G3 G 6h 6h 6h 63h 6ECh 6Eh 6EEh 6EFh G3 G9 7h 7h 7h 73h 7ECh 7Eh 7EEh 7EFh G3 G8 8h 8h 8h 83h 8ECh 8Eh 8EEh 8EFh G3 G7 9h 9h 9h 93h 9ECh 9Eh 9EEh 9EFh G3 G6 Ah Ah Ah A3h AECh AEh AEEh AEFh G3 G5 Bh Bh Bh B3h BECh BEh BEEh BEFh G3 G4 Ch Ch Ch C3h CECh CEh CEEh CEFh G38 G3 h h h 3h ECh Eh EEh EFh G39 G Eh Eh Eh E3h EECh EEh EEEh EEFh G3 G Fh Fh Fh F3h FECh FEh FEEh FEFh Page 84 of 9 Version: 54

85 i8/m68 system 8-bit data bus interface GRAM ata RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (58-3n) S (57-3n) S (56-3n) N= to 5 i8/m68 system 9-bit data bus interface st Transfer nd Transfer GRAM ata 9 9 RGB Assignment R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Source Output Pin S (58-3n) S (57-3n) S (56-3n) N= to 5 GRAM ata and display data of 8-/9-bit system interface (SS= ", BGR= ") Figure 33 i8-system Interface with 8-/9-bit ata Bus (SS=, BGR= ) Page 85 of 9 Version: 54

86 Window Address Function a-si TFT LC Single Chip river The window address function enables writing display data consecutively in a rectangular area (a window address area) made on the internal RAM The window address area is made by setting the horizontal address register (start: HSA[7:], end: HEA[7:] bits) and the vertical address register (start: VSA[8:], end: VEA[8:] bits) The AM bit sets the transition direction of RAM address (either increment or decrement) These bits enable the to write data including image data consecutively not taking data wrap positions into account The window address area must be made within the GRAM address map area Also, the GRAM address bits (RAM address set register) must be an address within the window address area [Window address setting area] (Horizontal direction) H HSA[7:] HEA[7:] EF H (Vertical direction) H VSA[8:] VEA[8:] F H [RAM address, A (an address within a window address area)]] (RAM address) HSA[7:] A[7:] HEA[7:] VSA[8:] A[:8] VEA[8:] GRAM Address Map h EF h Window Address Area h h 3Fh Fh 4Fh 4F3Fh F h FEF h Window address setting area HSA[7:] = h, HSA[7:] = 3Fh, VSA[8:] = h, VSA[8:] = 4Fh, I/ = (increment) AM = (horizontal writing) Figure 34 GRAM Access Window Map Page 86 of 9 Version: 54

87 Page 87 of 9 Version: 54

88 Gamma Correction incorporates the γ-correction function to display 6,4 colors for the LC panel The γ-correction is performed with 3 groups of registers determining eight reference grayscale levels, which are gradient adjustment, amplitude adjustment and fine-adjustment registers for positive and negative polarities, to make available with liquid crystal panels of various characteristics VREGOUT PRP/N Gradient Adjustment Register PRP/N Fine Adjustment Registers (6 x 3 bits) PKP/N5 PKP/N4 PKP/N3 PKP/N PKP/N PKP/N Amplitude Adjustment Register VRP/N VRP/N VgP/VgN V 8 to selection VgP/VgN V V 8 to selection VgP8/VgN8 V7 V8 8 to selection VgP/VgN V 8 to selection VgP43/VgN43 V43 8 to selection VgP55/VgN55 V55 V56 8 to selection VgP6/VgN6 V6 V6 VgP63/VgN63 V63 VGS Figure 35 Grayscale Voltage Generation Page 88 of 9 Version: 54

89 VREGOUT uf/v VROP ~ 6R VRP[4:] VgP VRON ~ 6R VRN[4:] VgN 5R 4R{ RP RP RP RP3 RP4 RP5 RP6 RP7 VP VP VP3 VP4 VP5 VP6 VP7 VP8 8 to Selection PKP[:] VgP 5R 4R{ RN RN RN RN3 RN4 RN5 RN6 RN7 VN VN VN3 VN4 VN5 VN6 VN7 VN8 8 to Selection PKN[:] VgN VRCP ~ 8R R{ RP8 RP9 RP RP RP RP RP PRP[:] VP9 VP VP VP VP VP VP VP 8 to Selection PKP[:] VgP8 VRCP ~ 8R R{ RN8 RN9 RN RN RN RN RN PRN[:] VN9 VN VN VN VN VN VN VN 8 to Selection PKN[:] VgN8 R{ RP RP RP RP8 RP9 RP RP RP VP VP8 VP9 VP VP VP VP3 VP4 8 to Selection PKP[:] VgP R{ RN RN RN RN8 RN9 RN RN RN VN VN8 VN9 VN VN VN VN3 VN4 8 to Selection PKN[:] VgN R{ RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP3 VP5 VP6 VP7 VP8 VP9 VP3 VP3 VP3 8 to Selection PKP3[:] VgP43 R{ RN3 RN4 RN5 RN6 RN7 RN8 RN9 RN3 VN5 VN6 VN7 VN8 VN9 VN3 VN3 VN3 8 to Selection PKN3[:] VgN43 R{ RP3 RP3 RP33 RP34 RP35 RP36 RP37 RP38 VP33 VP34 VP35 VP36 VP37 VP38 VP39 VP4 8 to Selection PKP4[:] VgP55 R{ RN3 RN3 RN33 RN34 RN35 RN36 RN37 RN38 VN33 VN34 VN35 VN36 VN37 VN38 VN39 VN4 8 to Selection PKN4[:] VgN55 VRCP ~ 8R 4R{ RP39 RP4 RP4 RP4 RP43 RP44 RP45 PRP[:] VP4 VP4 VP43 VP44 VP45 VP46 VP47 VP48 8 to Selection PKP5[:] VgP6 VRCN ~ 8R 4R{ RN39 RN4 RN4 RN4 RN43 RN44 RN45 PRN[:] VN4 VN4 VN43 VN44 VN45 VN46 VN47 VN48 8 to Selection PKN5[:] VgN6 5R RP46 VP49 VgP63 5R RN46 VN49 VgN63 VROP ~ 3R VRP[4:] VRON ~ 3R VRN[4:] VGS 8R RP47 8R RN47 Figure 36 Grayscale Voltage Adjustment Page 89 of 9 Version: 54

90 Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient of the curve representing the relationship between the grayscale and the grayscale reference voltage level To adjust the gradient, the resistance values of variable resistors in the middle of the ladder resistor are adjusted by registers PRP[:]/PRN[:], PRP[:]/PRN[:] The registers consist of positive and negative polarity registers, allowing asymmetric drive Amplitude adjustment registers The amplitude adjustment registers, VRP[4:]/VRN[4:], VRP[4:]/VRN[4:], are used to adjust the amplitude of grayscale voltages To adjust the amplitude, the resistance values of variable resistors at the top and bottom of the ladder resistor are adjusted Same as the gradient registers, the amplitude adjustment registers consist of positive and negative polarity registers 3 Fine adjustment registers The fine adjustment registers are used to fine-adjust grayscale voltage levels To fine-adjust grayscale voltage levels, fine adjustment registers adjust the reference voltage levels, 8 levels for each register generated from the ladder resistor, in respective 8-to- selectors Same with other registers, the fine adjustment registers consist of positive and negative polarity registers Grayscale voltage Grayscale voltage Grayscale voltage Gradient adjustment Amplitude adjustment Fine adjustment Figure 37 Gamma Curve Adjustment Register Groups Positive Polarity Negative Polarity escription Gradient PRP [:] PRN [:] Variable resistor VRCP, VRCN adjustment PRP [:] PRN [:] Variable resistor VRCP, VRCN Amplitude VRP [4:] VRN [4:] Variable resistor VROP, VRON adjustment VRP [4:] VRN [4:] Variable resistor VROP, VRON KP [:] KN [:] 8-to- selector (voltage level of grayscale ) KP [:] KN [:] 8-to- selector (voltage level of grayscale 8) Fine adjustment KP [:] KN [:] 8-to- selector (voltage level of grayscale ) KP3 [:] KN3 [:] 8-to- selector (voltage level of grayscale 43) KP4 [:] KN4 [:] 8-to- selector (voltage level of grayscale 55) KP5 [:] KN5 [:] 8-to- selector (voltage level of grayscale 6) Page 9 of 9 Version: 54

91 Ladder resistors and 8-to- selector Block configuration The reference voltage generating block consists of two ladder resistor units including variable resistors and 8-to- selectors Each 8-to- selector selects one of the 8 voltage levels generated from the ladder resistor unit to output as a grayscale reference voltage Both variable resistors and 8-to- selectors are controlled according to the γ-correction registers This unit has pins to connect a volume resistor externally to compensate differences in various characteristics of panels Variable resistors uses variable resistors of the following three purposes: gradient adjustment (VRCP(N)/VRCP(N)); amplitude adjustment () (VROP(N)); and the amplitude adjustment () (VROP(N)) The resistance values of these variable resistors are set by gradient adjustment registers and amplitude adjustment registers as follows Gradient adjustment Amplitude adjustment () Amplitude adjustment () PRP(N)/[:] Register VRCP(N) Resistance VRP(N)[4:] Register VROP(N) Resistance VRP(N)[4:] Register VROP(N) Resistance R R R 4R R R 8R 4R R R : : : : R : : : : R 58R 9R 4R 6R 3R 8R 6R 3R 8-to- selectors The 8-to- selector selects one of eight voltage levels generated from the ladder resistor unit according to the fine adjustment register and output the selected voltage level as a reference grayscale voltage (VgP(N)~6) The table below shows the setting in the fine adjustment register and the selected voltage levels for respective reference grayscale voltages Fine adjustment registers and selected voltage Register Selected Voltage KP(N)[:] VgP(N) VgP(N)8 VgP(N) VgP(N)43 VgP(N)55 VgP(N)6 VP(N) VP(N)9 VP(N) VP(N)5 VP(N)33 VP(N)4 VP(N) VP(N) VP(N)8 VP(N)6 VP(N)34 VP(N)4 VP(N)3 VP(N) VP(N)9 VP(N)7 VP(N)35 VP(N)43 VP(N)4 VP(N) VP(N) VP(N)8 VP(N)36 VP(N)44 VP(N)5 VP(N) VP(N) VP(N)9 VP(N)37 VP(N)45 VP(N)6 VP(N) VP(N) VP(N)3 VP(N)38 VP(N)46 VP(N)7 VP(N) VP(N)3 VP(N)3 VP(N)39 VP(N)47 VP(N)8 VP(N) VP(N)4 VP(N)3 VP(N)4 VP(N)48 Page 9 of 9 Version: 54

92 Source river Output (S[384:]) VCOM Negative polarity Postive polarity Figure 38 Relationship between Source Output and VCOM V Negative Polarity Source Output Levels Positive Polarity V63 GRAM ata Figure 39 Relationship between GRAM ata and Output Level Page 9 of 9 Version: 54

93 Application a-si TFT LC Single Chip river Configuration of Power Supply Circuit Page 93 of 9 Version: 54

94 a-si TFT LC Single Chip river IM IM3 nreset HSYNC ENABLE SO n RS FLM IM IM VSYNC OTCLK SI nwr ncs IOVCC VCC VPP VPP VPP3 VCC IOVCC uf/63v uf/63v uf/63v uf/63v uf/63v uf/63v uf/63v uf/v uf/v uf/5v uf/5v uf/v uf/v uf/v uf/v < 5 ohm < 5 ohm < 5 ohm < ohm < ohm < ohm < ohm < ohm < ohm ohm < ohm < ohm ohm < ohm < ohm < ohm < ohm ohm < ohm < ohm < ohm ohm < ohm < ohm ohm < ohm < ohm ohm < ohm ohm < ohm ohm < ohm < ohm ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < 5 ohm < 5 ohm < 5 ohm < 5 ohm < ohm < ohm < ohm < ohm < 5 ohm < 5 ohm < 5 ohm < 5 ohm < 5 ohm < ohm < 5 ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm < ohm UMMYR UMMYR TESTO VCCUM VPP VPP VPP VPP VPP VPP VPP VPP VPP3 VPP3 VPP3 TESTO IOGNUM TESTO3 TEST TEST TEST4 TEST5 TEST3 IM/I IM IM IM3 TESTO4 IOVCCUM TESTO5 nreset VSYNC HSYNC OTCLK ENABLE 9 8 TESTO6 IOGNUM TESTO SO SI n nwr/scl RS ncs TESTO8 IOVCCUM TESTO9 FMARK TS8 TS7 TS6 TS5 TS4 TS3 TS TS TS TSC TESTO IOGNUM3 TESTO TESTO OSCUM OSCUM OSC OSCUM3 OSCUM4 OSC OSCUM OSCUM UMMYR3 UMMYR4 IOGN IOGN IOGN IOGN IOGN IOGN IOGN IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC VCC VCC VCC VCC VCC VCC VCC VCC V V V V V V V V V V V V V TESTO VREF TESTO VREF TESTO VREFC TESTO VTEST AGN AGN AGN AGN AGN AGN AGN AGN AGN AGN AGN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN GN TESTO VTEST TESTO8 VGS TESTO9 VT TESTO VMON TESTO V3T VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH VCOML VCOML VCOML VCOML VCOML VCOML TESTO TESTO3 VREGOUT TESTO4 TESTA5 TESTO5 VCOMR TESTO6 VCL VCL VCL VLOUT VLOUT VLOUT VH VH VH VH VH VH VH VCIOUT VCIOUT VCIOUT VCI VCI VCI VCI VCI VCILVL VCI VCI VCI VCI VCI VCI VCI VCI C- C- C- C- C- C+ C+ C+ C+ C+ C- C- C- C- C- C+ C+ C+ C+ C+ AGNUM VLOUT3 VLOUT3 VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGNUM AGNUM3 AGNUM4 VLOUT VLOUT VGH VGH VGH VGH TESTO7 C- C- C- TESTO8 C+ C+ C+ TESTO9 C- C- C- C+ C+ C+ C- C- C- C+ C+ C+ C3- C3- C3- C3+ C3+ C3+ TESTO3 (-a) X Face Up (Bump View) UMMYR5 UMMYR6 G VGLMY UMMYR8 The information contained herein is the exclusive property of ILI Technology UMMYR7 Corp and shall not be distributed, TESTO3 TESTO3 (-b) Page 94 of 9 Version: 54 um Y um TESTO38 TESTO37 UMMYR UMMYR9 VGLMY4 G G4 G6 G8 G G3 G3 G3 G38 G3 VGLMY3 TESTO36 TESTO35 S S S3 S4 S5 S6 S7 S8 S9 G9 G7 G5 G3 S7 S7 S7 S7 S7 S7 S78 S79 S7 TESTO34 TESTO33 VGLMY G39 G3 G3 G3 G3

95 Figure 4 Power Supply Circuit Block The following table shows specifications of external elements connected to the s power supply circuit Items Recommended Specification Pin connection Capacity µf (B characteristics) Schottky diode 6V V 5V VF<4V/mA at 5 C, VR 3V (Recommended diode: HSC6) VREGOUT, VCI, V, VCL, VCOMH, VCOML, C+/-, C+/- VH, C+/-, C+/-, C3+/- VGH, VGL (AGN VGL), (Vci VGH), (Vci VH) Variable resistor > kω VCOMR isplay ON/OFF Sequence isplay Off Flow isplay On Flow isplay OFF GON = TE = [:] = isplay OFF GON = TE = [:] = Power Setting isplay On BASEE= GON = TE = [:] = Wait for frames or more isplay OFF GON = TE = [:] = isplay On BASEE= GON = TE = [:] = Power Supply Off SAP = APE= AP[:] = PON = isplay ON isplay Off Page 95 of 9 Version: 54

96 Figure 4 isplay On/Off Register Setting Sequence 3 eep Standby and Sleep Mode eep Standby Mode Sleep Mode Enter deep standby mode isplay Off Sequence Set Rh:STB = isplay Off Sequence Set Sleep (SLP = ) Release from Sleep (SLP = ) Release from Sleep Set ncs pin = Low, then Set ncs pin = High Power Supply Seeting Release from deep standby Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Set ncs pin low to high x6 isplay On Sequence Set ncs pin = Low, then Set ncs pin = High Set ncs pin = Low, then Set ncs pin = High Registers set as default value 's register setting GRAM data setting isplay On Sequence Figure 4 eep Standby/Sleep Mode Register Setting Sequence Page 96 of 9 Version: 54

97 4 Power Supply Configuration When supplying and cutting off power, follow the sequence below The setting time for oscillators, step-up circuits and operational amplifiers depends on external resistance and capacitance Power Supply ON (V CC, V CI, IOV CC) V CC IOV CC V CI Normal isplay isplay ON Setting TE= [:]= GON= GN V CC IOV CC V CI or V CC, IOV CC, V CI Simultaneously isplay OFF Sequence ms or more ms or more Oscillator Stabilizing time LC Power Supply ON Sequence Power On Reset and isplay OFF Registers setting before power supply startup isplay OFF Setting TE = [:] = GON = PON = Power supply initial setting Set VC[:], VRH[3:], VCM[4;], VV[4:], PON=, K= isplay OFF Power Supply Halt Setting SAP[:] = AP[:] = PON = Registers setting for power supply startup () Power supply operation setting () BT[:] = Set C[:], C[:] PON = Set AP[:] Power Supply OFF (V CC, V CI, IOV CC) V CI IOV CC V CC 4ms or more Step-up circuit stabilizing time GN V CI IOV CC V CC or Operational Amplifier stabilizing time Registers setting for power supply startup () Set the other registers Power supply operation setting () Set BT[:] V CC, IOV CC, V CI Simultaneously Power OFF Sequence isplay ON Sequence Set SAP[:] isplay ON TE= [:]= GON= Power ON Sequence Figure 43 Power Supply ON/OFF Sequence Page 97 of 9 Version: 54

98 5 Voltage Generation The pattern diagram for setting the voltages and the waveforms of the voltages of the are as follows BT VGH VGH (+9 ~ 5V) VH VH (45 ~ 6V) Vci (5 ~ 33V) VC REGP, VCI VRH VCM/VcomR VV VREGOUT (VCI ~ (VH-5)V ) VCOMH (VCI ~ (VH-5)V ) VciLVL VCOML (VCL+5) ~ V ) VCOMG VCL VCL ( ~ -VCI) BT VGL VGL (-4 ~ -5V) Figure 44 Voltage Configuration iagram Note: The VH, VGH, VGL, and VCL output voltage levels are lower than their theoretical levels (ideal voltage levels) due to current consumption at respective outputs The voltage levels in the following relationships (VH VREGOUT ) > 5V, (VCOML VCL) > 5V, (VCOML VCL) > 5V are the actual voltage levels When the alternating cycles of VCOM are set high (eg the polarity inverts every line cycle), current consumption is large In this case, check the voltage before use Page 98 of 9 Version: 54

99 6 Applied Voltage to the TFT panel VGH Gate Output VCOM Source output VGL Figure 45 Voltage Output to TFT LC Panel 7 Oscillator generates oscillation with the s internal RC oscillators by placing an external resistor between the OSC and OSC pins The oscillation frequency varies with resistance value of external resistor, wiring distance, and operating supply voltage For example, placing a Rosc resistor of larger resistance value or lower the supply voltage level will generate a lower oscillation frequency See the Notes to Electrical Characteristics section for the relationship between resistance value of Rosc resistor and oscillation frequency External Input Clock Example Internal RC Oscillator Example External Clock amping Resistor (K ohm) OSC AGN Rosc Rosc shall be placed as close to OSC and AGN as possible OSC AGN Figure 46 Oscillation Connection Page 99 of 9 Version: 54

100 8 Frame Rate Adjustment The has a frame frequency adjustment function The frame frequency for driving LCs can be adjusted by registers (using the IV, RTN bits) without changing the oscillation frequency To switch frame frequencies between when displaying a moving picture and when displaying a still picture, set a high oscillation frequency in advance By doing so, it becomes possible to set a low frame frequency when displaying a still picture for saving power consumption and to set a high frame frequency when displaying a moving picture Relationship between Liquid Crystal rive uty and Frame Frequency The relationship between the liquid crystal drive duty and the frame frequency is calculated from the following formula The frame frequency is adjusted by register using the H period adjustment bits (RTN bits) and the operation clock division bits (IV bits) Formula to calculate frame frequency Formula rate = f osc Clock cycles per line x division ratio x (Lines +BP+FP) f osc : frequency if RC oscillation Clock cycles per line : RTN bits ivision ratio : IV bits Lines : number of lines for driving the LC panel FP: Front porch lines BP; Back porch lines Example of Calculation: when maximum frame frequency = 6 Hz Number of lines to drive the LC: 3 lines H period: clock cycle (RTNI[4:] = ) Operational clock division ratio: / fosc = 6 Hz ( + ) clock / (3 + ) lines = 356 (khz) In this case, the RC oscillation frequency is 356kHz Adjust the external resistor of the RC oscillator to 356kHz 9 Partial isplay Function The allows selectively driving two partial images on the screen at arbitrary positions set in the screen drive position registers The following example shows the setting for partial display function: Base Image isplay Setting BASEE NL[5:] 6 h7 Page of 9 Version: 54

101 Partial Image isplay Setting PTE PTSA[8:] 9 h PTEA[8:] 9 hf PTP[8:] 9 h8 Partial Image isplay Setting PTE PTSA[8:] 9 h PTEA[8:] 9 hf PTP[8:] 9 hc PTSA=9'h GRAM MAP Partial Image GRAM Area LC Panel (st line) (nd line) (3rd line) PTEA=9'hF PTSA=9'h PTEA=9'hF Partial Image GRAM Area Partial Image isplay Area PTP=9'h8 PTP=9'hC Partial Image isplay Area 39 (3th line) Figure 47 Partial isplay Example Resizing Function supports resizing function (x/, x/4), which is performed when writing image data to GRAM The Page of 9 Version: 54

102 resizing function is enabled by setting a window address area and the RSZ bit which represents the resizing factor (x/, x/4) of image The resizing function allows the system to transfer the original-size image data into the GRAM with resized image data Original Image ata GRAM ata (,) (,) (,) (3,) (4,) (5,) (,) (,) (,) (3,) (4,) (5,) (,) (,) (,) (3,) (4,) (5,) (,3) (,3) (,3) (3,3) (4,3) (5,3) (,4) (,4) (,4) (3,4) (4,4) (5,4) (,5) (,5) (,5) (3,5) (4,5) (5,5) (,6) (,6) (,6) (3,6) (4,6) (5,6) (6,) (6,) (6,) (6,3) (6,4) (6,5) (6,6)? resizing (,) (,) (4,) (,) (,) (4,) (,4) (,4) (4,4) (6,) (6,) (6,4) (,6) (,6) (4,6) (6,6) Figure 48 ata transfer in resizing Original ata 4 Panel isplay RSZ='h 3 Write to GRAM Figure 49 Resizing Example Original Image Size (X Y) Resized Image Resolution / (RSZ= h) /4 (RSZ= h3) Page of 9 Version: 54

103 The RSZ bit sets the resizing factor of an image When setting a window address area in the internal GRAM, the GRAM window address area must fit the size of resized image The following example show the resizing setting X GRAM Address (X, Y) dx dx= (X-H)/N, H=X mod N dy= (Y-V)/N, V=Y mod N Y Original Image Size dy (X+dx-, Y+dy-) Original image data number in horizontal direction X Original image data number in Vertical direction Y Resizing Ration /N Resizing Setting RSZ N- Remainder pixels in horizontal direction RCH H Remainder pixels in vertical direction RCV V GRAM writing start address A (x, y) HSA x GRAM window setting HEA x+dx- VSA y VEA y+dy- Page of 9 Version: 54

104 Electrical Characteristics Absolute Maximum Ratings The absolute maximum rating is listed on following table When is used out of the absolute maximum ratings, the may be permanently damaged To use the within the following electrical characteristics limit is strongly recommended for normal operation If these electrical characteristic conditions are exceeded during normal operation, the will malfunction and cause poor reliability Item Symbol Unit Value Note Power supply voltage () VCC, IOVCC V -3 ~ + 46, Power supply voltage () VCI - AGN V -3 ~ + 46, 4 Power supply voltage () VH - AGN V -3 ~ + 6, 4 Power supply voltage () AGN -VCL V -3 ~ + 46 Power supply voltage () VH - VCL V -3 ~ + 9, 5 Power supply voltage () VGH - AGN V -3 ~ + 85, 5 Power supply voltage () AGN - VGL V -3 ~ + 85, 6 Input voltage Vt V -3 ~ VCC+ 3 Operating temperature Topr C -4 ~ , 9 Storage temperature Tstg C -55 ~ + 8, 9 Notes: VCC,GN must be maintained (High) (VCC = VCC) GN (Low), (High) IOVCC GN (Low) 3 Make sure (High) VCI GN (Low) 4 Make sure (High) VH ASS (Low) 5 Make sure (High) VH VCL (Low) 6 Make sure (High) VGH ASS (Low) 7 Make sure (High) ASS VGL (Low) 8 For die and wafer products, specified up to 85 C 9 This temperature specifications apply to the TCP package Page of 9 Version: 54

105 C Characteristics (VCC = 4 ~ 33V, IOVCC = 5 ~ 33V, Ta= -4 ~ 85 C) Item Symbol Unit Test Condition Min Typ Max Note Input high voltage V IH V VCC= 8 ~ 33V 8*IOVCC - IOVCC - Input low voltage V IL V VCC= 8 ~ 33V -3 - *IOVCC - Output high voltage() ( - Pins) Output low voltage ( - Pins) V OH V IOH = - ma 8*IOVCC V OL V IOVCC=5~33V VCC= 4 ~ 33V IOL = ma - - *IOVCC - I/O leakage current I LI µa Vin = ~ VCC Current consumption during normal operation (V CC GN ) Current consumption during standby mode (V CC GN ) LC riving Voltage ( VH-GN ) I OP µa VCC=8V, Ta=5 C, fosc = 376KHz ( Line) GRAM data = h - 6 (VCC) - - I ST µa VCC=8V, Ta=5 C VH V Output voltage deviation mv ispersion of the Average Output Voltage V mv Clock Characteristics VCC = 4 ~ 33V, IOVCC = 5 ~ 33V Item Symbol Test Condition Min Typ Max Unit External Clock Frequency fcp VCC = 4 ~ 33V KHz External Clock uty f uty VCC = 4 ~ 33V External Clock Rising Time Trcp VCC = 4 ~ 33V - - µs External Clock Falling Time Tfcp VCC = 4 ~ 33V - - µs RC oscillation clock f OSC Rf = KΩ, VCC = 8V KHz 4 Reset Timing Characteristics Reset Timing Characteristics (VCC = 8 ~ 33 V, IOVCC = 5 ~ 33 V) Item Symbol Unit Min Typ Max Reset low-level width t RES ms - - Reset rise time t rres µs - - t RES t rres nreset V IL V IH Page of 9 Version: 54

106 5 AC Characteristics 5 i8-system Interface Timing Characteristics Normal Write Mode (IOVCC = 5~33V, VCC=4~33V) Item Symbol Unit Min Typ Max Test Condition Write t CYCW ns Bus cycle time Read t CYCR ns Write low-level pulse width PW LW ns Write high-level pulse width PW HW ns Read low-level pulse width PW LR ns Read high-level pulse width PW HR ns - - Write / Read rise / fall time t WRr /t WRf ns Setup time Write ( RS to ncs, E/nWR ) - - t AS ns Read ( RS to ncs, RW/n ) Address hold time t AH ns Write data set up time t SW ns - - Write data hold time t H ns - - Read data delay time t R ns - - Read data hold time t HR ns RS V IH V IL V IH V IL t AS t AH ncs PW LW, PW LR PW HW, PW HR nwr, n V IH V IL V IL V IH V IH t WRf t WRr t CYCW, t CYCR t SW t H Write ata [:] V IH V IL Valid ata V IH V IL t R t HR Read ata [:] V OH V OL Valid ata V OH V OL Figure 5 i8-system Bus Timing Page of 9 Version: 54

107 5 Serial ata Transfer Interface Timing Characteristics (IOVCC= 533V and VCC=4~33V) Serial clock cycle time Item Symbol Unit Min Typ Max Test Condition Write ( received ) t SCYC ns - - Read ( transmitted ) t SCYC ns - - Serial clock high level Write ( received ) t SCH ns pulse width Read ( transmitted ) t SCH ns - - Serial clock low level Write ( received ) t SCL ns pulse width Read ( transmitted ) t SCL ns - - Serial clock rise / fall time t SCr, t SCf ns Chip select set up time t CSU ns - - Chip select hold time t CH ns Serial input data set up time t SISU ns - - Serial input data hold time t SIH ns - - Serial output data set up time t SO ns - - Serial output data hold time t SOH ns ncs V IL V IH t CSU t SCYC t SCH t SCr t SCf t SCL t CH SCL V IH V IL V IH V IL V IH V IL V IH V IL t SISU t SIH SI V IH V IL Input ata V IH V IL Input ata t SO SO V OH V OH V OL V OL Output ata Output ata V OH V OL Figure 5 SPI System Bus Timing 53 RGB Interface Timing Characteristics 8/-bit Bus RGB Interface Mode (IOVCC = 5 ~ 33V, VCC=4~33V) Item Symbol Unit Min Typ Max Test Condition VSYNC/HSYNC setup time t SYNCS ns ENABLE setup time t ENS ns ENABLE hold time t ENH ns P ata setup time t PS ns P ata hold time t PH ns OTCLK high-level pulse width PH ns OTCLK low-level pulse width PL ns OTCLK cycle time t CYC ns OTCLK, VSYNC, HSYNC, rise/fall time t rghr, t rghf ns Page of 9 Version: 54

108 6-bit Bus RGB Interface Mode (IOVCC = 5 ~ 33V, VCC=4~33V) Item Symbol Unit Min Typ Max Test Condition VSYNC/HSYNC setup time t SYNCS ns ENABLE setup time t ENS ns ENABLE hold time t ENH ns P ata setup time t PS ns P ata hold time t PH ns OTCLK high-level pulse width PH ns OTCLK low-level pulse width PL ns OTCLK cycle time t CYC ns OTCLK, VSYNC, HSYNC, rise/fall time t rghr, t rghf ns t rgbf t rgbr t SYNCS HSYNC VSYNC V IH V IL tase t ENS t ENH HSYNC VSYNC V IH V IL V IH V IL t t rgbf PL rgbr PH V IH V IL V IL V IH V IH t CYC t PS t PH V IH V IL Write ata V IH V IL Figure5 RGB Interface Timing Page 8 of 9 Version: 54

109 Revision History a-si TFT LC Single Chip river Version No ate Page escription V 6/4/ New Created V4 6// Modify the SPI interface V44 6// Modify the OSC description section, The internal resistor is used in the default setting V45 6//7 Modify the VCOMR description Let this pin as open when it s unused The unused interface pins are shorted to GN 3 ithering function removed V46 7//3 Modify the VCCUM, UMMYR~, TEST3, TEST4, TSC pins connection V47 7/3/ Add the thickness of chip by customer order V49 7/5/9 Modify /9/8 bit System interface type error V5 7/6/ Modify VPP3 pins connection to GN or floating V5 7/7/3 Modify the diode connection of VGL pin connection Modify chip size(including scribe line) um x 67um V53 7//3 Modify Au BUMP size : umxum 3 Modify Au BUMP width was um not um V54 7//3 95 Modify the display off sequence V55 8// Modify VCC current elete LC power supply current 3 elete drive output delay time Page 9 of 9 Version: 54