Bi-Annual Report 2008/2009 Solid-State Electronics Department

Transcription

1 Bi-Annual Report 2008/2009 Solid-State Electronics Department Prof.Dr.rer.nat. F.J.Tegude Universität Duisburg-Essen Fakultät für Ingenieurwissenschaften Institut für Technologien der Informationstechnik Halbleitertechnik/Halbleitertechnologie Lotharstrasse 55 / ZHO D Duisburg Germany Tel.: ++49 (0) (Secr.) Fax: ++49 (0) www: Editors: Dr.-Ing. Werner Prost Dr.-Ing. Wolfgang Brockerhoff Halbleitertechnik/ Halbleitertechnologie

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3 Bi-Annual Report 2008/ Solid-State Electronics Department Table of Contents 1 Preface Members of the Department Teaching Activities Lectures and Laboratory Exercises Student Projects - Projektarbeiten Student Reports - Studienarbeiten Diploma Thesis - Diplomarbeiten Doctor Thesis - Dissertationen Seminar on Semiconductor Electronics Research Activities Epitaxial Growth and Materials Growth of p-type Doped GaAs Nanowires Using DEZn I. Regolin, A.Lysov Determination of p-type GaAs Nanowire Dopant Density C. Gutsche, I. Regolin Axial pn-junctions in Vapour-Liquid-Solid Grown GaAs Nanowires by MOVPE using DEZn and TESn I. Regolin, C. Gutsche, A. Lysov Electrical Characterisation of MOVPE Grown n- and pn-gaas Nanowires C. Gutsche, I. Regolin, A. Lysov Growth and Doping of InP Nanowires A. Lysov, C. Gutsche, K. Blekker Au-Assited MOVPE of GaN Nanowires in a Close Coupled Showerhead Reactor I. Regolin, H. Behmenburg, J. P. Ahl Device and Circuit Processing Optimized RTD-Design for Application in Microwave Frequency Generation Circuits B. Münstermann, R. Geitmann Scalable High-Current Density RTD with Low Series Resistance A. Tchegho, B. Münstermann, R. Geitmann Low-Power RTD-based-VCO for Ka-Band Application B. Münstermann, Kai Blekker Fabrication of Nanowire Based Top-Contacted pn-diodes A. Lysov... 56

4 Bi-Annual Report 2008/ Solid-State Electronics Department Layout and Technology for Coplanar Contact Pattern of Nanowire Field-Effect Transistors B. Li, K. Blekker, B. Münstermann InAs Nanowire MISFET with Al2O3 Gate Dielectric K. Blekker, W. Prost, T. Mizutani Fabrication of Nanowire-Devices Using Field-Assisted Self Assembly O. Benner, K. Blekker n-zno Nanowire Field Effect Transistors K. Blekker, M. Lange, M. Lorenza, M. Grundmann, R. Richter Device and Circuit Simulation, Measurement and Modelling RF Measurement of High Frequency pin-photodetectors G. Keller, I. Nannen, A. Poloczek Optical-Detector-Circuitry Using Staggered pin-photodiodes for All-Optical- Input Gate A. Poloczek, K. Blekker, H. Barbknecht PINIP / NIPIN Layer Sequences and Crosstalk Properties of the Wavelength- Selective Detector A. Poloczek, B. Münstermann Physical Simulation of InP-based Field-Effect Transistors Using Silvaco Atlas B. Betting, K. Blekker Modelling of InP Heterostructure Bipolar Transistors (HBT) for Operation in Monolithic Microwave Integrated Circuits G. Keller, B. Münstermann Development of a Transimpedance Amplifier with Balanced Optical Input I. Nannen Simulation and Investigation of Opto-Electronic Receiver Circuits Ö. Kahraman, I. Nannen Modeling of Resonant Tunneling Diodes Y. Fu, A. Tchegho, B. Münstermann, W. Prost Investigation of n-n-heterostructure Diodes D. Zhang, W. Prost, B. Münstermann, A. Poloczek, R. Geitmann, S. Köppen, A. Eckhardt Unipolar Heterostructure Diode for Small Signal Rrectification and DC Power Supply in RFID Transponders B. Münstermann, A. Poloczek, W. Prost, T. Feldengut, R. Geitmann, A. Eckhardt High Frequency Measurements on InAs Nanowire Field-Effect Transistors K. Blekker, B. Münstermann

5 Bi-Annual Report 2008/ Solid-State Electronics Department On the Temporal Behavior of DC and RF Characteristics of InAs Nanowire MISFET with SiN x Gate Dielectric Y. Otsuhata, K. Blekker, T. Waho, W. Prost Conference Contributions Publications Research Projects Other Activities rd Nanowire Growth Workshop 2008 W. Prost Visiting Report: Prof. Takao Waho: A Nanoelectronic Circuit Designer from Sophia University, Tokyo W. Prost Schueler-Ingenieur-Akademie/Junior-Ingenieur-Akademie I. Nannen, W. Brockerhoff Guide to the Solid-State Electronics Department

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7 Annual Report 2008/ Solid-State Electronics Department 1 1 Preface This report presents the teaching and research activities of the Solid State Electronics Department (Fachgebiet Halbleitertechnik/Halbleitertechnologie) during the years 2008 and Regarding teaching activities two completely new lectures have been prepared in the frame of the study course Nano Engineering : Technology of Nanostructures I (Nanostrukturierung I) and Nanoelectronics (Nanoelektronik). For many years now our research work covers the areas of 1) Epitaxial Growth and Materials, 2) Device and Circuit Processing, 3) Device and Circuit Simulation, Measurement and Modelling, and 4) Nanoelectronics. The Nanoelectronics and Epitaxial Growth fields could significantly be strengthened by the acquisition of the NaSoL project, addressing the investigation of semiconductor nanowires for solar cells and light emitting diodes. Within this project a new Aixtron MOVPE system for III-Nitrides will be installed in April 2010 to support nanowire preparation for white light LEDs. NaSoL is funded by the NanoMikro+Werkstoffe.NRW initiative of North Rhine Westphalia and started in July In our nanowire work the controlled p- and n-doping of nanowires during and after growth was a major activity, and we successfully demonstrated axial core-shell GaAs-pn junctions with diode characteristics for the first time. Together with our NaSoL project partner Aixtron we have grown first GaN nanowires using Au layers as growth seed elements, too. Significant progress also was achieved for nanowire contact and device processing. Here technology development for top contacts on as grown nanowires and electric field assisted nanowire self assembly should be pointed out. In the field of resonant tunnelling devices (RTD), we significantly improved device characteristics and the integration with HBT, HFET and photodetctors towards MMICs and OEICs. Let me finally thank all friends and partners for their support and fruitful cooperation, and all members and students of the Solid State Electronics Department for their excellent efforts and contributions, which is indispensable for future successful work. Duisburg, March 2010 Prof. Dr. rer. nat. F.-J. Tegude

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9 Bi-Annual Report 2008/ Solid-State Electronics Department 3 2 Members and Guests of the Department 379- office head of the department Prof. Dr.rer.nat. Franz-Josef Tegude LT 207 franz.tegude@uni-due.de secretary Dagmar Birke LT 206 dagmar.birke@uni-due.de scientific staff Dipl.-Ing. Kai Blekker LT 106 kai.blekker@uni-due.de Dr.-Ing. Wolfgang Brockerhoff (AOR) LT 205 wolfgang.brockerhoff@uni-due.de Dipl.-Ing. Christoph Gutsche LT 203 christoph.gutsche@uni-due.de Dipl.-Ing. Gregor Keller since 12/ LT 203 gregor.keller@uni-due.de Dipl.-Phys. Andrey Lysov LT 203 andrey.lysov@uni-due.de Dipl.-Ing. Andreas Matiss until 03/08 Dipl.-Ing. Benjamin Münstermann LT 204 benjamin.muenstermann@uni-due.de Dipl.-Ing. Ingo Nannen LT 204 ingo.nannen@uni-due.de Dipl.-Ing. Artur Poloczek LT 104 artur.poloczek@uni-due.de Dr.-Ing. Werner Prost LT 205 werner.prost@uni-due.de Dipl.-Ing. Ingo Regolin LT 104 ingo.regolin@uni-due.de Dipl.-Ing. Anselme Tchegho LT 204 anselme.tchegho@uni-due.de technical staff Udo Doerk LT 202 udo.doerk@uni-due.de Dipl.-Ing. Ralf Geitmann LT 202 ralf.geitmann@uni-due.de Dipl.-Ing. Wolfgang Molls LT 201 wolfgang.molls@uni-due.de Andrea Merz LT 104 andrea.osinski@uni-due.de Ing. (grad.) Reimund Tilders LT 201 reimund.tilders@uni-due.de apprentices Alice Eckhardt since 08/ LT 104 alice.eckhardt@uni-due.de Svenja Köppen since 08/ LT 104 svenja.koeppen@uni-due.de Maximilian Keiser since 08/ LT 105 maximilian.keiser@uni-due.de

10 4 Bi-Annual Report 2008/ Solid-State Electronics Department students Benner, Oliver Li, Bo Chakroun, Faten since Mao, Xin Chen, Yun Richter, René since Denker, Joachim Troost, Aaron since Gronert, Daniel Wildmann, Manuel Javarone, Dino since Xue, Yan Keller, Gregor Guests of the department: Prof. Takao Waho, Sophia University, Tokyo, Japan

11 Bi-Annual Report 2008/ Solid-State Electronics Department 5 3 Teaching Activities 3.1 Lectures and Laboratory Exercises Lectures and exercises Schedule International Studies in Engineering (ISE) Electrical and Electronic Engineering Nanoengineering. B.Sc. M.Sc B.Sc. M.Sc B.Sc. M.Sc. Solid-State Electronics Festkörperelektronik Basic Electronic Devices Grundlagen Elektronischer Bauelemente 4 th sem. (EEE) 5 th sem. (EEE) 2 nd sem. 4 th sem. 3 rd sem. 5 th sem. Basic Electronic Circuits Grundlagen Elektronischer Schaltungen 2 nd sem. Fundamentals of Electronics Grundlagen der Elektronik Basic FET- and Bipolar Transistor Circuits Grundschaltungen der FET und Bipolarelektronik Components for Wireless Communication Komponenten für die drahtlose Kommunikation Technology of Nanostructures Nanostrukturierung Nanoelectronics Nanoelektronik Semiconductor Microelectronics Technology 1/ III-V Technologies and Components 1/ Halbleitertechnologie 1 5 th sem. (CSCE, ACE) optional 2 nd sem. 2 nd sem. 1 st sem. 3 rd sem.

12 6 Bi-Annual Report 2008/ Solid-State Electronics Department Laboratory exercises Schedule diploma course International Studies in Engineering (ISE) Electrical and Electronic Eng. Nanoengineering. B.Sc. M.Sc B.Sc. M.Sc B.Sc. M.Sc. Introduction to Operational Amplifiers Praktikum Operationsverstärker Semiconductor Technology 2 Halbleitertechnologie 2 Semiconductor Technology Praktikum Halbleitertechnologie Basic Electronic Circuits Praktikum Grundlagen Elektronischer Schaltungen Electronics and RF Praktikum Grundlagen Elektronischer und Hochfrequenzschaltungen Basic FET- and Bipolar Transistor Circuits Grundschaltungen der FET- und Bipolarelektronik 2 nd sem. optional optional 5 th sem. 2 nd sem. 2 nd sem. Seminars and Colloquia Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik Seminar on Epitaxial Problems 6

13 Bi-Annual Report 2008/ Solid-State Electronics Department 7 Lectures and Exercises: Solid-State Electronics Festkörperelektronik Starting with basics of Quantum Physics, i.e. Heisenberg s uncertainty relations, Schroedinger equation, atomic models, this course gives an introduction to the electronic properties of solid-state materials. Using Schroedinger s equation the simple Kronig-Penney bandstructure model is developed to distinguish between isolators, metals and semiconductors. The carrier statistics and densities in these materails for electrons and holes is develoepd and, together with transport properties especially in semiconductors (microscopic model of the mobility), the electrical conductivity is evaluated. Poisson and continuity equations are derived ending up with the fundamentals of the pn-junction and MOS-system. Basic Electronic Devices / Fundamentals of Electronics Grundlagen Elektronischer Bauelemente / Grundlagen der Elektronik Based on the solid-state electronics fundamentals MOS-capacitors and charge-coupled devices (CCD) are treated. Subsequently, the basics of field-effect transistors (MOSFET, junction FET (MESFET, JFET) and heterostructure-fet (HFET)) and bipolar devices (pn-diode, npn- and pnp-bipolar transistors, tunnel diodes and thyristors) are covered and the DC-characteristics of these devices are derived. Basic Electronic Circuits / Basic FET- and Bipolar Transistor Circuits Grundlagen Elektronischer Schaltungen / Grundschaltungen der FET- und Bipolarelektronik Based on the small-signal analysis of electronic devices like diodes, field-effect transistors (FET) and bipolar transistors fundamental methods to calculate and design komplex electronic circuits are introduced and applied. Basic circuits and their characteristics are analysed and discussed in detail. Both, analog and digital circuits are treated. Components for Wireless Communications Komponenten für die drahtlose Kommunikation This lecture introduces the fundamentals of electronic circuits for wireless communication systems. Topics are fundamentals of wireless systems and architectures and the principles and technology of modern active electronic bipolar and FET components; silicon transistor technology as well as very high frequency heterojunction tecnology will be covered. Circuit topics range from oscillators to amplifiers and mixers where we will investigate linear and non-linear properties and match, gain, power, stability and noise.

14 8 Bi-Annual Report 2008/ Solid-State Electronics Department Semiconductor Microelectronics 1 Halbleitertechnologie 1 The semiconductor microelectronics technology lectures are devoted to III/V-semiconductor heterostructures for high speed electronic devices. The process steps from crystal growth to circuit fabrication are discussed. The first semester is focused on heterostructure material issues. Modern growth techniques like molecular beam epitaxy (MBE) and metal-organic vapour-phase epitaxy (MOVPE) are discussed in terms atomic layer control of thickness, composition, and doping. High Resolution X-ray diffraction, photoluminescence, and ellipsometry are explained for nondestructive material assessment in the mono-layer scale. The second semester is devoted to microelectronic fabrication techniques for high speed (f 100 GHz) devices and circuits. The lateral and vertical processing of epitaxial films, insulating layers, and metallizations are presented for high performance monolithic high speed analog and digital integrated circuits. Technology of Nanostructures Nanostrukturierung The lecture should improve the knowledge on the technological procedures to fabricate nanostructured materials and components as well as the accompanying analysis methods with help of actual examples from the electronic device production. This contains: Modern growth technologies for layer deposition in the range of mono-atom-layers like metal-organic vapour phase epitaxy (MOVPE) and molecular beam epitaxy (MBE), with regard to composition, control of the layer thickness and doping. Use of self organization mechanisms and template processes. Advanced high-resolution lithography procedures for the production of nano-scaled structures (electron beam, X-ray as well as scanning force lithography). Micro- and nano-electronic fabrication techniques for electronic and opto-electronic nanocomponents, e.g. for high frequency applications. Lateral and vertical processing of epitaxial films, insulating layers and metallisations up to monolithic integrated nano-electronic circuits. Non destructive analysis of nano-structures and devices by high-resolution X-ray difraction and by the use of the interaction of electron probes with the materials. Analysis methods with mechanical probes (scanning tunneling and the scanning force microscope) 8

15 Bi-Annual Report 2008/ Solid-State Electronics Department 9 Nanoelectronics Nanoelektronik The lecture treats electronic aspects of the nanotechnology and differs from the areas nano-photonic and nano-magnetism. It starts with a classification of suitable materials and nano-structures and briefly introduces fabrication techniques. The Boltzmann transport equation, transport mechanisms, in particular tunnel and ballistic transport, are treated. Transistors with two-dimensional electron gas as channel (2DEG), resonance tunnel diodes and transistors, single Electron transistors, Coulomb blockade as well as electromechanical nano-elements on semiconductor and carbon base are presented and discussed. Simple basic functions as examples for a nano-circuit technology conclude the lecture. Laboratory exercises Introduction to Operational Amplifiers Praktikum Operationsverstärker The aim of this course is the understanding of the basic principles and the characteristics of operational amplifiers (OpAmps). The laboratory exercises demonstrate their applicability in electronic circuits enabling the students to an independent design and understanding of complex circuits. Starting with the measurement and interpretation of the most important characteristic parameters of OpAmps, circuits like adders and multipliers, amplifiers and active filters are intensively calculated and investigated. Oscillators and generators are designed and measured. Semiconductor Technology 2 Halbleitertechnologie 2 Electronic devices and circuits, based on III-V semiconductors, are fabricated in the clean room facilites under supervision. Produced devices are electrically characterised Semiconductor Technology Praktikum Halbleitertechnologie The laboratory covers various areas of semiconductor technology, which are under investigation in the Department of Engineering Sciences at the University of Duisburg-Essen. It offers topics from optoelectronics, silicon semiconductor technology, the technology for high-frequency devices made from III-V semiconductors and nanotechnology for quantum devices. The focus of the experiments lays on the manufacturing and technology-based characterization of components, making clear the relationship between production parameters and components. Detailed descriptions are available for the individual experiments, within which the necessary fundamentals are recapitulated.

16 10 Bi-Annual Report 2008/ Solid-State Electronics Department Comprehension questions and tasks are provided, to be solved as preparation at home. The labs include a colloquium to audit, the experimental procedure and the minutes. Experiments of the Optoelectronics Dept. (OE) Photovoltaics Packaging Experiments of the Solid-State Electronics Dept. (HLT) Fabrication of semiconductor test structures Characterization of the manufactured test structures Experiments of the Dept. of Electrical Engineering and Information Technology (WET) Nanolithography for quantum nano-devices Analysis of nanostructured devices Experiments of the Dept. of Electronic Devices and Circuits (EBS) Characterization of MOS capacitors and transistors metrology in semiconductor manufacturing Electronics and RF Praktikum Grundlagen Elektronischer und Hochfrequenzschaltungen The lab combines topics of RF-and Microwave Engineering with topics from Solid State Electronics for RF- and Microwave applications. The lab experiments are supported by extensive material on the theoretical fundamentals and by questions and tasks to be prepared by the students before the lab. The part on Electronics is organized by Fachgebiet Halbleietertechnologie and incorporates experiments on Schottky diode capacitance, switching behaviour of bipolar transistors and the dc current-voltage characteristic of field effect transistors. The part on RF technology is organized by Fachgebiet Hochfrequenztechnik and provides 12 experiments which cover the main theoretical concepts taught in the MRFT course. Basic Electronic Circuits / Basic FET- and Bipolar Transistor Circuits Praktikum Grundlagen Elektronischer Schaltungen / Grundschaltungen der FET- und Bipolarelektronik The lab is a supplement of the lecture "Basic FET and Bipolar Circuits" to intensify the understanding of the analysis of electronic circuits. 10

17 Bi-Annual Report 2008/ Solid-State Electronics Department 11 It consits of three practical exercises: - the investigation of simple digital circuits - the switching behaviour of bipolar transistors and - the analysis of amplifier circuits using a circuit simulator Seminars and Colloquia Seminar on Semiconductor Electronics Probleme der modernen Halbleiterphysik Within this seminar actual topics of the semiconductor electronics are discussed. Students, but also members of the department, report about their own work. Seminar on Epitaxial Problems Problems of the epitaxial growth of semiconductor structures are analysed, results are interpreted and future trends are discussed.

18 12 Bi-Annual Report 2008/2009- Solid-State Electronics Department 3.2 Student Projects (Projektarbeiten) 1. MEHMET SANLIALP, TALIP DEMIRCAN, GÖKHAN MENTES, Untersuchung einfacher Verstärkerschaltungen mit Bipolartransistoren (submitted : ) 2. FATAOU BOURAIMA, XUPU TANG, OCHI QUAJDI Untersuchung passiver Bauelemente für den Einsatz in monolithisch integrierten Mikrowellenschaltungen (MMIC) (submitted : ) 3. GENNADI KAUFMANN, TIM KÖNINGS Elektrische Charakterisierung von Nanodrähten (submitted : ) 4. TEODOR PENCHEV, Erstellung von Animationen mit dem Softwaretool 3dsMax (submitted : ) 3.3 Student Reports (Studienarbeiten) 1. LI BO Layout und Technologie von Koplanaren Kontakten für Nanodraht- Feldeffekttransistoren (submitted: ) 2. GREGOR KELLER Aufbau eines optischen Hochfrequenzmessplatzes (submitted: ) 3. BJÖRN BETTING Simulation von Feldeffekttransistoren des Typs HFET und MIS-HFET (submitted: ) 4. DUDU ZHANG Untersuchung von n-n-heterostrukturdioden (submitted: )

19 Bi-Annual Report 2008/2009- Solid-State Electronics Department BINGDONG TIAN Herstellung von vorstrukturierten MOVPE-Wachstumstemplaten mittels Nanosphärenlithografie (submitted: ) 6. YIYAO FU Modellbildung von Resonanztunneldioden (submitted: ) 7. OLIVER BENNER Herstellung von Nanodraht-Bauelementen mittels feldunterstützter Selbstjustage (submitted: ) 3.4 Diploma Thesis (Diplomarbeiten) 1. ÖZGÜR KAHRAMAN : Simulation und Untersuchung von opto-elektronischen Empfängerschaltungen (submitted: ) 2. GREGOR KELLER: Modellbildung für InP Heterostruktur-Bipolar-Transistoren (HBT) für den Einsatz in monolithisch integrierten Mikrowellenschaltungen (submitted : ) 3.5 Doctor Thesis (Dissertation) 1. ANDREAS MATISS Entwurf und Realisierung neuartiger Schaltungskonzepte mit Resonanztunneldioden (date of examination: ) 2. JÖRN DRIESEN Design von schnellen Heterostruktur-Transistoren für den Einsatz in Schaltungen mit Resonanz- Tunnel-Dioden (date of examination: ) 3. STEFAN NEUMANN Ein Beitrag zur Epitaxie von elektro-optischen Doppel-Heterostruktur-Bauelementen (date of examination: )

20 14 Bi-Annual Report 2008/ Solid-State Electronics Department 3.6 Seminar on Semiconductor Electronics BENJAMIN MÜNSTERMANN, REPORT ON THE DIPLOMA THESIS: 'Entwicklung eines RTD/HBT Oszillators für Ku- und Ka-Band Anwendungen' GREGOR KELLER, REPORT ON THE STUDENT THESIS: 'Aufbau eines optischen Hochfrequenzmessplatzes' LI BO, REPORT ON THE STUDENT THESIS: 'Layout und Technologie von Koplanaren Kontakten für Nanodraht- Feldeffekttransistoren' INGO NANNEN, REPORT ON THE PROJECT: 'Components for synchronous optical quadrature phase shift keyingtransmission' (SynQPSK) ANDREY LYSOV, REPORT ON STATE-OF-THE-ART OF 'Optische Charakterisierung von Nanodrähten' CHRISTOPH GUTSCHE, KAI BLEKKER, REPORT ON THE CONFERENCE: 'Nanoelectronic Days 2008' (ND), Aachen, Germany, ARTUR POLOCZEK, FRANZ-JOSEF TEGUDE, REPORT ON THE CONFERENCE: 'IEEE Int. Conf. on InP and Related Materials 2008' (IPRM), Versailles, France, INGO REGOLIN, REPORT ON STATE-OF-THE-ART OF 'Dotierung von Nanodrähten während des VLS-Wachstums' ANDREY LYSOV, REPORT ON THE CONFERENCE: 'Int. Conf. on Metalorganic Vapour Phase Epitaxy (MOVPE) -XIV' (IC MOVPE), Metz, France, WERNER PROST, REPORT ON THE CONFERENCE: '66th Annual Device Research Conference' (DRC), Santa Barbara, CA, USA, BENJAMIN MÜNSTERMANN, REPORT ON THE CONFERENCE: Europ. Microwave Week / GAAS, EuMC, ECWT 2008 (EuMW), Amsterdam, The Netherlands, WERNER PROST, REPORT ON THE PROJECT: "Nanowire/CMOS"

21 Bi-Annual Report 2008/ Solid-State Electronics Department INGO REGOLIN, REPORT ON THE CONFERENCE: DGKK Workshop, Braunschweig, Germany, M. WILDMANN, REPORT ON "Fachpraktikum bei der Fa. Cato" INGO NANNEN, "Opto-Elektronischer Empfängerverstärker mit balanciertem Eingang" N. SZABO, HMI BERLIN:, "MOCVD-präparierte III-V-Materialien für die Photovoltaik" BJÖRN BETTING, REPORT ON THE STUDENT THESIS: 'Simulation von Feldeffekttransistoren des Typs HFET und MIS-HFET' FRANZ-JOSEF TEGUDE, "NaSoL: Halbleiter-Nanodrähte für Solarzellen und Leuchtdioden: Projekt-Konzept, Ziele und Arbeitsprogramm" ANDREY LYSOV, "NaSoL - GaInN-Epitaxie und -Kristallstruktur" WERNER PROST, "NaSoL - Bauelement-Technologie" DUDU ZHANG, REPORT ON THE STUDENT THESIS: 'Untersuchung von n-n-heterostrukturdioden' FRANZ-JOSEF TEGUDE, REPORT ON THE CONFERENCE: IEEE Int. Conf. on InP and Related Materials (IPRM), Newport Beach, CA, USA, F.-J. TEGUDE, REPORT ON THE CONFERENCE: DPG Frühjahrstagung, Dresden, Germany, BINGDONG TIAN, REPORT ON THE STUDENT THESIS: 'Herstellung von vorstrukturierten MOVPE-Wachstumstemplaten mittels Nanosphärenlithografie' INGO REGOLIN, REPORT ON THE CONFERENCE: Europ. Workshop on MOVPE and Rel. Growth Techniques (EW MOVPE), Ulm, Germany, Ingo Regolin, Report on JEOL Workshop über Rasterelektronenmikroskopie YIYAO FU, REPORT ON THE STUDENT THESIS: "Modellbildung von Resonanztunneldioden"

22 16 Bi-Annual Report 2008/ Solid-State Electronics Department WERNER PROST, REPORT ON THE CONFERENCE: "Topical Workshop on Heterostructure Microelectronics" (TWHM), Nagano, Japan, ANDREY LYSOV, REPORT ON State of the art of the Photoluminescence Measurement Set-Up GREGOR KELLER, REPORT ON THE DIPLOMA THESIS: "Modellbildung von InP Heterostruktur-Bipolar-Transistoren (HBT) für den Einsatz in monolithisch integrierten Mikrowellenschaltungen"

23 Bi-Annual Report 2008/ Solid-State Electronics Department 17 4 Research Activities 4.1 Materials, Growth and Characterization

24 18 Bi-Annual Report 2008/ Solid-State Electronics Department Growth of p-type doped GaAs Nanowires using DEZn Scientist: I. Regolin, A. Lysov Introduction III-V semiconductor nanowires have attracted great research interest due to their superior electrical and optoelectronic properties for future high performance nanoscaled devices. While the vapourliquid-solid (VLS) growth of elementary semiconductors like Si is widely understood [1], a complete model is still pending for VLS growth with more species like group-iii and group-v elements in III/V nanowires [2]. Many fundamental questions, especially about the doping mechanism, remain open up to now. In general, there are only a very few publications, describing initial doping results of different III/V nanowires. Successful n- and p- type doping of GaN has been realised in [3]. With hydrogen sulfide (H 2 S) as an MOVPE dopant precursor n-type sulfur doping in InP nanowires was demonstrated [4] including a pn-junction delivering on-currents in the na range. Moreover, easy and precise measurement techniques in order to determine the carrier concentration inside the nanowires are still lacking. We report on controlled p-type doping of GaAs nanowires using diethyl zinc (DEZn) as precursor material during the growth. Since the nanowires were grown untapered, we can exclude the formation of an additive shell around the VLS grown nanowire. To clarify, if the Zn is incorporated via VLS mechanism, we also investigated the possible doping via in-situ MOVPE diffusion of diethyl zinc during and after wire growth. Experimental Setup Monodisperse as well as polydisperse Au nanoparticles were deposited as growth seeds prior to growth. Monodisperse nanoparticles with a diameter of 150 nm were taken from a colloidal solution. Polydisperse nanoparticles were produced by annealing of a thin evaporated Au layer of nominally 2.5 nm thickness. The anneal step was carried out at 600 C for 10 minutes under group-v overpressure and results in nanoparticles with diameters from 30 nm to some 100 nm. Nanowires were grown by metal-organic vapour-phase epitaxy (MOVPE) on (111)B GaAs substrates at a total pressure of 50 mbar. Trimethylgallium (TMGa) and Tertiarybutylarsine (TBAs) were used as group-iii and V precursor, respectively. The total gas flow of 3.4 l/min was provided by N 2 as carrier gas, while H 2 was used for the bubblers. The growth start was initiated at 450 C for 3 minutes. After adjusting the final growth temperature of 400 C the growth was continued with an additional supply of Zn for 20 minutes. Therefore, the DEZn/TMGa (II/III) ratio was varied between and 0.008, while the V/III ratio was kept constant at 2.5. In order to study the effect of Zn diffusion, nominally undoped nanowires were exposed to DEZn ambient for 20 minutes at 400 C after TMGa was switched off. The nanowires were inspected by scanning electron microscopy (LEO 1530). Electrical results were obtained with standard DC-measurements setup. Therefore the as grown structures were transferred to special prepared carriers and finally contacted by electron beam lithography (E-Beam) [5].

25 Materials, Growth and Characterization 19 Results Figure 1 a,b show scanning electron microscopy micrographs of GaAs nanowires. The stumps of the nanowires were grown at 450 C in order to reduce structural defects and frequent wire kinking during the initial nucleation. Next the growth temperature is reduced to 400 C which suppresses the conventional layer growth on the side facets leading to a very high aspect ratio up to g r,vls /g r,vs > 1000 for the upper part of the wire. The wire given in Fig. 1a is grown from a colloidal Au seed nanoparticle with 150 nm diameter and is non intentionally doped. This sample is used as a reference for further doping experiments. Nanowires grown from polydisperse seed particles, formed by annealing of a 2.5 nm thick Au layer, are depicted in Fig. 1b. This approach provides a wide range of wire diameters. 400 C a 400 nm 450 C b 1 µm Fig. 1 Scanning electron micrographs of GaAs nanowires grown on GaAs (111)B substrate at 400 C with an initial stump grown at 450 C (a) from colloidal Au nanoparticles with 75 nm radius and (b) grown with a II/III ratio of from polydisperse seed particles formed by annealing of a 2.5 nm Au layer. In the first series of experiments we studied the effect of DEZn flow on the properties of the nanowire. Fig. 2 shows a series of GaAs nanowires grown under different supply of zinc. We observed good structural properties up to a II/III ratio of (Fig. 2a), while at higher II/III ratio wire kinking (Fig. 2b) and at even higher (II/III = 0.067) a seed splitting was observed (Fig 2c). The number of structural defects increased with wire radius and II/III ratio, respectively. However, below a II/III ratio of 0.004, nanowires up to 350 nm are grown completely strait and therefore best suitable for further investigations. Most of the wires grown at II/III = show kinking effects, enabling a limited analysis.

26 20 Bi-Annual Report 2008/ Solid-State Electronics Department (II/III = 0.004) (II/III = 0.007) (II/III = 0.067) a) 200 nm b) 200 nm c) 200 nm Fig. 2 Scanning electron micrographs of p-gaas nanowires grown on GaAs (111)B substrate from colloidal Au nanoparticles with 75 nm radius at different II/III ratios (a) 0.004, (b) and (c) To enable electrical characterization, the structures were scratched from the substrate and solved into isopropanol. After that the solution was dropped onto s.i. GaAs substrate including an additional 250 nm SiN x insulation layer and prefabricated contact unit cells. Using the E-beam lithography, positions of the deposited nanowires could be verified, what enables the connection to the contact pad structures in combination with standard technology processes. I/V measurements revealed that the conductance of GaAs nanowires increased about 5 orders of magnitude compared to nominally undoped wires. In addition a almost linear behaviour between DEZn flow and Zn concentration was observed in the investigated range [5]. In our experiments we were able to adjust the Zn incorporation from cm -3 down to cm -3. Since the DEZn precursor supply was about hundred times lower then normally used for the doping of conventional layers, Zn has to be incorporated very effective at the used growth temperature of 400 C. The realized doping effect might be related to a diffusion of Zn via the side walls or due transport via the Au seed particle. A possible side wall diffusion effect attributed to DEZn in the gas phase was studied using a nominally undoped wires which were exposed to DEZn under TBAs overpressure at T Diff = 400 C for 20 minutes, reveals that their conductance is not affected. Even at higher temperatures like 500 C, no effective increase of the wire conductivity could be observed. Therefore, we conclude that the incorporation of the doping atoms happens via the Au seed particle or via the seed/wire interface. Conclusion In summary, controllable p-type doping during the VLS growth of GaAs nanowires using diethyl zinc as doping precursor was demonstrated. Tapering free structures as well as diffusion experiments reveal, that the Zn incorporation was driven by the VLS mechanism. The doping concentration in the nanowires, depending on the DEZn flow, was estimated by mobility vs. carrier concentration model, taking surface depletion due to Fermi-level pinning into account [5]. It could be adjusted by varying the II/III ratio in a wide range from cm -3 down to cm -3. A linear dependence was observed in the investigated range. Stronger kinking of the nanowires with increasing diethyl zinc flow giving evidence that Zn is incorporated via VLS mechanism but also indicates an upper limit of p-type doping. Further investigations should provide more detailed information about the deferral incorporation of the doping species into the wire crystal.

27 Materials, Growth and Characterization 21 The described route for the controlled doping of nanowires is of general interest for all compound semiconductor nanowires. It points out fundamental aspects of growth and doping, respectively, which are the essential challenges for future applications in optoelctronics and sensor technologies. Acknowledgement This work was supported by Sonderforschungsbereich 445 Nanoparticles from the gas-phase References [1] E.I. Givargizov; J. Crystal Growth 31, pp , 1975 [2] K. A. Dick, K. Deppert, L. S. Karlson, L. R. Wallenberg, L. Samuelson, W. Seifert; Adv. Funct. Mat. 15, pp , 2005 [3] Z. Zhong, F. Qian, D. Wang, C. M. Lieber, Nano Lett. 3, No. 3, pp , 2003 [4] E.D. Minot, F. Kelkensberg, M. van Kouwen, J.A. van Dam, L.P. Kouwenhoven, V. Zwiller, M.T. Borgstrom, O. Wunnicke, M.A. Verheijen, E.P.A.M Bakkers; Nano Lett. 7, pp , 2007 [5] C. Gutsche, I. Regolin, K. Blekker, A. Lysov, W. Prost, and F. -J. Tegude; Journal of Applied Physics, accepted in 2008

28 22 Bi-Annual Report 2008/ Solid-State Electronics Department Determination of p-type GaAs nanowire dopant density Scientist: C. Gutsche, I. Regolin Introduction During the last decade, growth and possible device applications of semiconductor nanowires have been researched intensely. Nevertheless one of the most complex challences remains the determination of dopant densities within nanowires grown via the vapor-liquid-solid (VLS) growth mode. Common methods like hall measurements, already established from microelctronic applications, are not suited for nanwoires. Therefore another approach is to investigate the conductivity and transistor data in terms of dopant density [1]. For GaAs and other semiconductor nanowires a surface depletion space charge layer (thickness d) lowers the effective conducting channel and has to be considered (see Fig 1). In addition the mobility of carriers strongly depends on carrier concentration. Here, we present a controlled route to determine the dopant density of p-type GaAs nanowires. The doping concentrations were estimated from electrical conductivity measurements applied to single nanowires with different diameters. This estimation is based on a mobility vs. carrier concentration model with surface depletion included. Fig. 1. Surface depletion of GaAs nanowires Experimental Setup The GaAs nanowires were grown in a metal-organic vapor-phase (MOVPE) apparatus, using Au particles as catalyst. Detailled growth informations can be found in [4] and report of I.Regolin. For electrical measurements, the nanowires were scratched off the growth substrate and transferred to a carrier. The carrier consists of a semi-insulating GaAs substrate which was covered with 300-nm-thick silicon nitride (SiNx) for improved isolation. The ohmic contacts were formed by evaporation of Pt (5 nm)/ti (10 nm)/pt (10 nm)/au (400 nm). A metal-insulator-field-effect transistor (MISFET) device is fabricated with about 35 nm SiNx gate dielectric and a Ti/Au gate metal [5]. All patterning was done with electron beam lithography, evaporation, and lift-off. 1 µm Fig. 2. Electrical contacts to a single GaAs nano

29 Materials, Growth and Characterization 23 Electrical characterisation and transport model The impact of the DEZn flow on the electrical conductance of GaAs wire is given in Figure 1. If no DEZn is supplied during growth, the current is in the pa range. Next, DEZn at II/III = was added to the gas phase during growth. The corresponding I-V characteristic is perfectly ohmic, exhibiting a high current of 400 µa at 1 V applied bias. The realized doping effect might be related to a diffusion of Zn via the side walls or due transport via the Au seed particle. A possible side wall diffusion effect attributed to DEZn in the gas phase was studied using a nominally undoped wires which were exposed to DEZn under TBAs overpressure at T Diff = 400 C for 20 minutes. Figure 1 reveals that their conductance is not affected. Even at higher temperatures like 500 C, no effective increase of the wire conductivity could be observed. Any doping effect attributed to side wall diffusion is marginal and not exceeding a carrier concentration of cm -3. Therefore, we conclude that the incorporation of doping atoms mainly happens via the Au seed particle or via the seed/wire interface. For the used parameters Zn diffusion within the nanowires is limited to the low nm range and can be neglected. current / µa p-gaas NW (DEZn) T G = 400 C d NW = 150 nm (a) as grown (b) diffusion after growth -200 (c) supply during growth (II/III = 0.04) voltage / V Fig. 2. Representative I-V characteristics of the untapered GaAs nanowires grown at 400 C: (a) as grown; (b) without supply of DEZn during growth, but with post growth diffusion 20 min at 400 C in DEZn and TBAs flow; (c) grown under supply of DEZn. In order to set-up an experimentally verified transport model of p-gaas:zn nanowires, the electrical conductivity of a large number of nanowires with various radii ( 20 nm < r 0 < 150 nm) grown under different DEZn flow ( < II/III < 0.008) were analyzed. We used TLM structures with three, four or five contacts and different contact spacings along the wires, leading into a statistical evaluation. Exemplary the corresponding experimental wire resistances for a II/III ratio of 0.004, normalized to a contact spacing of L = 1 µm are depicted in Fig. 2. (based on electrical measurements of about 80 single nanowires per sample)

30 24 Bi-Annual Report 2008/ Solid-State Electronics Department wire resistance (1µm) / kohm (a) fit to data 5.0 x cm x cm x cm x cm-3 p-gaas NW experimental data wire radius / nm Fig. 2. Evaluated wire resistances versus the wire radius for different II/III ratios. The resistance is nominated to one micron. Fig. 2 (a) shows the measured data of one sample (II/III = 0.004) (based on electrical measurements of about 80 single nanowires per sample), the fitted trend line and additionally modelled data for different acceptor concentrations (dashed lines). The experimental wire resistance decreases both with increasing II/III ratio and wire radius, respectively. This behavior suggests that the conductivity is proportional to the Zn acceptor density N A. Using the typical values for p-gaas of 0 = 450 cm 2 /Vs, r = 13, the following equations (all [4]) may describe the mobility as a function of acceptor density N A : (1) 2 cm 450 ( N A) Vs N 1 10 cm A GaAs and other semiconductor nanowires, exhibit a surface depletion space charge layer with thickness d spc. If we assume a surface potential of s = 0.5 V the corresponding depletion width d spc can be calculated as 2 0 r S (2) dspc q NA with the acceptor concentration p = N A. For a perfect cylindrical symmetry of the nanowires the resistance is hence given by 1 L (3) R. q 2 N µ ( N ) ( r d ) A A o spc The contact resistances calculated from our TLM measurements were located in the low kohm range, generally even below 1 kohm for the doped nanowires. Taking the contact resistance into account would just lead to a marginal shift to slightly higher carrier concentrations. The space charge thickness at the surface reduces the conductive cross section of the nanowire and depends on the dopant density according to eq. 2. Using eqn. (1-3), the modeled wire resistance is plotted as a function of the wire radius and fitted to the experimental data.

31 Materials, Growth and Characterization 25 The experimental data are compared in Fig. 2 with the fitted parameter of the model in eqn. (1-3) giving a very good agreement over a wide range of dopant densities and wire radius. Therefore, we can conclude, that the Zn acceptor density is proportional to the II/III ratio and that the conductivity is proportional to the wire cross section if the surface depletion is taken into account. In addition, an almost linear behaviour between DEZn flow and Zn concentration was demonstrated in the investigated range. This characteristic is depicted in Figure 3. 1 x carrier concentration N A / cm -3 1 x x ,001 0,01 II/III Ratio Fig. 3. Carrier concentration as function of the II/III ratio. A linear dependence is visible. Nevertheless it has to be mentioned, that slight saturation effects occur for high dopant values. In our experiments we were able to adjust the Zn incorporation from cm -3 down to cm -3. Since the DEZn precursor supply was about hundred times lower then normally used for the doping of conventional layers, Zn has to be incorporated very effective at the used growth temperature of 400 C. The use of DEZn implies a p-type conductivity of the wire. To verify the type of doping and the transport model accuracy, metal-insulator-field-effect-transistor (MISFET) devices were fabricated [5]. The transfer characteristic exhibits typical p-channel behavior as the channel conductance increases with negative gate bias. This experiment proves the p-type doping effect using DEZn. In addition, we analyzed the transistor data with respect to mobility and carrier concentration. (Details are given in [4]). The calculated values were in excellent agreement with the values evaluated from the transport model. Conclusion In summary, controllable p-type doping during the VLS growth of GaAs nanowires using diethyl zinc as doping precursor was demonstrated. Tapering free structures as well as diffusion experiments reveal, that the Zn incorporation was driven by the VLS mechanism. Transfer characteristic of MISFET s, fabricated from these nanowires, proved that the doping of the nanowire is p-type. The doping concentration in the nanowires, depending on the DEZn flow, was estimated by mobility vs. carrier concentration model, taking surface depletion due to Fermi-level pinning into account. It could be adjusted by varying the II/III ratio in a wide range from cm -3 down to cm -3. A linear dependence was observed in the investigated range.

32 26 Bi-Annual Report 2008/ Solid-State Electronics Department References [1] E.D. Minot, F. Kelkensberg, M. van Kouwen, J.A. van Dam, L.P. Kouwenhoven,V. Zwiller, M.T. Borgström, O. Wunnicke, M.A. Verheijen, and E.P.A.M. Bakkers; Nano Lett. 7 (2), (2007). [2] K. A. Dick, K. Deppert, L. S. Karlson, L. R. Wallenberg, L. Samuelson, W. Seifert; Adv. Funct. Mat. 15, 1603 (2005). [3] D. Stichtenoth, K. Wegener, C. Gutsche, I. Regolin, F.J. Tegude, W. Prost, M. Seibt, C. Ronning; Appl. Phys. Lett. 92, (2008). [4] C. Gutsche, I. Regolin, K. Blekker, A. Lysov, W. Prost, and F. J. Tegude; Journal of Applied Physics (accepted Dec 2008). [5] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, F. J. Tegude; IEEE Electron Device Lett. 28, 682 (2007).

33 Materials, Growth and Characterization Axial pn-junctions in Vapour-Liquid-Solid Grown GaAs Nanowires by MOVPE using DEZn and TESn Scientist: I. Regolin, C. Gutsche, A. Lysov Introduction III-V semiconductor nanowires have attracted great research interest due to their superior electrical and optoelectronic properties for future high performance nanoscaled devices. The control of carrier type and density in an extremely wide range is the unique advantage of semiconductors for (opto-) electronic device applications [1]. Therefore, the future of any semiconductor nanowire technology will inherently rely on their doping capability. However, the specific parameters for nanowire growth do often not favor the incorporation of doping atoms. This holds especially, if both n- and p- type doping shall be realized during one nanowire growth. In the few recent publications, very low current densities were reported [2]. In addition, a combination of nanowire growth and layered growth enabling core-shell pn-junctions or a combination of doped substrate and nanowire have been selected in order to particularly overcome the doping problem. Moreover, easy and precise measurement techniques in order to determine the carrier concentration inside the nanowires are still lacking. In this contribution, we report on axial pn-gaas nanowires grown on (111)B GaAs substrate by MOVPE method, using the VLS mechanism in combination with Au growth seeds. For p-type doping diethylzinc (DEZn) was used as precursor material and lead to doping concentrations up to 2E19 cm -3, as recently published [3]. To realize the n-doped part, tetraethyltin (TESn) was used as precursor material during the growth. Experimental Setup Monodisperse as well as polydisperse Au nanoparticles were deposited as growth seeds prior to growth. Monodisperse nanoparticles with a diameter of 150 nm were taken from a colloidal solution. Polydisperse nanoparticles were produced by annealing of a thin evaporated Au layer of nominally 2.5 nm thickness. The anneal step was carried out at 600 C for 5 minutes under group-v overpressure and results in nanoparticles with diameters from 30 nm to some 100 nm. Nanowires were grown by metal-organic vapour-phase epitaxy (MOVPE) on (111)B GaAs substrates at a total pressure of 50 mbar. Trimethylgallium (TMGa) and Tertiarybutylarsine (TBAs) were used as group-iii and V precursor, respectively. The total gas flow of 3.4 l/min was provided by N 2 as carrier gas, while H 2 was used for the bubblers. After the growth start, initiated at 450 C for 3 minutes, the final growth temperature was adjusted to 400 C, to exclude almost completely additional growth on the nanowire sidewalls. P-doping was realized by an additional diethylzinc (DEZn) supply with II/III ratios between and 0.067, while the V/III ratio was kept constant at 2.5. To realize the n-doping, tetraethyltin (TESn) was introduced to the reactor with IV/III ratios in the range of and To reach the highest IV/III ratio, the TMGa supply was divided by two, resulting in a V/III ratio of 5 instead of the normal adjusted value of In order to study the doping effects, nominally undoped nanowires, single doped structures, as well as pn-junctions were grown.

34 28 Bi-Annual Report 2008/ Solid-State Electronics Department The nanowires were inspected by scanning electron microscopy (LEO 1530). Electrical results were obtained with standard DC-measurements setup. Therefore the as grown structures were transferred to special prepared carriers and finally contacted by electron beam lithography (E-Beam). The n- as well as the p-type behavior was in addition verified by processed MISFETs structures on single n- and p-doped wires using equal growth parameters. Results Figure 1 show scanning electron microscopy micrographs of GaAs nanowires. The stumps of the nanowires were grown at 450 C in order to reduce structural defects and frequent wire kinking during the initial nucleation. Next the growth temperature is reduced to 400 C which suppresses the conventional layer growth on the side facets leading to a very high aspect ratio up to g r,vls /g r,vs > 1000 for the upper part of the wire. The wires given in Fig. 1 were grown from a colloidal Au seed nanoparticle with different diameters under additional TESn supply with an II/III ratio of The nanowires were grown straight in (111) direction and show no kinking or other structural defects, even at higher II/III ratios up to (IV/III = 0.08) 1 µm Fig. 1. Scanning electron micrographs of n-gaas:sn structures grown on GaAs (111)B substrate at 400 C from colloidal Au nanoparticles and a IV/III ratio of In contrast to that result, p-gaas nanowires show a strong influence to the crystal structure, if to much DEZn is introduced during the growth. This effect is already described in the previous report and shows, that the number of structural defects increases to higher II/III ratios. To enable electrical characterization, the structures were transferred onto s.i. GaAs substrate including an additional 250 nm SiN x insulation layer and prefabricated contact unit cells. Using the E- beam lithography, positions of the deposited nanowires could be verified, what enables the connection to the contact pad structures in combination with standard technology processes. I/V measurements revealed that the conductance of the n-gaas nanowires increased up to 3 orders of magnitude compared to nominally undoped wires. First estimations revealed a doping concentration of approximately cm -3. The n-type behavior could be verified by processed MISFET structures. The successful p-type doping, which is in addition adjustable from cm -3 down to cm -3, has recently been published [3]. In the next step, both p- as well as n-type doping was realized in single nanowire structures. Therefore, nanowires were grown from polydisperse seed particles, formed by annealing of a 2.5 nm

35 Materials, Growth and Characterization 29 thick Au layer. After 3 minutes at 450 C, the growth temperature was again reduced to 400 C. During the whole growth time of 40 minutes the dopant precursor was changed at half time from DEZn to TESn without any additional growth interruptions. The Zn supply was adjusted by the II/III ratio of 0.004, while the IV/III ratio of 0.16 was chosen in the case of Sn doping. The grown pn-gaas nanowires are depicted in figure 2. They have length up to 20 µm with different diameters up to some 100 nm according to the evaporated Au layer prior the growth. 1 µm Fig. 1. Scanning electron micrograph of pn-gaas nanowires grown on GaAs (111)B substrate from a nominal 2.5 nm thin Au layer, evaporated prior the growth. The afterwards processed devices exhibit diode-like I-V characteristics. The currents in the 100 na range is limited by the conductivity of the n-side. A detailed I-V analysis is given in the annual report from Christoph Gutsche (4.1.4). With the successful realization of both, n- and p-type doping in one wire, the requirements for electroluminescence are elaborated. Conclusion In summary, the growth of pn-junctions during the VLS growth of GaAs nanowires using diethyl zinc and TESn as doping precursors was demonstrated. While structural influences and kinking effects are visible with increasing diethyl zinc flow, indicating the upper limit of p-type doping, no effects were observed depending on the tin supply. Since the nanowires were grown untapered, we can exclude the formation of an additive shell around the VLS grown nanowire. The described route for the controlled doping of nanowires is of general interest for all compound semiconductor nanowires. It points out fundamental aspects of growth and doping, respectively, which are the essential challenges for future applications in optoelectronics and sensor technologies. To our knowledge this is the first axial GaAs pn-diode realised in single nanowires. Acknowledgement This work was supported by Sonderforschungsbereich 445 Nanoparticles from the gas-phase References [1] B. Tian et al., Chem. Soc. Rev. 38 (16), [2] E.D. Minot et al., Nano Lett. 7, pp , 2007 [3] C. Gutsche et al., J. Appl.. Phys. 105 (024305), 2009.

36 30 Bi-Annual Report 2008/ Solid-State Electronics Department Electrical Characterisation of MOVPE Grown n- and pn-gaas Nanowires Scientist: C. Gutsche, I. Regolin, A. Lysov Introduction Recently, we presented a controlled route to determine the dopant density of p-gaas nanowires, doped with diethylzinc (DEZn). The doping concentrations were estimated from electrical conductivity measurements applied to single nanowires with different diameters. By adjusting the II/III ratio, controlled doping concentrations from up to cm -3 could be achieved at a growth temperature of 400 C [1]. In this report we adopt the model to n-gaas nanowires, doped with tetraethyltin (TESn). Finally we show the rectifying behaviour of an axial pn-junction, which is to our knowledge the first axial GaAs pn-diode realised in a single nanowire. Experimental Setup The GaAs nanowires were grown in a metal-organic vapor-phase (MOVPE) apparatus, using Au particles as catalyst. Detailled growth informations can be found in [1]. For electrical measurements, the nanowires were scratched off the growth substrate and transferred to a carrier. The carrier consists of a semi-insulating GaAs substrate which was covered with 300- nm-thick silicon nitride (SiNx) for improved isolation. The ohmic contacts were formed by evaporation of Pt (5nm)/Ti (10 nm)/pt (10 nm)/au (400 nm) for p-gaas and Ge (5 nm)/ni (10 nm)/ge (25 nm)/au (400 nm) for n-gaas, respectively. To improve the contact properties an rapid thermal annealing was carried out for 30 s or 300 s at 320 C. A metal-insulator-field-effect transistor (MISFET) device is fabricated with about 35 nm SiN gate dielectric and a Ti/Au gate metal [2]. All patterning was done with lithography, evaporation, and lift-off. Electrical characterisation and transport model n-doping The impact of the TESn flow on the electrical conductance of a GaAs wire is given in Figure 1. If no TESn is supplied during growth, the current is in the pa range. Next, TESn at IV/III = 0.08 was added to the gas phase during growth. The corresponding I-V characteristic is not perfectly ohmic, which indicates a remaining contact barrier. However, annealing at higher temperatures than 320 C leads to an outdiffusion of Ga into the Au contact layer. This effect is also reported for bulk material [3], but gets crucial in the nanoscale and has to be avoided. Nevertheless the current of 2 µa at 1 V applied bias is about six orders of magnitude higher than for the not intentional doped sample, giving evidence of the doping effect. The realized doping effect might be related to a diffusion of Sn via the side walls or due transport via the Au seed particle as already observed for Zn. The possible side wall diffusion effect will be checked in further experiments.

37 Materials, Growth and Characterization n-gaas NW (TESn) T G = 400 C d NW = 60 nm current / µa 0-1 (a) as grown (b) supply during growth (IV/III = 0.08) voltage / V Fig. 1 Representative I-V characteristics of the untapered GaAs nanowires grown at 400 C: (a) as grown; (b) grown under supply of TESn. In order to determine the carrier concentration of the n-doped GaAs nanowires, we adopted the model used for p-gaas (for detailed informations see [1]) and exchanged the varying parameters and equations. For (100) n-gaas the value for the surface potential φ S is 0.6 ev [4]. The dependence between carrier concentration and mobility µ is given by the Hilsum formula [5]: (1) ( N D ) N 17 D 3 cm Here we used a value of μ 0 = 8000 cm 2 /Vs. The electrical conductivity of a number of nanowires with various radii ( 30 nm < r 0 < 70 nm) were analyzed. In Fig 2a the corresponding experimental wire resistances for a IV/III ratio of 0.08, normalized to a contact spacing of L = 1 µm are depicted. Rhombuses represent contact annealing for 30 s, rectangles for 300 s respectively. No dependence on the duration of the annealing step can be observed from this figure. In addition modeled data for three different values of carrier concentration (5x10 17 cm -3, 1x10 18 cm -3, 2x10 18 cm -3 ) is given in dashed lines. The wire resistance decreases both with increasing carrier concentrations and wire radius, respectively. It is evident that the experimental resistance data is spreading between the three modeled lines. Fig. 2b shows the corresponding carrier concentration N D against wire radius r. We can conclude that N D varies from 7x10 17 cm -3 to 2x10 18 cm -3. Taking into account that the contact resistance is neglected for this analysis and that the carrier concentration might change along the wire (as already reported for Zn doped GaAs nanowires [1]) this is a fairly good and reliable result.

38 32 Bi-Annual Report 2008/ Solid-State Electronics Department wire resistance (1µm) / kohm 75 (a) n-gaas NW 1 x cm x cm x cm s s wire radius / nm carrier concentration N D / cm -3 1,0E+19 1,0E+18 1,0E+17 (b) φs = 0.6 ev 320 C 30s 320 C 300s radius / nm Fig. 2 Fig.2 (a) shows the measured wire resistances versus the wire radius for a IV/III ratio of 0.08 (based on electrical measurements of single nanowires) for two different annealing cycles. The resistance is nominated to one micron. In addition modeled data for three different carrier concentrations (5x1017 cm-3, 1x1018 cm-3, 2x1018 cm-3) is given in dashed lines. Fig. 2 (b) shows the corresponding carrier concentration ND against wire radius r. The use of TESn implies a n-type conductivity of the wire. To verify the type of doping, multichannel metal-insulator-field-effect-transistor (MISFET) devices were fabricated [2]. The transfer characteristic exhibits typical n-channel behavior as the channel conductance increases with positive gate bias (see Fig. 3). This experiment proves the n-type doping effect using TESn, which 0,045 U DS = 2 V I D / ma 0,040 is to our knowledge the first successfully n-doped GaAs nanowire grown by VLS. Fig. 3 0, U GS / V Transfer characteristic of an n-gaas nanowire MISFET. The drain-source voltage is 2 V. Typical n-channel behavior is observable. pn-junction Since we now demonstrated p- and n-type doping in GaAs nanowires, we tried to combine both in one single structures. Therefore nanowires with a scheme as depicted in Fig. 4a were grown (for detailled growth informations refer to report of I. Regolin). Surprisingly the doping transitions can be identified via optical microscope (see Fig. 4b). We suppose that the surface might be changed due to the influence of dopants, leading into different reflections.

39 Materials, Growth and Characterization 33 (a) C IV/III = C II/III = C n p i (b) 5 µm n ~ 8.7 µm 1 µm p ~ 8.7 µm n i ~ 1µm p Fig. 4 (a) Nanowire scheme for grown GaAs pn-junctions. (b) Micrograph taken with optical microscope, doping transitions can be identified. Inset shows contact structure. For electrical characterisation the nanowire pn-diodes were processed as described before with two contacts on p- (Pt/Ti/Pt/Au) and n-doped (Ge/Ni/Ge/Au) area (see inset in Fig. 4b). The measured I-V curves of the p-side (Fig. 5a) are perfectly ohmic and exhibit high currents of about 50 µa at 0.5 V bias, proving the estimated carrier concentration for the chosen DEZn flow (N A (II/III=0.04) 1.6x10 19 cm -3 [1]) (a) pn-gaas NW (DEZn,TESn) T G = 400 C (b) pn-gaas NW (DeZn,TESn) T G = 400 C current / µa 0-25 p-side Fig. 5 current / na voltage / V voltage / V I-V curves for the p-side(a), the n-side and the pn-junction (both (b)) of a fabricated axial nanowire pn-diode; note the different scaling of both diagrams To overcome the contact barrier problems for the n-side we tried to increase the carrier concentration (IV/III ratio) by decreasing the Ga flow. Hence we achieved a IV/III ratio of 0.16 which is doubled compared to the upper sample. 0 U th -20 pn-junction n-side

40 34 Bi-Annual Report 2008/ Solid-State Electronics Department The corresponding I-V characteristic of the n-side (Fig. 5b) reveals that the conductivity as well as the contact properties are not enhanced, but even poorer. It is evident that the current flow is decreased by three orders of magnitude, from the µa to the na range. To prove this effect and exclude an influence of p-doped nanowire part, we also processed n-gaas samples grown with the same parameters. The measured data were consistent with our previous results. In addition we observed that the growth rate of the nanowires grown at IV/III = 0.16 is higher then for the ones grown at IV/III = 0.08 though the Ga flow is halved (gr nm/min, gr nm/min). This effect might be attributed to a higher diffusion length of Ga atoms induced by Sn, so that the reduced Ga flow is overcompensated. Herewith also an possible explanation for the lower carrier concentration would be given. Nevertheless comparing the curves of the pn-junction with the n-part data shows that the devices exhibit diode-like I-V characteristics. The current in forward direction sets on at a voltage of approximately 1.5 V, which is in fairly good agreement with the estimated one (U DGaAs = 1.42 V, note that we have an additional barrier stemming from the contacts). The low current in the na range is limited by the conductivity of the n-side. With the successful realization of both, n-and p-type doping in one wire the requirements for electroluminescence and further device elements are elaborated. Our upcoming experiments will be aimed to overcome the problems of n-type contacts and low current density in the n-part. Conclusion In summary, we presented the first succesfull n-type doping during the VLS growth of GaAs nanowires using tetraethyltin as doping precursor. From the experimental resistance data we were able to estimate a donor concentration N D varying from 7x10 17 cm -3 to 2x10 18 cm -3. Transfer characteristic of MISFET s, fabricated from these nanowires, proved that the doping of the nanowire is n-type. The processed axial GaAs pn-diode exhibit diode-like I-V characteristic with a threshold voltage U th of approximately 1.5 V. Though the low currents in the na range are limited by the n-side, this is to our knowledge the first axial GaAs pn-diode realised in single nanowires. Acknowledgment This work was supported by SFB 445 Nanoparticles from the gas-phase and CENIDE. References [1] C. Gutsche, I. Regolin, K. Blekker, A. Lysov, W. Prost, and F. J. Tegude; J. of Appl. Phys. 105, (2009). [2] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, F. J. Tegude; IEEE Electron Device Lett. 28, 682 (2007). [3] R. Williams: Modern GaAs Processing Methods (Artech House, London, 1990) Chap. 11. [4] W.E.Spicer, I. Lindau, P.E. Gregory et al., J. Vac. Sci. Technol, Vol. 13, No.4, (1976). [5] C. Hilsum, Electron. Lett. 10, 13, , (1974).

41 Materials, Growth and Characterization Growth and Doping of InP Nanowires Scientist: A. Lysov, C. Gutsche, K. Blekker Introduction Semiconductor nanowires offer a possibility of complex bottom-up design, that is attractive for future nanophotonic device concepts. InP nanowires have recently received attention for use in nanowire based photodiodes and LEDs [1,2,3]. InP nanowire based applications reported until now had a drawback of low current density, originating from the surface depletion of the p-inp nanowires. This contribution reports about the growth and doping of InP nanowires with alternative not gaseous precursors. The influence of the essential growth parameters such as growth temperature and V/III ratio on the nanowire morphology is discussed. Experimental setup InP nanowires were produced by low pressure (50 mbar) metallorganic vapour-phase epitaxy (MOVPE) using tertiarybutylphosphine (TBP) as group-v, while trimethylindium (TMIn) as group- III source. As doping sources diethylzinc (DEZn) und tetraethyltin (TESn) were used. Colloidal Au-nanoparticles with the diameter of 100nm and 2,5 Au-layers deposited on the (111)B InP were used as templates for the nanowire growth. Before growth an annealing step of 5 min. at 600 C under TBP atmosphere was carried out. The growth temperature and the V/III ratio were varied in the ranges between 395 C 430 C and respectively. The characterisation of morphology was done by scanning electron microscope (SEM). For electrical measurements, the structures were transferred to a carrier substrate. The contacts to the nanowires were patterned by optical beam lithography. For n-type contacts Ge/Ni/Ge/Au and for p-type contact Ti/Pt/Au as well as ZnAu alloy was evaporated. An annealing step of 30 sec. at 300 C and 5 minutes at 300 C were carried out for p- and n-inp nanowires correspondingly. Results Nanowires grown from colloidal nanoparticles and those, grown from the evaporated gold layers show considerably different dependence of the nanowire morphology on the growth parameters. To find out the optimal growth parameters for the nanowire growth from colloidal nanoparticles growth experiments at the temperature of 415 C with different V/III ratios were carried out (Fig. 1). At low V/III ratio of 10 growth seeds seem to split up at the beginning of the growth. Nanowires have negative tapering with the diameter increasing towards the top of the nanowires. The probable reason for such a morphology is a lack of the group V-component causing the growth seed suck indium and blow up during the growth.

42 36 Bi-Annual Report 2008/ Solid-State Electronics Department With increasing of V/III ratio negative tapering disappears. At V/III of 50 nanowires grow untaperad, but the kinking effect takes place. At the V/III ratio of 120 kinking of the nanowires disappear, at the same time tapering effect increases. In general increasing of the V/III ratio at a definite growth temperature leads to the better nanowire morphology but favours the growth of an unintentional nanowire shell. Fig. 1 InP nanowires grown from 100nm colloidal nanoparticles at 410 C with different V/III ratios. The ratio of the lateral and radial growth rates is indicated on the pictures. The reason for the observed morphology dependence is attributed to the decrease of the surface diffusion length of indium on the phosphor reach surface. There exist two ways for indium species to reach the growth seed either directly from the gas phase or through the diffusion on the nanowire side facets (Fig. 2). If the diffusion lengths of indium species decreases not all of them will reach the growth seed but will deposit on the side facets causing the nanowire tapering. Fig. 2 Scheme of the different ways of material transport into the nanowire. In order to reduce the growth of the unintentional shell at the V/III of 120 the growth temperature was reduced to 400 C. It turned out, that nanowires kink at the beginning of the growth, and partially grow along the surface. For this reason a two-temperature growth regime was applied. To prevent wire kinking at the beginning of the growth an initial nanowire stump was grown for 8 seconds at 410 C, then temperature was lowered to the growth temperature and the rest of the nanowire was grown. To investigate the dependence of the nanowire tapering on the temperature growth experiments at the different temperatures were carried out for the constant V/III ratio (Fig. 3).

43 Materials, Growth and Characterization 37 Fig. 3 InP nanowires grown from 100nm colloidal nanoparticles at V/III of 120 with two temperature growth regime. As one can see the ratio of the axial and radial growth rates increases as the growth temperature is decreased. At the growth temperatures of 400 C and 395 C the axial growth rate is 1000 times higher as radial, so that nanowires can be considered as untapered. Nanowires grown from the gold layer at a definite V/III ratio doesn t show any temperature dependence of the morphology in the investigated temperature range of 395 < T < 430. Growth experiments from the thin gold layer carried out at the temperature of 410 C and different V/III ratios have revealed that nanowires grow untapered with V/III ratio beeing in the range between 50 and 200. The growth rate of 2 nm/sec is one tenth of that in the case of colloidal particles. This behaviour can be explained by the dense arrangement of the growth seeds, that reduces a material difussion over the side facets, wich is responsible for the appearing of tapering. To investigate the doping of InP nanowires growth experiments under supply of DEZn and TESn were carried out. High II/III ratios were chosen to achieve high doping levels, which are necessary for the reliable electrical characterisation. In both cases a deteoriation of the nanowire morphology coming along with an increasing flow of the doping precursor was observed. With an increasing flow of DEZn tapering of the nanowires increases and growth of the small branches appears (Fig. 4). Fig. 4 InP nanowires grown from 100 nm colloidal nanoparticles at a temperature of 400 C and V/III of 120 under different DEZn supply. An initial nanowire stamp was grown at 410 C to promote the growth start.

44 38 Bi-Annual Report 2008/ Solid-State Electronics Department In the case of TESn an increasing of the nanowire kinking was obeserved with the increasing of the IV/III ratio. The both described effects weren t observed for the nanowires grown from the thin gold layer. Electrical investigations of untapered InP nanowires grown under supply of DEZn and TESn have revealed currents in a µa range flowing through single wires. This indicates sex orders of magnitude higher conductivity, than in nominally undoped samples, where current in pa range were registered. ZnAu contacts as well as Pt/Ti/Pt/Au contacts were used to contact p-type InP nanowires. In the case of zinc doped InP nanowires bad contact properties complicated an estimation of electrical measurements. InP is known to have a Fermi-level pinned at the surface 1 ev over the valence band edge, so that there is a large energetic barrier for holes. The last fact causes nonlinearity of the IV curves. To contact Sn doped nanowires Ge/Ni/Ge/Au contacts were used. An annealing step of 5 minutes at 300 C was carried out to obtain linear IV characteristics. In the next steps chemical passivation of the surface will be tried to obtain better electrical properties of zinc doped InP wires The combination of already achieved p- and n- doping in a single nanowire should lead in further steps to the preparation of axial and radial pn-junctions in single nanowires. Conclusion In summary, the growth of InP nanowires from colloidal gold nanoparticles and thin layers was developed. Optimum growth parameters to produce untapered nanowires were found. When growing from the colloidal nanoparticles a two temperature growth turned out to be necessary in order to avoid an unintentional shell. Doping experiments have revealed an influence of doping precursors on the nanowire morphology, yielding branched and tapered nanotrees, when DEZn was supplied during the growth from colloidal nanoparticles. In the case of TESn kinking of the nanowires appeared. The both described effects weren t observed for the nanowires grown from the thin gold layer. Electrical investigations of untapered InP nanowires grown under supply of DEZn and TESn have revealed currents in a µa range flowing through single wires. The fermi level pinning at the nanowire surface turned out to be a problem for the contact properties, which should be solved in the future. References: [1] C. Novotny et al Nano Lett., 8 (3), pp [2] Ethan D. Minot et al Nano Lett., 7 (2), pp [3] M. T. Borgström et al Nanotechnology, 19,

45 Materials, Growth and Characterization Au-Assited MOVPE of GaN Nanowires in a Close Coupled Showerhead Reactor Scientist: I. Regolin, H. Behmenburg (Aixtron AG, RTWH Aachen) J. P. Ahl (Aixtron AG, RTWH Aachen) Introduction In recent years, wide band-gap semiconductors like GaN and related III-nitride alloys have attracted great attention because of their applications in optoelectronics and electronics. The controlled growth of GaN structures with small lateral dimensions like nanowires causes an increased interest because of additional advantages. The small growth area could reduce the usually large density of lattice-mismatch induced threading dislocations, which cannot be avoided in conventional layer growth on the whole substrate. In addition the growth rate of GaN nanowires could be much higher than compared to conventional layer growth, depending on the growth method. The first GaN based nanowire LED was reported in 2004 by Kikuchi et al., using MBE [1]. In 2009 Hersee et al. presented the first MOVPE grown GaN nanowire LED [2]. Thereby, in both cases no catalyst like Au was used for the wire growth. Up to now, there is only one publication, describing the successful realization of MOVPE grown GaN nanowires in combination with Au-catalysts in a self-made horizontal MOVPE reactor [3]. In this contribution, we report first experiments on GaN nanowires grown on c-plane sapphire substrate by MOVPE method, using Au growth seeds. Since there are only a few reports on Auassisted growth in a close coupled showerhead (CCS) reactor a lot of parameters like reactor pressure, annealing step, gallium pre-deposition, growth temperature and V/III ratio were varied in a wide range. A lot of experiments revealed, that the window for successful wire growth seems to be very small. However, depending on the main parameters like growth temperature, reactor pressure and V/III ratio, first wire-like structures could be realized. A further fine tuning of the growth conditions should lead to homogeneous and longer structures with high aspect ratios to enable electrical characterization and doping experiments. Experimental Setup Growth experiments were done in a CCS metal-organic vapour-phase epitaxy (MOVPE) system on c-plane sapphire substrates. Since the new MOVPE System for nitride-based materials will be installed in the middle of 2010, these experiments were carried out in a similar system at Aixtron (Herzogenrath), which is also partner in this project. Polydisperse nanoparticles were produced by annealing of a thin evaporated Au layer of nominally 1 nm thickness. Simultaneously, samples with a deposited layer of 1 nm Ni have been prepared for comparison. The anneal step was carried out at the respective growth temperature for 3 minutes under ammonia (NH 3 ) overpressure. In addition, triethylgallium (TEGa) was introduced as pre-deposition step to form Au-Ga nanoparticles with different diameters. The influence of the pre-deposition was thereby investigated up to a deposition time up to 6 minutes. The total reactor pressure was varied between 50 mbar and 900 mbar. Triethylgallium (TEGa) and NH 3 were used as group-iii and V precursor, respectively. The total

46 40 Bi-Annual Report 2008/ Solid-State Electronics Department gas flow of 8 l/min was provided by N 2 as carrier gas and was also used for the bubblers. The growth temperature adjusted between 844 C and 912 C, while the V/III ratio was investigated between 3 and 27. The growth time was kept constant at 15 min for all experiments. The grown structures were inspected by scanning electron microscopy (LEO 1530). Results 100 nm Fig. 1 Scanning electron micrograph of GaN structures grown on a c-plane sapphire substrate at 870 C. As growth seeds a 1 nm thin Au-layer was used in combination with an annealing step and a TEGa pre-deposition for 2 minutes. The reactor pressure was adjusted to 900 mbar at a V/III ratio of 7. Figure 1 shows a scanning electron microscopy micrograph of the first realized wire-like GaN structures. The structures were grown at 870 C at a V/III ratio of 7. The reactor pressure was adjusted to 900 mbar. The growth seeds were realized during the annealing step of a nominally 1 nm thin Au-layer at growth temperature and a TEGa pre-deposition time of 2 minutes. However, the depicted nanowire structures, with length clearly below 1 µm were only grown on the sample edges. In addition the density of the wire-like structures is even very low at the edges and decreases rapidly in direction to the sample center. This result reveals, that the growth conditions are different between the sample edges and the most part of the sample. Nevertheless, experiments with varying the V/III ratio at 900 mbar indicating, that a low V/III ratio is favorable for the nanowire growth. In the next step, the reactor pressure was reduced to 100 mbar during the growth, enabling the first wire-like structures, even in the center of the samples. Figure 2 shows two results of GaN structures realized at a V/III ratio of 27 (a) and 3 (b), respectively.

47 Materials, Growth and Characterization nm 100 nm a) Fig. 2 b) Scanning electron micrographs of GaN structures grown on c-plane saphirre substrate at 870 C. As growth seed, a 1 nm thin Au-layer was used in combination with an annealig step and a TEGa pre-deposition for 2 minutes. The reactor pressure was adjusted to 100 mbar. Strong conventional growth is visible at a V/III ratio of 27 leading to heavily tapered nanowire structures (a). Non-tapered wire-like structures were grown in a high density at a V/III ratio of 3 (b). The growth temperature was again 870 C for both cases and a nominally 1 nm thin Au-layer was used as growth seed under the same annealing conditions. The structures in figure 2(a) show a strong tapering effect, due to additional conventional layer growth. In addition the density of the pyramid like nanowire structures is very low. In contrast to that, the reduced V/III ratio led to nontapered nanowire structures in a high density nearly on the whole sample (fig. 2(b)). Only the sample edges show no wire growth probably due to the already explained difference of the local growth conditions. The wires have lengths of up to 1 µm and the Au/Ga droplets are still visible on top of the grown structures. The reason for the difference in the diameter between wire and seed particle is not clear yet, but could be explained with the cooling down step and the related reduced solubility of gallium in gold. Up to now, a low V/III ratio around 3 or even less in combination with a reactor pressure around 100 mbar seems to be necessary for successful GaN wire growth in a CCS MOVPE system. The used growth temperatures above 800 C indicate that the growth is not driven by a typical VLS process. At those temperatures, the solubility of gallium in gold is unlimited. Therefore, no equilibrium state with a super-saturation point does exist, enabling a typical VLS process. Therefore, we assume that the Au/Ga droplet acts as sink for the precursor material. In case of the 1 nm Ni-layer as growth seed, no controlled nanowire growth was observed during the whole experiments, besides some wire-like structures at the sample edges. In the next step the Au-layer thickness, the annealing conditions as well as the growth temperature and the pre-deposition step will be tuned more precisely to enhance the nanowire growth. In addition the growth time will be increased to get longer wires, to enable the first electrical measurements. Since the diffusion length of the source material is an important parameter, which is also influenced by other precursor materials, a simultaneous supply of silan (SiH 4 ) could enhance the growth rate of the GaN structures. Conclusion In summary, we demonstrated the first successful growth of GaN nanowires in a CCS MOVPE system, using a thin Au-layer as growth seed and elevated temperature. The growth is thereby not

48 42 Bi-Annual Report 2008/ Solid-State Electronics Department driven by a typical VLS process with a defined super-saturation. Continuing experiments with further tuned growth conditions should enable electrical characterization of these GaN nanowires. Acknowledgement This work was supported by the NRW-Project Ziel 2 Projektförderung Forschung, Innovation und Technologie des Landes NRW (FIT) LHO Kooperationsprojekt: Halbleiter-Nanodrähte für Solarzellen und Leuchtdioden (NaSoL) References [1] A. Kikuchi et al., Jap. J. Appl. Phys. 43, No. 12A, pp. L1524-L1526, 2004 [2] S. D. Hersee et al., IEEE Electronics Letters 45, No. 1, 2009 [3] V. Gottschalch et al., J. Crystal Growth 310, pp , 2008

49 Bi-Annual Report 2008/ Solid-State Electronics Department Device and Circuit Processing

50 44 Bi-Annual Report 2008/ Solid-State Electronics Department Optimized RTD-Design for Application in Microwave Frequency Generation Circuits Scientist Technical Assistant B.Münstermann R.Geitmann Introduction Resonant Tunnelling Diodes (RTD) are promising devices for microwave frequency generation circuits. These strongly nonlinear devices offer a negative differential resistance region in their DC- Characteristic, which can be used to restore energy in resonators for generating microwave power. The amount of available RF-power depends on the shape of the I/V-curve in the NDR-region. To achieve possible improvements in RTD-based oscillators, the design of the RTD layer stack is investigated and optimized in this work. RTD behaviour in oscillators From Leesons law [1] it is known, that a high voltage swing at the resonator is crucial for designing low phase noise oscillators. When using RTDs the differential conductance in the NDR-region determines the open loop gain and is therefore an important parameter to increase the voltage swing. In addition the width of the NDR-region should be increased to create a wide voltage range in which the RTD can amplify oscillation. ΔI ΔI ΔV ΔV V RTD / V V RTD / V Fig. 1 I-V simulation results at 20 GHz: standard RTD model used for digital applications (a) and modified model (b). To investigate the influence of RTD-characteristics on the voltage swing of the oscillator, simulations based on the large-signal model described in [2] were made. The resonator consisting of a varactor diode and a spiral inductor in parallel is designed to oscillate around the center frequency of 20 GHz. To achieve an accurate description of the resonator losses the lumped components were modelled based on measurements of fabricated devices up to 50 GHz. The results of transient simulations are shown in Fig.1 for the standard RTD model and a modified model with increased

51 Device and Circuit Processing 45 peak to valley current ratio (PVCR) and a high peak voltage. Apart from the DC-characteristics (shown in red) the AC-current flowing into the RTD is plotted in black to show the differences in simulated voltage swings ΔV between the two RTD-designs. Layer Composition The standard RTD layer structure (Fig.2b) consist of all lattice matched InGaAs well and InAlAs barrier layers grown by Metal Organic Vapour Phase Epitaxy (MOVPE) on InP substrate. To get access to the intrinsic device additional doped InGaAs layers are needed to form ohmic contacts. The realization of high peak current densities in combination with a high PVCR in RTDs needs thin and energetic high barriers which can be realized by Molecular Beam Epitaxy (MBE). The optimized layer stack of the fabricated devices is depicted in Fig.2a. In addition to the change to AlAs as barrier material, the thickness of the barrier is reduced to 6-7 monolayers which corresponds to a thickness of 1.7 nm / 1.98 nm. Fig. 2 Double barrier RTD grown with MBE (b) and grown with MOVPE (b) For device testing both designs were fabricated with an RTD technology using standard wet chemical etching processes and PtTiAu evaporation for ohmic contacting. Devices of several emitter sizes between 0.56 µm 2 and 25 µm 2 have been successfully realized to attest scaling of peak current and contact resistances for accurate modelling. Measurement Results In Fig.3 the IV-characteristics of fabricated devices of 1 µm x 1 µm size are shown. The standard RTD (a) exhibits a peak current density of 60 ka/cm 2 with a PVCR of 2.5. The width of the NDRregion is about 180 mv. The curves (b) and (c) represent the characteristics of the MBE-grown RTDs with 7 ML AlAs barriers and two different doping concentration in the spacer layer. The MBE layer design leads to a high PVCR of 10 and wide NDR regions of 300mV for high (b) and 400mV (c) for low spacer doping. To increase the absolute current difference ΔI the barrier thickness was reduced to 6 ML AlAs which leads to very high peak current densitys of 195kA/cm 2 together with a PVCR of 10 and a 400mV wide NDR-region.

52 46 Bi-Annual Report 2008/ Solid-State Electronics Department To investigate the RF-performance the devices have been characterized by measuring the s- parameters of devices from 50MHz to 40GHz. To describe the RTD the small signal model shown in Fig. 4a is used. The parameter R s describes the contact and bulk resistances in the extrinsic layers and is bias-independent but scalable with emitter size. The extraction was done by biasing the RTD near the valley voltage V v. At high frequencies the real part of the impedance converges to the resistance R s, because G d and C d can be neglected under these conditions. The bias dependent parameters can be extracted after substracting R s. Fig. 3 I-V characteristics of RTD: Standard RTD (a), MBE RTD with 1.98 nm barrier (b, c) and with 1.7 nm barrier (d) With the help of the extracted small signal model the cut off frequency fmax of the device can be estimated as shown in [3]. For small area devices fabricated with the optimized layer design fmax is estimated to be higher than 300 GHz, which clarifies the high frequency applicability of this RTD design (Fig.4b). freq (50.00MHz to 40.00GHz) freq (1.000GHz to 1.000THz) Fig. 4 a) small signal model for RTD, b) measured and modelled S-Parameters

53 Device and Circuit Processing 47 Conclusion An optimized RTD-design for application in frequency generation circuits has been fabricated and characterised with a cut off frequency of 300GHz. References [1] Matiss, A. Poloczek, W. Brockerhoff, W. Prost and F.- J. Tegude Large-Signal Analysis and AC Moedlling of Sub Micron Resonant Tunneling Diodes, Europ. Microw Conf., pp , 2007 [2] Leesson, D.B. A simple model of feedback oscillator noise spectrum. Proceedings of the IEEE. 1966, pp [3] C. Kidner, I. Mehdi, J. R. East, and G. I. Haddad, Power and stability limitations of resonant tunneling diodes, IEEE Trans. Microw. Theory Tech., vol.38, pp , 1990

54 48 Bi-Annual Report 2008/ Solid-State Electronics Department Scalable High-Current Density RTD with Low Series Resistance Scientist Technical Assistant A. Tchegho, B. Münstermann R.Geitmann Introduction Resonant tunnelling diodes (RTD) are promising devices for high-speed circuit design. The negative differential resistance in their non-linear current-voltage characteristic and their fast switching speed make them suitable for a wide range of circuit applications. A well known digital circuit example is the monostable-bistable transition logic elements (MOBILE) suitable for various logic gates [1, 2, 3] but also for analogue and mixed signal circuits. The MOBILE consists of two series connected RTD. It is a robust high speed self-latching logic, gate that requires for high speed operation both, a high peak current density and a very small emitter area, respectively. Moreover, the logic function is determined by the absolute current value and hence is very sensitive to the homogeneity and reproducibility of epitaxial growth and to the precision of emitter area definition. To increase the switching speed of the MOBILE, it is necessary to increase the current density of the RTDs. However, this approach makes the device even more sensitive to epitaxial growth fluctuations [3]. Moreover, the voltage drop at the parasitic series resistance R s and its scaling with device area are tremendous problems inhibiting a presice scaling of I-V data at DC and RF which is mandatory for the functionality high speed circuits. The series resistance R s is a parasitic component of the RTD, and is dominated by the ohmic contact and the resistance of the contact layer. It has to be kept low to reduce the voltage drop at the parasitics and to reduce the RC-delay. RTD Technology and Design The epitaxial growth of the heterostructure layer sequence was realised with molecular beam epitaxy on semi-insulating InP-substrate [3]. The intrinsic RTD structure (see Fig. 2-a) consists of an InGaAs/InAs/InGaAs quantum well (1.1 nm / 1.2 nm /1.1 nm) sandwiched between 1.7 nm AlAs barriers. The lattice matched InGaAs smoothes the surface after lattice-mismatched growth and reduces the valley current such that a peak-to-valley current ratio > 10 becomes feasible despite the high current density. The device processing was carried out using electron beam lithography, wet or dry etching, and Ti/Pt/Au(/Ni) lift-off technology. The process started with the definition of single or multiple RTDanode electrodes down to a nominal area 0.75 x 0.75 µm². Using the upper electrode as an etch mask, the RTD-layer stack was etched down to the lower interconnection layer. Two etching processes were compared: the wet chemical etching and the inductively-coupled plasma reactive ion etching (RIE). The SEM micrograph of a fabricated 4-mesa device is shown in Fig. 1-a. A typical I-V characteristic of a fabricated RTD is given in Fig. 2-b exhibiting a very high peak-tovalley current ratio.

55 Device and Circuit Processing 49 Device Characterisation The fabricated devices have been characterized under DC conditions to extract the peak current density from the IV-characteristics. In Figure 2-b the measured peak current density for devices of 0.56 µm 2 up to 25 µm 2 mesa-area sizes is depicted for the two investigated process technologies. The wet etching of the mesa results in a lower effective electrode area. Hence, the nominal peak current density is always lower than in case of RIE etching. At smaller area (< 10 µm²), the undercut of wet chemical etching decreases the nominal current density down to 1/3 of the original value. The dry etched sample, however, shows a good scalability and reproductively of the nominal peak current density down to 0.75 µm² electrode area. This technology is the best candidate for RTD manufactory in the nanometre range. a) b) Fig. 1 - a) SEM micrograph of quad mesa RTD with 4 x 0.75 x 0.75 µm² active area. - b) IV-Characteristics of a RTD with 4-µm 2 mesa area. The inset shows a large signal model with bias independent series resistor R S Fig. 2 a) Topology of the double barrier RTD grown with MBE b) Measured Peak Current Density for the ICP-RIE process and wet chemical process

56 50 Bi-Annual Report 2008/ Solid-State Electronics Department To extract the source resistance the high frequency scattering parameters (up to 50 GHz), applying the large signal equivalent circuit [2] in Fig.1-b, have been measured, while biasing the RTD in the valley region. This procedure allows reliable extraction of the source resistance under stable bias conditions. The series resistance for varying mesa area is shown in Figure 3 for the investigated single-mesa, double-mesa and quad-mesa design (cf Fig.1-a). The series resistance is substantially reduced in case of multiple mesa devices for the same devices area enabling higher speed operation. resistance RS [Ohm] µm 1µm 2µm 2.5µm Fit (0.75µm) Fit (2µm) Fit (1µm)) Fit (2.5 µm) y = 35.2x y = 22.56x y = 10.4x y = 7.6x a) 0 0 1/4 1/2 3/4 1 1/Number of Mesa b) Fig. 3 Series resistance for single, double and quad mesa design versus the inverse of the number of mesa (a) and versus the total mesa area (b). Conclusion The scalability in sub-micrometer range and the reproducibility of the high current density RTD have been proven. The splitting of the RTD mesa area can be used to reduce the series resistance, which is an important factor of its speed performance. This study shows that RTD are ready for use in very large scale integrated high speed circuits and may contribute to the development of future nanoelectronic circuits.

57 Device and Circuit Processing 51 References [1] K. Meazawa, T. Mizutani, A New Resonant Tunneling Logic gate Employing Monostable- Bistable Transition, Jpn. J. Appl. Phys., Vol. 32, pp. L 42-L 44, 15 January 1993 [2] A. Matiss.et al. "Large-signal analysis and AC modelling of sub micron resonant tunnelling diodes," Microwave Integrated Circuit Conference, EuMIC European, vol., no., pp , 8-10 Oct [3] W. Prost et al. Manufacturability and Robust Design of Nanoelectronic Logic Circuits based on Resonant Tunneling Diodes, Int. J. Circ. Theory and Appl, Vol. 28, pp , 2000

58 52 Bi-Annual Report 2008/ Solid-State Electronics Department Low-Power RTD-based-VCO for Ka-Band Application Scientists: B. Münstermann, Kai Blekker Introduction The benefits of the resonant tunneling diodes are very high oscillation frequencies, low power consumption and low phase noise as reported in several publications. The build-in negative resistance of the device can easily be used to enforce oscillation, but also causes a bias instability problem, which prevents reliable measurements. To overcome the problems of instability in voltage controlled oscillators (VCO) the RTD-pair architecture allows using large capacitors near to the circuit to stabilize DC-biasing. To design this RTD-VCO accurately, a precise characterization of the RTD, especially when biased in the negative differential resistance (NDR) regime, is crucial. In the widely-used RTD-modeling technique errors caused by up-scaling small sized RTD are generated. Hence the disagreement between simulated and fabricated RTD-VCO requires additional iterations in the design and optimization process of the circuits. In this paper a new method is reported to enable stable DC- and S-parameter measurements. Based on these measurements a RTD-HBT VCO has been designed and fabricated to demonstrate the applicability of RTDs in Ka- Band frequency generation. Device Technology Fig. 1 Integration of InP HBT- and MBE RTD - technology The resonant tunneling diodes have been grown by molecular beam epitaxy (MBE). The double barrier structure consists of a quantum well formed by InGaAs/InAs/InGaAs heterostructure of 3.55 nm sandwiched by two AlAs barriers with a nominal thickness of 1.7 nm. The InGaAs contact layers are highly doped to provide ohmic behavior of the metal/semiconductor contacts. The RTD technology is combined with an InP HBT three mesa technology for monolithically integrating output buffer stages and varactors. In Fig.1 the integrated RTD HBT layer stack is shown. The HBT is grown by metal organic vapour phase epitaxy on top of the RTD layers. The chosen order of epitaxial steps has demonstrated the best yield of processed RTD, because the

59 Device and Circuit Processing 53 devices with thin barriers have shown a high sensitivity to rough surfaces. The base collector pnjunction is also used to create a 11x11 µm 2 varactor diode to enable an appropriate tuning range. The measured quality factor varies from 25 to 45 between 0.5 V and 3 V reverse voltage. The inductor is created by two metal layers of 400 nm and 600 nm thickness respectively, using an air bridge technology. The design used exhibits an inductance value of 300 ph and a quality factor of 19 at 20 GHz. Advanced RTD characterization technique The measurement of the I/V-characteristics of resonant tunneling devices is challenging, because the build in negative resistance tends to enforce unwanted oscillations in parasitic environments, like e.g. inductive cables or probe tips. The appearance of spurious oscillations strongly depends on the negative differential conductance which should be high for good oscillator performance. 5 4 without stabilization stabilized measurement I RTD / ma ,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 V RTD / V -I RTD V RTD 50Ω R stab R stab 50Ω 0V Fig. 2 a) Test-structure for stable measurements in the NDR-region, b) DC-measurement of a 4µm 2 RTD with and without on-wafer stabilization, c) Schematic of the measurement setup The new method for the stable characterization of discrete tunneling diodes uses resistors to increase the resistive load of the parasitic resonant circuit. We adapted this technique to the new onwafer test structure depicted in Fig.2 a,c. The RTD is contacted by a 2-port coplanar contact pattern with stabilizing shunt resistors R stab which use the lower InGaAs contact layer of the RTD layer

60 54 Bi-Annual Report 2008/ Solid-State Electronics Department stack. The DC-measurement can be done by using two source-meter-units as voltage sources. While the voltage V RTD is swept by the first SMU the second sets the voltage drop on the Resistor R stab to 0 V and measures the current through the device. By choosing low values for R stab the suppression of unwanted oscillations can be achieved as can be seen in the IV-characteristics of a 4 µm 2 RTD in Fig.2 b). The plotted currents are measured with a short integration time to illustrate the oscillation errors in the NDR regime (grey plot). V tune V rtd1 V CC v out a) b) V rtd2 V EE Fig. 3 Circuit topology (a) and Chip-Foto (b) of the designed RTD-HBT VCO VCO Circuit and Results The signal power available from RTD-oscillators depends on the available negative conductance g RTD at the bias point and on the width of the NDR-region. One way to improve these properties is to use an RTD-pair. Here, two RTD s of identical areas, connected in series and biased with opposite voltages, are used to create a negative conductance at the center node. In Fig. 4 the circuit topology for the designed VCO is depicted. The HBT-Buffer is added to isolate the oscillation node from the measurement environment. The bias instability in conventional RTDoscillators is caused by spurious oscillation in the bias line. This effect is more critical for high values of g RTD, and therefore restricts the usable RTD-areas and available RF-power. An additional advantage of the RTD-pair is the separation of the oscillation node from the DC-supply lines, thus large shunt capacitors can be added to reject unwanted spurious oscillation without influencing the oscillation frequency. We added large on-chip MIM capacitors using SiN x as dielectric layer to realize maximum suppression of unwanted bias line oscillation. In Fig. 3a photograph of the produced VCO-chip is shown. The chip-size including pads for on-wafer characterization is 1 x 1 mm 2. The output spectrum measured on-wafer with a spectrum analyser without compensation the losses of cables. A sharp peak at the designed centre frequency of 20 GHz was observed. The peak power detected varies from -3.8 dbm to the maximum power of up to -0.9 dbm over a tuning range of 1 GHz. The DC-power consumed from the VCO was below 8 mw, from which only 2.14 mw were

61 Device and Circuit Processing 55 required for the RTD-pair VCO core. The measured phasenoise at 1 MHz offset from the carrier was -108 dbc/hz. Conclusion Based on an advanced characterization method for RTD in the negative conductance region, a VCO design in RTD/HBT technology was developed and processed to create a 20 GHz VCO with 1 GHz tuning range. The low power consumption and low phase noise observed demonstrate the potential of RTD-based VCO-Circuits.

62 56 Bi-Annual Report 2008 /2009- Solid-State Electronics Department Fabrication of Nanowire Based Top-Contacted pn-diodes Scientist A. Lysov Introduction The standard technique used for the contact preparation of nanowires includes transfer of the nanowires from the growth substrate onto the host substrate as well as a following electron beam lithography step for the definition of the contact positions. Since both methods are time consuming and partly expensive they are unsuitable for the use as a contacting procedure in the mass production of nanowire based photovoltaic and LED devises. This contribution reports on the fabrication of electrical top-contacts to free-standing wires. Topcontact technology was first proposed by Hiruma et. al. [1], whereby tapered GaAs-nanowires standing on the substrate were contacted at the top, using spin on glass as a space holder. In our work nontapered nanowires were utilized and a durimide technology was adopted to form the device isolation and electrical contacts. The size and the location of a template and hence the device area are defined by optical lithography. Nanowire based top-contacted pn-diodes were fabricated with n-type doped GaAs-substrate serving as n-type part of the diode and zinc doped nanowires serving as p-type part. Strong band-gap electroluminescence emission from pn-diodes was demonstrated, yielding a proof of successfully formed pn-junction between substrate and the nanowires. Experiments and results For the top-contact process en existing hetero-bipolar transistor mask set was implemented. The device fabrication starts with 300 nm Ti/Ge thick alignment marks fabricated on a (111) n- GaAs substrate. Since the emcon layer in the existing HBT 03 mask set used for this step contains besides of alignment marks also emmiter stripes, which are unnesessury in the top-contact process, part of the sample was covered with an UV-film. Only covered part of sample can be later used for the top-contacted structures. Ti/Ge was chosen instead of Au in order to prevent wire growth in on the alignment marks. During the next step prestructered fields for the nanowire growth are fabricated via optical lithography using the bscon layer in the HBT 03 mask set and evaporation of 2,5 nm Gold. For the VLS growth, an ensemble of seeds is produced by an annealing process during 5 min at 600 C, which transfers an Au film into droplets forming a nano-scaled template. The disadvantage of this method is that the seeds are not monodispers but have different diameters. Futher works on this field are necessary to produce monodispers growth-seeds. Next, p-doped GaAs nanowires were grown employing low-pressure metal-organic vapour phase (MOVPE) epitaxy. Diethylzinc (DEZn) was used for the p-type doping. The growth experiments were performed at 400 C. For the presaturation of gold seed with zinc Diethylzinc (DEZn) was supplied to the reactor together with TBAs for 2 minutes before growth. The V/III ratio of 5 as well 19 as the II/III ratio of 0.004, corresponding to the hole concentration of 2 10 was kept constant in all experiments.

63 Device and Circuit Processing 57 In next step contact to the substrate is produced. To define the position of the contact via optical lithography the cocon layer of the HBT 03 mask set was used. Ge/Ni/Ge/Au (5/10/10/600 nm) was chosen as metalisation (c. f. 1). Fig. 1 SEM-image of GaAs nanowire field together with the contact to the substrate A series of annealing experiments was carried out to improve the contact properties. Figure 2 shows IV curves between two substrate contacts fabricated with different annealing steps. Fig. 2 IV curves mesuared between two substrate contacts. Green curve: without annealing step, blue curve: after annealing step of 30 sec at 360 C, black curve: after annealing step of 30 sec at 400 C. The best annealing parameters were found to be 30 seconds at 400 C. Next, a flattening durimide layer was deposited by spin-on coating, to form a space holder separating top contact from the substrate. With oxygen plasma the durimide is etched down until the whisker top is got free while the durimide still provides isolation of the substrate (c.f. 3).

64 58 Bi-Annual Report 2008 /2009- Solid-State Electronics Department Fig. 3 SEM-image of GaAs nanowire field covered with durimide and ethed with oxygen plasma untill the nanowire tips got free. Finally a Pt/Ti/Pt/Au (10/10/25/400 nm) metallization was patterned to form the contacts to the device (c.f. 4). B E K a b Fig. 4 a) Schematics and b) an SEM-image of the top contacted GaAs nanowire field. To prove the functionality of the pn-junction IV curves were measuared between the nanowire top contact and the contact to the substrate (c.f. 5a). As expected IV curve has a diode-like form and a diffussion voltage of 1,3 V, which comes close to the bandgap of galliumarsenide. a b Fig. 5 a) IV curve of the nanowire based top-contacted pn-diodes b) Electroluminescence spectra taken at 5K for different currents.

65 Device and Circuit Processing 59 Low temperature electroluminescence measurements on the bonded nanowire based top-contacted pn-diodes yielded a bandgap peak, which scales with the current (c.f. 5b ). The origine of the schoulder peak should be futher investigated in detail. It is noteworthy, that the hetero-bipolar transistor mask set turned out to be bedly sutable for the top contact design because of the internal short sircuit, that was not taken into account while planning the process. For this reason an another mask set was disigned for the top contact process. Conclusion: In summary, pn-diode was fabricated from the top-contacted free-standing wires. An existing HBT 03 mask set was implemented for the top-contact process and turned out to be unsuitable for the flawless functioning of the device. By cutting off the conductive pass from the contact pads creating the short cut expected functionality of the pn-junction was achieved. Measured IV curve had a diode-like form, current of 2 ma at 2 V and a diffusion voltage of approximately 1,3 V, which comes close to the bandgap of galliumarsenide. Strong band-gap electroluminescence emission from bonded nanowire based top-contacted pn-diodes was demonstrated. References: [1] K. Haraguchi, T. Katsuyama, K. Hiruma, and K. Ogawa; Growth GaAs p-n junction formed in quantum wire crystals, J. Appl. Phys. 60, 745, 1992.

66 60 Bi-Annual Report 2008/ Solid-State Electronics Department Layout and Technology for Coplanar Contact Pattern of Nanowire Field-Effect Transistors Student Scientist B. Li K. Blekker, B. Münstermann Introduction Nanowire field-effect transistors have already proven their excellent DC characteristics [1], and are also expected to have a particularly good high-frequency (HF) potential. However, the research on InAs nanowire field-effect transistors (NW-FET) has just been started and, therefore, is still in a very early stage [2]. Both the extremely low signal power and the small intrinsic gate capacitance compared to the relatively large parasitic capacitances of the contact pattern cause enormous challenges. In addition, a precise deembedding, subtracting the parasitic contributions from the measured signal, is essential for a detailed study on the HF-characteristics of a NW-FET. In this report, the optimization of coplanar contact pattern for the high-frequency characterization of nanowire transistors is shown. Experimental and Results In order to minimize the parasitic capacitances various pad layouts were designed and processed by means of electron beam lithography and metal evaporation. The scattering parameters were analyzed, both from simulation using Advanced Design Systems and from RF measurements of the realized structures, respectively. In order to extract the parasitic elements from the scattering parameters, small signal equivalent circuits were developed and utilized. The original layout M11 (see Fig. 1) was systematically changed. By comparing the different structures, we could highlight that the geometric changes may cause a remarkable decrease of the parasitic elements. This investigation was focused on reducing the input-to-output capacitance, expected to be crucial for the NW-FETs. As a result of the optimizations, the input-to-output coupling capacitance C io of the contact pattern was reduced to the half compared to the original layout M11 (see Fig. 1 M4cds). This was achieved not only by reducing the size of the gate and the drain pads, but also by increasing the size of the source pads for a stronger electromagnetic shielding between input and output. In addition, InAs nanowire FETs have been fabricated using the optimized contact pattern. InAs nanowires were transferred on a GaAs carrier substrate with a SiN x layer on top. Both the contact pattern and the inner electrodes were processed by means of electron beam lithography and metal evaporation. SiNx gate dielectric was deposited at room temperature. In order to achieve a signal power as high as possible, self-aligned multi-finger gate contacts (see Fig. 2 a) were used. Fig. 2 b shows one of the processed nanowire field-effect transistor with the contact pattern M6. For the first time, the Cascade-Open-Short-Thru (COST) deembedding [3] was used on InAs nanowire FETs. In contrast to earlier studies, we succeeded in extracting the current gain. A current gain cut-off frequency of about 500 MHz (see Fig. 3) and maximum oscillation frequency f max of above 1 GHz (see Fig. 3) were achieved for long channel devices.

67 Device and Circuit Processing 61 3,0 2, Cio [ff] at 20 GHz 2,0 1,5 1, ,5 0,0 M11 M33a M4cds M6 Important pad structures Fig. 1 Input-to-output capacitance C io of different pad structures [M11 is the original contact pattern] extracted from measured S-Parameter (a) (b) Fig. 2 Nanowire field-effect transistor: (a) Layout of a NW-FET with two-finger self-aligned gate contacts. (b) SEM Micrograph of a NW-FET with pad structure M6

68 62 Bi-Annual Report 2008/ Solid-State Electronics Department V ds = 1V V gs = 0.2V h 21 [db] MSG[dB] E8 1E9 1E10 f / Hz Fig. 3 Current gain and Maximum Stabile Gain of an InAs NW-FET Outlook In order to further reduce the parasitic capacitances other substrates with a smaller dielectric constant, e.g. silicon substrate with a silicon oxide layer, should be used. And it s recommended that attaching more than two gate fingers on the nanowire increases the signal power significantly. This requires appropriate technologies to realize the Source-Air-Bridge, which can accommodate more transistors in a rather short nanowire. References [1] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, F.-J. Tegude; High Transconductance MISFET With a Single InAs Nanowire Channel ; Electron Device Letters, IEEE Volume 28, Issue 8, Aug Page(s): [2] K. Blekker, Q.-T. Do, A. Matiss, W. Prost, F.-J. Tegude; High Frequency Characterisation of Single InAs Nanowire Field-Effect Transistor ; IPRM 2008 [3] M.-H. Cho, G.-W. Huang, C.-S. Chiu, K.-M. Chen, A.-S. Peng, Y.-M. Teng; A Cascade Open-Short-Thru (COST) De-Embedding Method for Microwave On-Wafer Characterization and Automatic Measurement ; IEICE Transactions on Electronics 2005 E88-C(5): , Mai 2005.

69 Device and Circuit Processing InAs Nanowire MISFET with Al 2 O 3 Gate Dielectric Scientist K. Blekker, W. Prost T. Mizutani (Nagoya University, Nagoya, Japan) Introduction Recently, III/V nanowire have demonstrated ground breaking performance [1, 2]. InAs nanowire MISFET are exhibiting a high current density I d /D 3 A/mm), and a transconductance of g m /D 2 S/mm normailized to the diameter D of the wire [2]. InAs has an extremly low bandgap with a carrier accumulation at the surface such that an insulting thin film as a gate dielectric is indispensable. The deposition of the insulating film has to be carried out at low temperatures in order to avoid a damage of the critical InAs surface. We previously studied room-temperature depsotion of SiN x using an ECR-CVD system [3] and in collaboration with Werner Keune et al. MgO deposited by MBE [4]. The SiN x gate dielectrics enables the hightest gain but it suffers from severe hysteresis effect in the I-V characteritics. The MBE method reduces the hysteresis at the expense of high deposition efforts but also degrades the transcondcutance of the device. In this study we have investigated Al 2 O 3 deposited by atomic layer depositon as a gate dielectric. The deposition has been carried out at the University of Nagoya [5, 6]. In this report preliminary results of this study are presented. Sample preparation Fig. 1 SEM micrograph of the gate region of a NW MISFET (M4053a2) fabricated by FASA. The shadow at the metal/nanowire edge may indicate the thickness of the Al2O3 gate dielectric.

70 64 Bi-Annual Report 2008/ Solid-State Electronics Department InAs nanowires were grown using the VLS mode in an MOVPE apparatus using Au colloidal nanoparticles of about 50 nm diameter (M4053). The wires were shaved from the growth substrate and transferred to a Silicon substrate with a 4 µm thick SiO x cap layer using the field-assisted selective deposition process (FASA). This sample (M4053a3) was delivered to Nagoya University, Department of Quantum Engineering (Prof. T. Mizutani) for atomic layer deposition (ALD) of 30 nm Al 2 O 3 at a temperature of 250 C [5]. In addition, an InP-based heterojunction FET sample (M3966b2) was delivered. The samples were covered with 30 nm SiN x by ECR-CVD at 300 K for comparison. After the deposition of the dielectric a 0.5 µm and a 1 µm long gate was defined by ebeam-lithography. In Fig. 1 the gate region of a fabricated nanowire MISFET with Al 2 O 3 gate dielectric is shown. In this case 4 wires are connecting the source and drain contact. DC characteristics Both types of gate dielectrics result in functional transistors. The pinch-off of both transistors is somewhat degraded. The threshold voltage of the MISFET M4053a2 with Al 2 O 3 gate dielectric is severely shifted to negative bias (~ -20 V) while the sample with SiN x exhibit the expected threshold bias of about V th ~ V. The reason for the V th shift is presently unknown. The MISFET with Al 2 O 3 gate dielectric exhibits an extremely high breakdown voltage in excess of 20 V with negligible gate current (< 3 6 V) indicating excellent isolation properties. The purpose of the study is to compare the transient behaviour of nanowire MSFET with Al 2 O 3 versus SiN x gate dielectric. As an initial study, the measurement mode of the HP 4145B parameter analyzer has been varied during the take up of the transfer characteristics (cf. Fig. 2). There are three measurement modes (short, medium, and long) available indicating a different waiting time at each measurement point. In Fig. 2b the well known problem of SiN x gate dielectric is shown: the transfer characteristic severely depends on the measurement speed which is related to a low charging speed of traps in the gate dielectric or at its interface. The sample with Al 2 O 3 dielectric exhibits almost no variation regardless of the drain bias selected. In this respect the main goal of the project has been reached. drain current I D [µa] a) Al 2 O 3 M4053 a2 V DS = 1.0 V V DS = 0.5 V speed: short medium long gate-source voltage V GS [V] b) SiN x M4053 a gate-source voltage V GS [V] a) b) Fig. 2 Transfer characteristics of NW MISFET with different gate dielectric consisting of up to 10 parallel wires: a) Al2O, b) SiNx drain current I D [µa] V DS = 0.5 V speed: short medium long

71 Device and Circuit Processing 65 RF characteristics RF measurements were performed on a HP 8510 network analyzer using an on wafer testset for frequencies up to 50 GHz. From measured scattering parameters the maximum stable gain (MSG) and current gain (h 21 ) are extracted. The NW MISFET with about 1 µm gate length and an Al 2 O 3 gate dielectric exhibit despite the degraded threshold voltage a MSG of 10 db at 1 GHz while the cut-off frequency of current gain reaches f T = 12 GHz (cf. Fig. 3a, b). These data are not the best obtained but they are clearly comparable to data from NW MISFET with SiN x gate dielectric. 30 h 21 a) Al 2 O 3 L G = 1 µm 30 h 21 b) SiN x L G = 0.5 µm gain [db] MSG M4053 a2 gain [db] MSG M4053 a3 MAG MAG frequency f [GHz] frequency f [GHz] a) b) Fig. 3 Maximum stable gain (MSG) and current gain (h 21 ), and maximum available gain (MAG) extracted from measured scattering parameters with carefully de-embedded contact pattern of the NW MISFET with (a) Al 2 O 3 (M4053a2) and (b) SiN x gate dielectric. Discussion According to Fig. 4, the very negative threshold voltage of the sample with Al 2 O 3 gate dielectric does not degrade the rf-performance despite the much lower transconductance g m. According to the basic formula: gm (1) ft, 2 C gs we may assume that the gate capacitance C gs is also much smaller in order to maintain the current gain. A thicker Al 2 O 3 gate dielectric and/or a severe change of the dielectric constant causing 20 V threshold shift is also very unlikely. Presently, we assume that the ALD process using oxygen from a H 2 O precursor may cause an Indiumoxide (InO x ) surface layer on the InAs nanowire. InO x which is electrically conductive at very low mobility. Thus a higher density of states might be at the wire surface which may degrade the threshold voltage. Therefore, further measurements on the MIS- HFET sample shall be carried out in order to clarify the origin of the problem and to elaborate a solution.

72 66 Bi-Annual Report 2008/ Solid-State Electronics Department The transient behavior of the investigated MISFET with Al 2 O 3 is excellent. Therefore, we put much hope on this approach and are highly motivated to solve the remaining problem of threshold voltage shift. Acknowledgement: The support from Prof. Koichi Maezawa towards this collaboration is gratefully acknowledged. This work has been supported by the joint Japanese (JST) and German (DFG) programme on nanoelectronics. References: [1] T. Bryllert, L.-E. Wernersson, L.E. Froberg, L. Samuelson, Vertical high-mobility wrapgated InAs nanowire transistor, IEEE Electron Device Letters, vol. 27, pp , [2] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, and F.-J. Tegude, High transconductance MISFET with a single InAs nanowire channel, IEEE Electron Device Letters, vol.28, no.8, pp , August [3] Q. T. Do, K. Blekker, I. Regolin, E. Schuster, R. Peters, W. Prost, and F.-J. Tegude, Magnesium oxide (MgO) as gate dielectric for n-doped single InAs nanowire field-effect transistor, 7th Topical Workshop on Heterostructure Microelectronics, Japan, August [4] A. Wiersch, C. Heedt, S. Schneiders, R. Tilders, F. Buchali, W. Kuebart, W. Prost, F. J. Tegude, Room-temperature deposition of SiN x using ECR-PECVD for III/V semiconductor microelectronics in lift-off technique, J. Non-Crystalline Solids, (1995) [5] E. Miyazaki, Y.Goda, S. Kishimoto, and T. Mizutani; AlGaN/GaN MOSFETs with Al2O3 Gate Oxide Deposited by Atomic Layer Deposition; Comparative Study,, Topical workshop on Heterostructure Microelectronics, Nagoya, [6] S. Sugiura,, Y. Hayashi, S. Kishimoto, T. Mizutani, M. Kuroda, T. Ueda, T. Tanaka; Fabrication of normally-off mode GaN and AlGaN/GaN MOSFETs with HfO2 gate insulator Sol.-St. Electronics, 54(1) p.79-83, 2010.

73 Device and Circuit Processing Fabrication of Nanowire-Devices Using Field-Assisted Self Assembly Student Scientist O. Benner K. Blekker Introduction Due to their one-dimensional geometry nanowires offer unique electrical properties and open up new possibilities for the production of electronic components. In order to contact a large number of nanowires by means of optical lithography a controllable positioning of nanowires is mandatory. This is possible by dielectrophoresis, which describes the manipulation of neutral particles in a liquid medium using a non-uniform alternating current (AC) electric field. In such an electric field a dipole moment is induced in the nanowires due to charge separation along the nanowires [1]. Because of the dielectrophoretic force the nanowires align with the electric field, move in direction of increasing field strength and finally bridge the electrodes [2]. In this report the process of fieldassisted self assembly for nanowires of various material systems is proven. Experimental and results In the field-assisted self assembly nanowires are largely aligned parallel to each other and placed at predefined locations, which are given by pairs of electrodes. The electrode structure was processed by means of optical lithography and metal evaporation. Then a 30 nm thick, insulating SiN x layer is deposited by chemical vapor deposition on the entire surface of the sample. In order to deposit the nanowires an AC voltage with an amplitude of 10 V and a frequency of 10 khz was applied to the electrodes. Thus InP, GaAs and InAs / InP core / shell wires could be controlled positioned with the help of field-assisted self assembly. Figure 1 shows optical micrographs of aligned nanowires for the used material systems. Fig. 1 Optical micrographs of aligned InP (left), GaAs (middle), InAs/InP core/shell (right) nanowires (electrode width: 10 µm) After the nanowires were successfully aligned, they must be contacted. First, the source and drain contacts were processed for all samples (see Fig. 2). Afterwards the InP and GaAs nanowires were characterized by I/V measurements. Therefore a voltage was applied to the two source contacts and the current through the nanowires was measured.

74 68 Bi-Annual Report 2008/ Solid-State Electronics Department S S D Fig. 2 Optical and SEM micrograph of GaAs nanowires provided with source and drain contacts (electrode width: 10 µm) a) 7 b) M Wg10_dds3_ current I S / na Voltage V S / V resistance / kohm M4018 dds number of wires Fig. 3 I/V characteristic of a single InP nanowire (a), measured resistance of the GaAs nanowires versus number of wires (b) In figure 3 (a) an I/V characteristic of a single InP nanowire is shown. The course is nonlinear and only very low currents are measured. This suggests that the InP nanowires were not sufficiently doped. Thus it appears that the process of field-assisted self assembly works well, even for weakly doped nanowires. Figure 3 (b) shows the measured resistance values of the GaAs nanowires over the number of wires. The result is consistent with the expectation of parallel resistors. The data variation can be explained by the different diameters of the nanowires. With an increasing number of nanowires, the variation decreases. Therefore, a large number of nanowires is required to avoid variations of the component properties. The InAs / InP core / shell nanowires were also provided with a gate contact (see Fig. 4). These nanowire field-effect transistors (NW-FETs) were characterized with the help of transfer and output characteristics. Figure 5 shows the characteristics of a nanowire FET with 11 wires of 50 nm to 200 nm in diameter. The transfer characteristic describes a counter-clockwise directed hysteresis. From the characteristic a maximum transconductance of g m = 240 µs can be determined. In the output characteristic a drain current of 450 µa is achieved.

75 Device and Circuit Processing 69 S G S D Fig. 4 SEM micrographs of InAs / InP core / shell nanowires provided with gate contact (electrode width: 20 µm) drain current I D / µa M nm Wg20 dds3_3_ gate-source voltage V GS / V drain current I D / µa M nm Wg20 dds3_3_8 +1 V 0.75 V V GS V -0.5 V drain-source voltage V DS / V a) b) Fig. 5 Transfer (a) and output (b) characteristics of an InAs / InP core / shell NW-FET Conclusion In summary, with the help of field-assisted self assembly nanowire-devices of different material systems have been fabricated and characterized. I/V characteristics demonstrated on the one hand that the InP nanowires were weakly doped, which proves that the procedure of the field-assisted self assembly works well for low-doped nanowires. On the other hand it was shown that a large number of nanowires is required in order to minimize data variation. Furthermore nanowire field-effect transistors have been successfully fabricated of InAs / InP core / shell nanowires. References: [1] Peter A. Smith, Christopher D. Nordquist, Thomas N. Jackson and Theresa S. Mayer; Electric-field assisted assembly and alignment of metallic nanowires, Appl. Phys. Lett., 77(9) [2] A. Motayed, M. He, A. V. Davydov, J. Melngailis, S. N. Mohammad; Simple model for dielectrophoretic alignment of gallium nitride nanowires, J Vacuum Sci. & Techn. B 25(1) p , 2007.

76 70 Bi-Annual Report 2008/ Solid-State Electronics Department n-zno Nanowire Field Effect Transistors Scientist Student: K. Blekker, M. Lange, M. Lorenz.(Universität Leipzig, AG) M. Grundmann, René Richter ZnO nanowires are promising candidates for short-wavelength optoelectronic devices, e.g. lightemitting diodes (LEDs) and laser diodes (LDs). For future device applications, fundamentals like doping type and carrier mobility have to be investigated. In this work, transport data of n-doped ZnO nanowires was preliminary studied by both, transmission line type measurements and transistor characteristics. The ZnO nanowires of this study were grown on a-plane sapphire by pulsed laser deposition (PLD). For device fabrication, nanowires were transferred onto highly insulating Si/SiO 2 substrates. All contacts were patterned using optical lithography followed by Ti/Au evaporation. 30 nm silicon nitride (SiN x ) was deposited as gate isolation layer and for passivation of the ungated nanowire surface. Thereby, the transconductance of the ZnO nanowires was increased about five times compared to transmission line type measurements carried out before SiN x deposition. Even for passivated ZnO nanowires, the contact resistance only slightly contributes to the total resistance. Fig. 1 (left) shows the output characteristics of a transistor with two ZnO nanowires of about 100 nm in diameter. All fabricated devices exhibit typical n-channel behaviour. The electron mobility was estimated to about 600 cm²/vs (cf. [1]). In addition, a remarkable on/off ratio of more than 10 7 and a subthreshold-swing of down to 120 mv/dec was achieved (Fig. 1 right). drain current I D [A] 70µ V GS = -1 V V 60µ steps 0.5 V 50µ L G = 1.2 µm 40µ 30µ 20µ 10µ drain current I D [A] 10µ 1µ 100n 10n 1n 100p 10p V DS = 2 V p drain-source voltage V DS [V] gate-source voltage V GS [V] Fig.1. Output characteristics of a ZnO nanowire transistor (left) and transfer characteristics (right). The inset shows one of the fabricated FETs. References [1] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, and F.-J. Tegude, High transconductance MISFET with a single InAs nanowire channel, IEEE Electron Device Letters, vol.28, no.8, pp , 2007.

77 Bi-Annual Report 2008/ Solid-State Electronics Department Device and Circuit Simulation, Measurement and Modeling

78 72 Bi-Annual Report 2008/ Solid-State Electronics Department RF Measurement of High Frequency pin-photodetectors Student Scientist G. Keller I. Nannen and A. Poloczek Introduction The development of High Speed Photodiodes is an important topic to increase the data rates in modern glass fiber communication systems. This work deals with the build-up and calibration of a measurement set-up in the frequency range up to 20 GHz. This way, the frequency response of PINphotodetectors is analysed. As an aside effect the coupling efficiency of lensed fibre instead of tapered was measured. Measurement Setup SMU Lasersource + Attenuator SMU Signalgenerator E8241A Bias-T 40GHz EAM DUT rf-probes Bias-T Spectrum Analyzer E4448A Reference pin-diode 83440D Fig. 1 RF-measurement set-up Figure 1 shows the block diagram of the measurement setup used. The high frequency optical signal is generated by an electro-absorption-modulator (EAM). This element modulates a constant laser source in dependence of an electrical signal. This configuration is available for both typical wavelengths (1550 nm and 1310 nm) for optical communication systems. The modulators exhibit a cut off frequencies of 10 GHz for 1550 nm, and of 40 GHz for 1310 nm. Further on, the frequency limitation of the signal generator is 20 GHz. The PIN-photodetectors as the device under test (DUT) must be contacted optically and electrically. The optical coupling is performed with a micro manipulator equipped with a lensed or tapered fibre. The electrical contact to the DUT is provided by a microwave probe with a Ground-Signal-Ground (GSG) configuration. These probe tips can be used for frequencies up to 40 GHz. The detection of the signal is done by a spectrum analyser. Calibration procedure The normally used open/short/thru calibration elements are not available for optoelectronic measurement set-up [1]. Instead, calibration measurements are done up to 50 GHz using a well

79 Device and Circuit Simulation, Measurement and Modeling 73 know reference diode. For this purpose the detector diode Agilent 83440D with cut off frequency of 27 GHz is used. Software One of the mayor topics of this work was the development of a user friendly software using the graphical programming environment LabView. The developed user interface of the measurement program is shown in figure 2. All important functions like calibration and performing a measurement are implemented in order to alleviate the handling. The use of other reference elements in the future is enabled because reference data can be loaded from different data files. Fig. 2 User interface of the Measurement Software Measurement Results The measurement results of an array of four pin diodes are given in figure 3. The RF measurement was performed at 1310 nm. The array was biased with 5 V to drive the pin diodes to the correct working point.

80 74 Bi-Annual Report 2008/ Solid-State Electronics Department An example of a measurement can be seen in fig. 3. The pin diodes work excellent with high cut of frequencies beyond 10 GHz and high homogeneity. Only one pin diode of four showed a cut off frequency lower than 10 GHz. M3869A Frequency Response Response / db G8B1_DO1 G8B1_DO1 G8B1_DU1 G8B1_DU2-20 G DC Supply G S G Frequency / GHz Fig. 3 Measured frequency response of a pin-array. The coupling efficiency of lensed fiber instead of tapered was also investigated. The measurements were performed on pin-diodes with different diameters down to 12 µm. These measurements showed that the coupling efficiency is almost independent of the type of fiber used. In conclusion the lensed fiber can be used instead of the tapered one, what will be more cost effective. Summary A measurement setup for calibrated optical/electrical measurements was build. A program was developed such that the measurement and the calibration can done easily. References [1] D. Hale, F. Williams Calibrated Measurements of Optoelectronic Frequency Response IEEE Transaction on microwave theory and techniques, vol. 51, No. 4, April 2003

81 Device and Circuit Simulation, Measurement and Modeling Optical-Detector-Circuitry Using Staggered pin-photodiodes for All-Optical-Input Gate Scientists: Technical Assistant: A. Poloczek, K. Blekker H. Barbknecht Introduction Today s high-capacity optical communication networks use multiple wavelengths to increase the maximum transmission data rate. The wavelength division multiplexing technology (WDM) uses both important communication wavelengths = 1.3 µm and = 1.55 µm for data transmission. The simultaneous detection of two signals on separate communication wavelengths via a single device was already a matter of interest three decades ago [1]. We propose an optical detector circuitry based on the monostable-bistable-transition-logic-element concept (MOBILE) [2] using a dual wavelength detector [3]. Here, clock and data signal are streamed simultaneously through a single fiber into the detector circuit. Thus, new application facilities are opened up without the need of clock recovery. equivalent network channel 1 =1.3µm fiber 1 upper contact channel 2 =1.55µm upper absorber: "InGaAsP" center contact SEM-micrograph lower absorber: "InGaAs" lower contact InP - substrate Detector Concept Fig. 1 Concept illustration of the wavelength-selective receiver Our proposed wavelength-selective detector (WS-detector) contains two stacked PIN-diode layer sequences with a common center terminal. By the use of quaternary material with a band-gap of

82 76 Bi-Annual Report 2008/ Solid-State Electronics Department W g,ingaasp = 0.85eV, the upper absorption layer is designed to be transparent for the lower energy wavelength ( =1.55µm) and absorptive for =1.3µm. The lower absorption layer consists of lattice matched InGaAs and absorbs both wavelengths. Thus, the discrimination between the two signals is essentially managed by the bandgap and the thickness of the quaternary InGaAsP layer. By illuminating the device with both wavelengths transmitted through a single fiber, the WS-detector performs an oe-conversion and separates the incoming data on two electrical channels. The development progress of the device is traceable with the last annual reports of the department. Currently, we present the device RF-performance in figure 2. The depicted frequency response measurements prove an useful RF-performance up to 10 GHz for a 12 µm diameter device. 0 mag [db] dB cutoff d=12µm / RF down d=12µm / RF up d=21µm / RF down d=21µm / RF up d=30µm / RF down d=30µm / RF up frequency [GHz] Fig. 2 The frequency response of wavelength-selective detectors for upper (InGaAsP, black) and lower (InGaAs, red) diode using different device diameters All-Optical-MOBILE Because of its simple design, the MOBILE gate is still a very interesting approach for digital signal processing. It offers the functionality of a D-flip flop by using only two resonant tunnelling diodes (RTD) in series connection. The concept upgrade by introducing a photo element for data detection was already demonstrated one decade ago by [4]. We have developed a solution for a complete RFdrive of the MOBILE gate, where data and clock are detected by the WS-detector. The circuit design is shown in figure 3. The 1.55 µm channel of the WS-detector is used for data detection and is connected directly with the MOBILE input node. The clock is transmitted using =1.3 µm. The generated photo current on the 1.3 µm channel is transformed to a voltage swing using a simple HFET circuit which clocks the MOBILE gate. Only electrical DC-power supply is necessary for circuit operation. We have fabricated the circuit described above by growing the epitaxial layers

83 Device and Circuit Simulation, Measurement and Modeling 77 with MOVPE on InP, where we started with the HFET, followed by RTD layers and the WSdetector on top. The total layer thickness is 2.3 µm. Fig. 3 All-Optical-MOBILE design (left) and SEM-micrograph of a realized circuit (right) The processing was performed using optical lithography and electron beam exposure for critical structures (HFET-gate, upper RTD-contact). Vertical structuring was carried out by wet chemical etching and by plasma technology for RTD processing, in order to achieve best possible aspect ratio for accurate device characteristics. A circuit micrograph captured by SEM is depicted in figure 3. Circuit Measurement Results RESET RESET RESET RESET RESET SET SET SET SET SET signal level [50mV / div] opt. "1" opt. "0" 0,0 0,5 1,0 1,5 2,0 2,5 time [ns] Fig. 4 Measured timing-diagram of a realized All-Optical-MOBILE circuit at 2 GHz

84 78 Bi-Annual Report 2008/ Solid-State Electronics Department Figure 4 demonstrates the rf-switching performance of a realised detector circuit at a clock frequency of 2 GHz. The DC-voltage supply during the measurement was adjusted to V DD = 2V and corresponds completely with the simulation results. According to our measurement feasibility, we modulated a = 1.3 µm CW-laser by am EAM and coupled a second = 1.55 µm CW-laser source without modulation on the same fiber. The two curves depicted in figure 4 show the circuit behaviour if the = 1.55 µm CW-laser is switched on (blue) and off (yellow). This result proves the appropriate working of the oe-clock conversion and the correct sampling of the incoming data. The inversion of an optical 1 to an electrical 0 and vice versa is due to the buffer design used. Conclusion Within the last period we have demonstrated the rf-performance of fabricated WS-detector devices up to 10 GHz and potential beyond. Further on, we have developed an application circuit, which proves the selective detection of two wavelengths at a modulation frequency of 2 GHz. The developed circuit is a successful advancement of the MOBILE concept for fiber based digital communication systems. References [1] J. C. Campbell, A. G. Dental, T. P. Lee, C. A. Burrus, Improved Two-Wavelength Demultiplexing InGaAsP Photodetector, IEEE Joutnal of Quantum Electronics, Vol. QE-16, No. 6, June 1980 [2] K. Maezawa, T. Mizutani, A new resonant tunneling logic-gate employing monostablebistable transition, Jpn. J. Appl. Phys. Lett. v [3] A. Poloczek, W. Wang, J. Driesen, I. Regolin, W. Prost, F.-J. Tegude, Concept and Development of a New MOBILE-Gate with All Optical Input, German Microwave Conference, Germany, 2006 [4] T. Akeyoshi, N. Shimizu, J. Osaka, M. Yamamoto, T. Ishibashi, K. Sano, K. Murata, E. Sano, Optoelectronic logic gate monolithically integrating resonant tunneling diodes and unitraveling-carrier photo diode, Proc. International Conference on Indium Phosphide and Related Materials, 1998

85 Device and Circuit Simulation, Measurement and Modeling PINIP / NIPIN Layer Sequences and Crosstalk Properties of the Wavelength-Selective Detector Scientists : A. Poloczek, B. Münstermann Introduction Our efforts to develop a single-spot and microwave suitable wavelength-selective receiver, which works at wavelengths within the second optical window, were discussed in recent annual reports. Recently, we reported on the RF-performance up to 12 GHz and a sucessful drive of an monolithically fabricated all-optical MOBILE circuit using a WS-detector with 12 µm active diameter. This contribution summarizes the results on electrical crosstalk investigations between the both device channels in consideration of two possible layer sequences PINIP and NIPIN. Device Technology "PINIP"-layerstack "NIPIN"-layerstack d active p-ingaas:zn 50nm n-ingaas:si 50nm nid-ingaasp 600nm =1.3µm i-ingaasp 600nm n-inp:si nid-ingaas 100nm 600nm =1.55µm p-ingaas:zn i-ingaas 50 / 200nm 600nm p-ingaas:zn 200nm n-ingaas:si 200nm Fig. 1 Investigated WS-detector layer sequences The investigated layer stacks were grown lattice matched on s.i.-inp substrates by an AIX200 MOVPE system with non-gaseous source configuration. Two layer concepts with layer data are depicted in figure 1. Depending on further device merging (e.g. HBT) or circuit topology, a WSdetector based on a PINIP or a NIPIN layer stack may be preferred. Our realized PINIP device utilizes a fully transparent InP center contact layer in order to prevent absorption there. This approach is not feasible for the NIPIN device because of the hole-blocking effect due to the valance band discontinuity at the PI-interface for both channels. The situation is depicted in figure 2 via calculated band-diagrams for a NIPIN layer-sequence using both, transparent p-inp and absorptive p-ingaas as center contact material. It is obvious, that the remaining energy barrier inside the valance band for InP contact material affects the transport of the generated holes so that the depletion of the absorption region after an illumination event is slowed down. Thus, the expected hole transit time may negatively influence the device cutoff frequency. For this reason, we decided to use an InGaAs homojunction here. To achieve best possible ohmic contact behavior, all contact layers exhibit the highest doping concentration accessible with our epitaxy. The absolute

86 80 Bi-Annual Report 2008/ Solid-State Electronics Department Energy (refering to vacuum level) [ev] n-ingaas nid-ingaasp nid-ingaas A B p-ingaas p-inp current blocking n-ingaas s.i. InP W C W V W C -5.5 no blocking W V Fig. 2 crystallographic direction Calculated band-diagrams for a NIPIN layer-sequence using p-inp (A) and p-ingaas (B) as center contact material values are N D = cm -3 with silicon and N A = cm -3 for InGaAs and InP doped with zinc. We decided to use zinc as p-dopant because, when using carbon, a 10 times reduction of p-doping is observed within the buried p-layer and the forming of high quality ohmic contacts is prevented. The device processing was performed using standard wet chemical etching and UV300 optical lithography arranging a triple-mesa formation with three ring-contacts for each doped layer. Crosstalk Properties The crosstalk between the two device channels is a very important issue for application purposes. It has an frequency independent optical origin and an electrical contribution which raises at higher frequencies. In our case, the claim for a lowest possible crosstalk is desired only for one of the both channels. Our objective was to demonstrate an threshold logic gate without the need of electrical rfinput, i.e. using optical data as well as clock input signals. Therefore, a high-quality detection of the clock signal is essential. A high crosstalk on the data channel can be handled by an adequate choice of the threshold value of the subsequent logic gate. Thus, the achieved optical crosstalk results of C upper diode = -21dB and C lower diode = -0.5 db satisfy our desired application. The high crosstalk inside the lower diode is mainly dedicated to the relatively small layer thickness of InGaAsP (d InGaAsP = 600nm). If necessary, it can be clearly improved by increasing the layer thickness of the upper absorber. In this case, the process technology has to be adapted in order to handle the increased device topology. Figure 3 (left) shows the microwave transmission behavior for both layer stack concepts. The scattering parameter S21 was measured up to 40 GHz, while both device diodes were reverse-biased at V bias = -2V. Starting with a negligible transmission near DC, the value saturates at approximately 10 GHz. Furthermore, in contrast to the NIPIN sequences the PINIP device exhibits the lowest transmission with -30dB, clearly. This is related to a lower depletion of the center contact layer for the PINIP device caused by different maximum doping concentrations for p and n.

87 Device and Circuit Simulation, Measurement and Modeling 81 This results demonstrates the high importance of the common center contact layer. Depletion especially 0 NIPIN -10 mag(s21) [db] nm (sim.) 50nm (meas.) 200nm (sim.) 200nm (meas.) 100nm (sim.) 100nm (meas.) port1 port frequency [GHz] s.i. InP s.i. InP PINIP norm 0 db -14dB -28dB -42dB -56dB -70dB Fig.3 Simulated and measured transmission parameters S21 for NIPIN and PINIP devices with center contact layer thickness as parameter (left). Simulated electrical field distribution for both layer sequences at a 10 GHz signal fed to the upper diode (right). combined with low center layer thickness lead to a higher device resistance and to a high electrical channel coupling at frequencies above a few GHz. This behavior was verified by performing 3 dimensional electromagnetic field simulations with an commercial Maxwell-equations solving tool using data from hall measurements and device layout. The simulation results in figure 3 (left) approve the measured behavior. Only a slight deviation within the saturation region for NIPIN is observed which might be related to a deviation of the absolute p-layer thickness in the device. Figure 3 (right) depicts the simulated electrical field distribution inside the WS-detector for both layer stack types. The 10 GHz rf-signal is fed to the upper diode, while the lower is connected to ground via 50 ohms. The high field amplitude inside the lower NIPIN absorber region indicates the microwave crosstalk, clearly. By far, this effect is less evident for the PINIP device because of the higher shielding by the center contact layer. Conclusion A wavelength-selective detector for simultaneous =1.3µm and =1.55µm detection has been developed and characterized with respect to its crosstalk concerning two layer stack concepts. The influence of layer parameters like doping and thickness has been identified on the electrical crosstalk which becomes important for device operation at signal frequencies in monadic GHz range.

88 82 Bi-Annual Report 2008/ Solid-State Electronics Department Physical Simulation of InP-Based Field-Effect Transistors Using Silvaco Atlas Student Scientist B. Betting K. Blekker Introduction With the aid of computer simulations microelectronic devices can be investigated and optimized much easier compared to time- and cost-intensive device processing. However, the physical properties have to be accurately simulated in order to achieve reliable results. The physical simulator Atlas [1], provided by the company Silvaco, meets this requirement. In this work, Atlas will be used to simulate an InGaAs/InP Heterostructure-Field-Effect-Transistor (HFET). The aim will be to optimize the layer stack for a threshold voltage of V T = -0.9 V as required in a current project. In addition, the transconductance and the threshold voltage of a metalinsulator-semiconductor- (MIS-) HFET will be analyzed for different thickness of the insulating layer. Simulation of an InP based HFET Fig. 1 Layout of the simulated HFET (left) with the appropriate band diagram (right) In Fig. 1 the layout of the simulated HFET and the associated band diagram are shown. Due to the heterojunction, the transistor channel is formed by electrons accumulated in a non- intentionally doped layer. In order to calibrate the necessary material parameters, measured data of fabricated devices have been taken as a reference. In addition, the exact geometrical values have been identified using SEM inspection, and uncertainties concerning to the donor layer doping concentration have been assumed. Reducing the doping concentration from cm to cm resulted in further approximation between simulation and measurement characteristics. Later on, this value was verified by Hall measurements. Additionally, model parameter, e.g. mobility and saturation velocity

89 Device and Circuit Simulation, Measurement and Modeling 83 of the electrons, have been adapted by accurate considerations of the output characteristics. In Fig. 2 the comparison of measured and simulated data after the calibration is shown. drain current I D [A/µm] 300µ Vgs = V (0.1 V) 250µ 200µ 150µ 100µ 50µ simulation measurement drain current I D [A/µm] 500µ 400µ 300µ 200µ 100µ V ds = 1 V simulation measurement drain-source voltage V ds [V] gate-source voltage V gs [V] Fig. 2 Comparison of measured and simulated data after calibration: output characteristics (left) and transfer characteristics (right) To reach the required threshold voltage of V T = -0.9 V in variation of the barrier thickness it is necessary to increase the barrier thickness from 12 nm to 18 nm (s. fig. 3 left). This approach leads 1 to the disadvantage that the transconductance is reduced from g m,max = 457 ms mm to 1 g m,max = 416 ms mm. This behaviour is explained by the increasing distance between gate contact and channel. The second approach to reach the required threshold voltage is the adaptation over the doping concentration of the donor layer. In this case it is necessary to increase the doping concentration from1,9 10 cm to 2,8 10 cm. The simulated transfer characteristics are shown in Fig. 3. Fig. 3 Ttransfer characteristics for adaptation over the barrier thickness (left), and adaptation over the doping concentration (right) at V DS = 1V In comparison with the adaptation over the barrier thickness, this approach has the advantage that 1 1 the transconductance increases from g m,max = 457 ms mm to g m,max = 516 ms mm. Besides, RF simulations have demonstrated that a higher donor layer doping concentration increases the transit frequency, whereas a thicker barrier layer results in lower RF performance.

90 84 Bi-Annual Report 2008/ Solid-State Electronics Department Simulation of an InP based MIS-HFET In the second part of this work a MIS-HFET was simulated. The layout is identical with the HFET, but with a silicon nitride (SiN x ) layer between Gate metal and semiconductor. For the SiN x a permittivity of 7 was assumed [3]. Again, for calibration of the material parameters uncertainties concerning the donor layer doping concentration have been taken into account. The best agreement 18 3 between simulation and measurement is reached for a donor layer doping of cm, instead 18 3 the specified value of cm. In addition, interface states between SiN x and the semiconductor have been implemented in the simulation. Best agreement between measured and simulated characteristics was found for an interface state density of cm -2. After calibration, the dependence of the threshold voltage on the SiN x layer thickness has been investigated. Fig. 4 (left) shows the transfer characteristics for a SiN x layer with 25 nm, 20 nm and 15 nm. The simulation shows that the threshold voltage increases linear with decreasing SiN x thickness. Also the transconductance increases for thinner SiN x layers, as shown in Fig. 4 (right). drain current I D [A/µm] 400µ 300µ 200µ 100µ 0 25nm 20nm 15nm V ds = 1 V gate-source voltage V gs [V] transconductance g m [msmm -1 ] 300µ 250µ 200µ 150µ 100µ 50µ 0 25 nm 20 nm 15 nm V ds = 1 V gate-source voltage V gs [V] Fig. 4 Ttransfer characteristics (left) and transconductance (right) for a SiN x layer thickness of 25 nm, 20 nm and 15 nm Conclusion In this study the layer stack of an HFET was modified for a threshold voltage of V T = 0.9 V using the commercial simulation software Atlas. The simulations have demonstrated that the donor layer doping concentrations should be increased instead of the barrier layer thickness. Thereby, a higher transconductance and transit frequency are achieved. The simulations of the MIS-HFET have shown that a reduced SiN x layer thickness results in a linear shift of the threshold voltage to higher values. In addition, the transconductance is increased. References: [1] Silvaco International, Atlas User s Manual, Santa Clara, Juni 2007 [2] F. J. Tegude, Technische Elektronik 1,2, Vorlesungsskript, Universität Duisburg-Essen, 2005 [3] Simone Schneiders, Zum Einfluß der Abscheideparameter auf die dielektrischen Eigenschaften von ECR-PECVD-Siliziumnitrid ; Studienarbeit, Universität Duisburg-Essen, 1994

91 Bi-Annual Report 2008/ Solid-State Electronics Department Modelling of InP Heterostructure Bipolar Transistors (HBT) for Operation in Monolithic Microwave Integrated Circuits Student Scientist G. Keller B. Münstermann Introduction The combination of fast resonant tunnelling diodes and low noise heterostructure bipolar transistors in monolithically integrated microwave circuits (MMIC) is very attractive for circuit development. Therefore accurate large signal transistor models for the frequency range up to 50 GHz are required, to simulate and design analog and digital circuits. This work covers the extraction of modelling parameters based on widespread choice of characterisation methods for DC and high frequency measurements in a wide temperature range from 20 K up to room temperature. To analyse the noise performance additional noise measurements up to 18 GHz have been included. The adapted transistor model Agilent HBT is fitted to a state of the art RTD/HBT technology and then used to design and simulate a HBT/RTD latch based on the current mode logic (CML) concept. Characterisation As a first step a large number of produced HBTs are measured with a fully automatic dc measurement setup to get representative data for the extraction of DC parameters. RF measurements are performed as a second step, which were performed with a HP8510 Network Analyser up to 50 GHz. For de-embedding of parasitic pad structures, on wafer open and short structures are measured and modelled. As last step the devices were investigated in the lowtemperature measurement setup depicted in fig.1 to get information on the temperature shift of modelling parameters and device performance. To condensation on the DUT a vacuum chamber like it s shown in fig. 1b and a closed cycle He cryostat is used. a) b) Fig. 1 a) installed Probe and Calibration Substrate b) schematic of the Probe chamber for low temperature measurements The noise performance of the devices for frequencies up to 18 GHz was tested with an automatic ATN tuner system. A noise fig. test set with an external synthesizer is used to extend the frequency range up to 18 GHz.

92 86 Bi-Annual Report 2008/ Solid-State Electronics Department Measurement results The measured transistors with an emitter area of 20 µm 2 show a DC gain between 30 up to 60 and a transit frequency of 120 GHz even for moderate current densities at the collector of 0.75 ma/µm 2. Low temperature RF measurements show an increasing transit frequency in cause of the lower parasitic resistances up to 150 GHz at 50 K. The noise performance was measured in device operating points typical for low noise applications such as oscillators and shows a noise fig. of 3 db at a frequency up to 18 GHz. Agilent HBT compact model To consider the specifics HBT on III/V material systems, the Agilent HBT model integrated in the advanced design system was used. This model take care of the parasitic diode structure between extrinsic base and collector region, with the topology given in fig. 2. Also the characteristic differences in transit time compared to silicon devices are included so simulation can be appropriate even for high current densities. Fig. 2 Topology of the Agilent HBT Model In fig. 3 the results of the fitting the compact model to the measured data is presented. The simulated large signal model output characteristics are in good agreement with the measured data, as well as measured (blue) and modelled (red) input reflection factor S 11 and the forward transmission factor S 21. a) b) Fig. 3 a) DC output characteristic, b) Scattering-parameters for frequencies up to 50 GHz

93 Bi-Annual Report 2008/ Solid-State Electronics Department 87 Circuit Simulation The performance investigation of the model for digital circuits is done by the simulation of a latch with RTD/HBT-Technology. The circuit used is based on the concept of the current mode logic (CML) presented by Kim [1]. a) b) Fig. 3 CML-Latch circuit (a) and simulation result (b) for a frequency of 3 GHz The circuit core is shown in fig. 4a. To improve output matching an additional buffer stage, realized with an impedance converter is used. The simulation (fig. 4b) demonstrated good performance and functionality up to 3 GHz. The circuit topology was transferred into a mask-design, wich can be used for further investigation and verification of the model-to-hardware correlation. Summary A compact HBT model for the ADS Design System is adapted to the state of the art RTD/HBT technology for MMIC development. The agreement with the measured data was demonstrated for DC as well as frequencies up to 50 GHz. Additional measurements of the DC- and RF-performance at low temperatures down to 20 K and noise fig. measurements for frequencies up to 18 GHz are used to explore the performance of the HBTs. The new model is used for design and simulation of a CML-latch based on the RTD/HBT concept. References [1] T.Kim, Y.Jeong and K.Yang, New rtd-based set/reset latch ic for high-speed mobile d-flipflops, Indium Phosphide and Related Materials, International Conference 2005, pp , May 2005

94 88 Bi-Annual Report 2008/ Solid-State Electronics Department Development of a Transimpedance Amplifier with Balanced Optical Input Scientist I. Nannen Introduction The increased performance of optical communication systems results in a higher bit rate, which has to be transported over existing optical fibers. Therefore the complexity and bandwidth of transmitted data had to be improved. Synchroneous Quadrature Phase Shift Keying (synqpsk) is an extremely attractive modulation format for long haul fiber communication. Thereby the tolerance to polarization mode dispersion and the tolerance against fiber nonlinearities are better compared to standard intensity modulation. Transimpedance Amplifier Within the synqpsk project, financed by the EU, a three stage transimpedance amplifier (TIA) was developed. The first stage is a cascode employing two Heterostructure Field Effect Transistor (HFET) which provides the gain. The transimpedance converter is used as second stage and feedback point for the feedback resistor R f forming the typical TIA configuration. The third and last stage is a differential amplifier. This stage matches the output impedance to 50 Ω and provides different outputs shifted 180 in phase. Balanced photo diode pair V 1 + C C Cascode to reduce effective input capacitance Buffer Stage Differential output stage V d1 V d2 V d3 6 7 C 8 C 1 R 1 T 1 R 3 R 4 R 5 T 3 u out,p u out,n D 1 V 1 - V 2 + C 2 C 5 R 2 R f D 2 D 3 T 5 T 6 R 6 C 3 T 2 D 4 T 4 T 7 C 4 second circuit: same as drawn above but seperate power supplies C 9 V S V 2 - Fig. 1 Opto-electronic Transimpedance Amplifier

95 Device and Circuit Simulation, Measurement and Modeling 89 Fig. 2 picture taken of fabricated circuit Measurement For the characterization of the pure electrical bahavior of the TIA, s-parameter measurements were performed. Therefore a circuit with electrical input was used. The results of these measurements are shown in the next picture. The transimpedance of the circuit is 60 dbω with a bandwidth arround 5 GHz for different single outputs but with a very good homogeneity accross the wafer. Fig. 3 Measured transimpedance of pure electrical circuit

96 90 Bi-Annual Report 2008/ Solid-State Electronics Department Simulation Rf measurements of the used transistors were performed to check the agreement of simulation results and measurement results. These measurement indicates a f t of the transistors of 60 GHz. Transistor models were designed in ADS using the measurement data and the circuit was resimulated including additionally the fitted resistor values, which were too high, because of an increased sheet resistance. The measured data is in good agreement with the simulated data. Fig. 4 Simulation and measurement results of the investigated TIA Summary The unexpected high sheet resistance and HFETs with a smaller f t than expected causes circuits with an increased gain, because of the higher feedback resistance, but with a lower bandwidth. A modeling of the HFETs and a resimulation with adapted resistor values leads to a good agreement between the measurement and the simulation.

97 Device and Circuit Simulation, Measurement and Modeling Simulation and Investigation of Opto-Electronic Receiver Circuits Student: Supervisor: Ö. Kahraman I. Nannen Introduction The transmission of large data sets is carried out mostly by optical transmission paths. Through the need of a subsequent conditioning or an evaluation of the optical signals requires opto-electronic receiver circuits, which converts the optical signals into electrical ones. This thesis incororated the simulation and investigation of opto-electronic receiver circuits built by III-V semiconductor devices. The aim was hereby to analyse processing effects on the circuit performance. For this, the influences of the utilized devices, wire structures and circuit parameters on the circuit performance were explored. The important specifications according to the circuit performance in this project were a transimpedance TZ 60 db and a corner frequency of f 3db 10 GHz. To use the advantages of simulation tools, it was also nessary to adjust the detected measurement data of the devices and the given ADS-model data. Circuit Setup Two in series connected pin-photodiodes are building the differential input of the receiver circuit and dissipate optical signals into an electrical photo-current. The following two amplifier stages set up with a feedback-resistance a transimpedance amplifier. It amplifies and converts the photocurrent signal into a voltage one. The proximate differential amplifier stage leds to the differential output signal, which is one of project specifications. In the following schematic (Fig.1), the given circuitry is illustrated:

98 92 Bi-Annual Report 2008/ Solid-State Electronics Department Fig. 1 Schematic of the receiver circuit Investigations and Results From the investigations, it is concluded that the device parameters play a remarkable role on the behaviour of the circuit. To analyze the effects of individual devices on the circuit properties, it was nessary to model and merge a new transistor (HEMT-M3720C1) into the ADS simulation environment. New simulations of the circuit with this transistor resulted in a shift of the operation points within the differential amplifier stage, which attenuated the transimpedance to values of TZ = 25 db. Through an adjustment of the operating points at the differential amplifier stage, a transimpedance of more than 60 db could be achieved. The investigations to the resistances resulted in a shift of the transimpedance, such that an increase of the transimpedance led to a decrease in the bandwidth and vice versa. The analysis of the condensator at the kaskode stage did not show any effect on the circuit characteristics. It was sufficiently large dimensioned. In total, especially the modelled transistors and resistance deviations affected the characteristics of the adjusted and dimensioned operating points such that they led to a noticeable deviation from the basic characteristics.

99 Device and Circuit Simulation, Measurement and Modeling 93 Fig. 2 Comparison of the RF performance befoe and after the optimization For the investigations of the wire structures, 2-Port and Multi-Port simulations were made. The 2- Port analysis yield in a first overview of the magnitude of the parameters and the potential effects on the circuit. Here impedances till R = 5, with capacitive portions till C = 431 ff and inductive portions till L = 210 ph were determined. Since the pieces of wire structures however connect many devices, these results were not sufficient to make statements concerning the circuit characteristics. Therefore it was nessary to provide on the basis multi-haven investigations new HFparameters. The obtained data were inserted by means of Data-Items into the receiver circuit schematic and resulted in a that the wire items did not have any influences on the transimpedance or corner frequency characteristics and could been neglectable. Circuit parameters like the supply voltages of the particular circuit stages, the threshold voltages of the transistors and their mutual effect on each other led to an increase in the transimpedance as well as a decrease in the corner frequency and vice versa. The changes in the circuit characteristics which could appear due to different threshold voltages could only be compensated conditionally by the supply voltages.

100 94 Bi-Annual Report 2008/ Solid-State Electronics Department Modeling of Resonant Tunneling Diodes Student Scientist Y. Fu A. Tchegho, B. Münstermann, W. Prost Introduction In recent years, the Resonant Tunneling Diode (RTD) has been widely studied because of its potential application in very high speed devices and circuits. SPICE models for low current densities (J = ka/cm²) RTD devices have been developed and the sensitivity parameters have been examined [1]. The new concept for digital and analog circuits in the Solid-State Electronics department of the University of Duisburg-Essen requires much higher current densities and smaller device areas. The aim of this work is to design a scalable simulation model, for a high current desity RTD (J = about 150 ka/cm 2 ) aided by Advance Design System. To model of the resonant tunneling diode, a description of the resonant tunneling current is required. Tsu and Esaki describe a semi-physical model [2], the resonance current density depends on the voltage applied to the double barrier. This analytical circuit model is composed of a voltagecontrolled current source and a voltage-dependent capacitance [3]. The series resistance RS is composed of the damage caused by the contact resistance, the electrical losses in the layers, and the parasitic losses of the RTD. Similar to the semi-classical mechanisms of drift and diffusion, the tunnel effect could also realize the transport of charges in solid state. The voltage-controlled current source could be described as the superposition of the resonant tunneling current IT and thermionic current ITH with some simplifications like shown in fig. 1 [3]. The mathematical description of the resonant tunneling current is a function of the different material parameters, which compose the epitaxial growth of the thin layer and their interaction. Additional to this material parameters and some fitting parameters, DC and HF measurements are needed to extract large and small signal parameters of the diodes and to achieve a good modelhardware corelation. The precise measurement and extraction of all it parameters as well as their fine-tuning are challenges faced during RTD modeling. DU862B_B6_1x1 Fig. 1 I-V curve for RTD DC model. The resulting diode current is a superposition of resonant tunneling current and thermionic current.

101 Device and Circuit Simulation, Measurement and Modeling 95 Experiments and Results The experimental I-V behavior of RTDs were collected by using DC measurement with measuring station (Süss PA 150) and the parameter analyzer (HP 4145B). Fig. 2 shows an example of the frequency diagram for nominal peak current density J p of DU862B. The statistical average is ka/cm 2. The variation can be explained by technological fluctuation and area of top contact areas definition Quantity Fig Peak current density J P [ka/cm 2 ] Frequency diagram for nominal peak current density J p of DU862B. The first mesa is erosed by ICP. To eliminate the influence of the contact resistance (between the needle and contact pad), the kelvin measurement (4-point) is used, as shown in Fig 3. The equation: R Z U U RTD / I RTD is used to calculate the contact resistance. Fig. 3 Equivalent circuit diagram of serie resistance,inclusive contact resistance R Z between the needle and pad.

102 96 Bi-Annual Report 2008/ Solid-State Electronics Department For a more accurate measurement of the parasitic series resistance, the dynamic method [3] is used. If we just consider the real part of the impedance equations for the RTD, the resistance R S is a frequency-independent constant in the impedance equation: Re{ Z RTD } R R /(1 ( C R ) ). S S d d 2 At a very high frequency, the frequency-dependent part vanishes and the term is simplified as: Re{ Z } RTD 0 R S. After analysis and calculation of the structure of the diode the series resistance(as shown in fig. 3) can be written in the following area-dependant equation: R S R R R and R 2.22 µm / TOP SH BUTTON 2 S A RTD Fig. 4 Comparison of I-V data of various diodes from measurement and simulation. In fig. 4 the I-V data of various diodes from measurement and simulation are compared after addition of raising the voltage at the series resistance. The advantages of the model are scalability of the active area device and accurate fit in the PDR1 region, but the biggest fitting error is localised in the valey region. In summary, the area-based RTD model with high current density have been designed. The current density is based on the theory of Tsu and Esaki. This model can be used in high-speed digital circuits.

103 Device and Circuit Simulation, Measurement and Modeling 97 References [1] W. Prost, U. Auer, F.-J. Tegude, C. Pacha (1), K.F. Goser (1), G. Janßen (2), T. van de Roer; Manufacturability and Robust Design of Nanoelectronic Logic Circuits based on Resonant Tunnelling Diodes, Int. Journal of Circuit Theory and Applications, Vol. 28, No. 6, Special Issue on Nanoelectronics Circuits, pp [2] G. Peter, "Resonanztunneldioden und Heterobipolartansistoren in dynamischen Digitalschaltungen hoher Funktionsdichte", Dissertation, Universität Dortmund, [3] A. Matiss, Entwurf und Realisierung neuartiger Schaltungskonzepte mit Resonanztunneldioden, Dissertation, Universität Duisburg-Essen, Feb, 2008.

104 98 Bi-Annual Report 2008/ Solid-State Electronics Department Investigation of n-n-heterostructure Diodes Student Scientist Technical Assistance: D. Zhang W. Prost, B. Münstermann, A. Poloczek R. Geitmann, S. Köppen, A. Eckhardt Introduction Semiconductor diodes exhibit a strongly asymmetric and non-linear I-V characteristic. This behavior is attributed to an electronic barrier basically formed by a pn-junction or a metal semiconductor interface. An alternative class of diodes based on semiconductor heterojunctions was presented by Allyn et al. using the material system GaAs/Al x Ga 1-x As [1]. Here, the barrier height is determined by the band edge discontinuity at the heterojunction. This height may be adjusted according to possible applications. A small signal rectifier will require low barriers while voltage shift diodes may use a fairly large value. These diodes are well suited for vertical integration and do not require a change of the carrier type. In this study, the InP materials system is adopted for unipolar heterojunction diodes. These materials offer a wider range of barrier height and excellent transport properties. The n-n unipolar diode consists of a saw-tooth type of conduction band barrier, which is sandwiched between two highly n-doped contact layers (cf. fig. 1b). The continuous increase of the conduction band edge is provided by a gradual composition change towards a lower electron affinity χ while the lattice constant has to remain constant [2]. In the Al x Ga 1-x As material system this can be easily provided by increasing the Al-content (0 < x < 0.6). On InP-substrate, a quaternary In 0.52 (Ga y Al 1-y ) 0.48 As layer was used, which is for all Al-compositions y lattice matched to InP (cf. fig. 1a) and which provides the conduction band rise by reducing the electron affinity χ(y) (fig. 1b). Fig. 1 band-gap W g / ev AlAs GaAs (a) Ge Al x Ga 1-x As InP 52 In 52 (Ga 1-y AI y ) 48 As 53 In x Ga 1-x As 300 K In x AI 1-x As lattice-constant a 0 / nm InAs 0.61 energy W [ev] Ga Al (b) 0.0 q. (z) In 52 (Ga 1-y AI y ) 48 As In W 0 = 0 vacuum level depth z [µm] a) Band-gap vs. lattice constant for GaAs and InP based heterostructures (b) Composition of Al and Ga and calculated electron affinity / band gap of a saw-tooth In 0.52 (Ga y Al 1-y ) 0.48 As barrier layer for n-n diode application. Ga Al W F W C W V composition

105 Device and Circuit Simulation, Measurement and Modeling 99 The band structure of the n-n diode was simulated by using the program SimWindows [3]. The electron affinity decreases from qφ B = 4.7 ev for In 0.53 Ga 0.47 As (y = 0) to qφ B = 4.2 ev for In 0.52 Al 0.48 As (y = 1) (fig. 1b). Hence according to Anderson s model a barrier height of 0.5 ev shall be formed. Experiments and Results The layer stack was grown by MBE, and the devices were fabricated with optical contact lithography, wet chemical etching, and lift-off (inset in fig. 2a). The experimental I-V behavior of the n-n diodes were in collected by using DC measurement with measuring station (Süss PA 150) and the parameter analyzer (HP 4145B. fig. 2 shows the I-V characteristics of an n-n diode on InP substrate. In addition The current-voltage characteristics were calculated in analogy to Schottky diode by using the thermionic-emission theory and diffusion theory [4]. The measurement and simulation data of reverse current for both n-n diodes have been compared in fig. 2b. At reverse bias the InP n-n diode shows good agreement with the simulation result of Φ B 0.4 ev (fig. 2b). Such a good agreement of simulation and measurement results like InP n-n diode was not reached for GaAs n-n diode partly due to the anomaly band structure. At forward bias InP n-n diodes with a high barrier exhibit an ideality factor of up to 6, while devices with lower barrier height exhibit an ideality factor between n = 1 and n = 2. current density I D [A/cm 2 ] T = 300 K A C = 10 x 17 µm² reverse current density I D [A/cm 2 ] A05 A26 q B = 0.3 ev q B = 0.5 ev DU 851 T = 300 K q B = 0.4 ev a DU 851 A26 b diode bias V [V] reverse bias V [V] Fig. 2 I-V characteristics of (a) InP-based and of b) GaAs-based (reverse bias) diodes. In fig. 3 the I-V data of various diodes on InP- and GaAs-substrate are compared after subtraction of the voltage drop at the series resistance. The current density both in forward and reverse direction are exponentially proportional to the barrier height used. The highest barrier is available at the n-gaas/tiptau interface of a Schottky diode which results in a low reverse current density ~10-5 A/cm². The highest current density is obtained for an n-n Diode on InP substrate with an In 0.52 (Ga y Al 1-y ) 0.48 As with y max = This device exhibits at V = 0.2 V a current density of 10 ka/cm² and is therefore of interest for a small signal microwave detector.

106 100 Bi-Annual Report 2008/ Solid-State Electronics Department diode current I D [A/cm²] 10, approx. q B = ~ 0.25 ev ~ 0.3 ev ~ 0.35 ev InGaAs/In(Al y Ga 1-y )As y max = 0.7, DU 863 InGaAs/InP HFET M 3892 GaAs/Al x Ga 1-x As (x max = 0.6) DU 854 n-gaas Schottky-diode M 248 0,0001 ~ 0.75 ev Fig. 3 1E diode voltage V D,int [V] Comparison of I-V data of various diodes on InP- and GaAs-substrate. Finally, preliminary rf measurements were performed (100 MHz 20 GHz) in order to receive a small -signal model. The equation: s = t / V= C / I [ns / V] has been used to calculate the speed index s. The GaAs n-n diode with a barrier height of 0.35 ev exhibits a low current density and accordingly also a low speed index of s = 2.3 ns/v at V = 0.5 V. The device with a higher current density provides a much higher speed index. The n-n diode on InP with y max = 0.71 results in a speed index of s = 8 ps/v at V D = 0.2 V. In summary, robust diodes on InP- and GaAs-substrate have been designed and fabricated. According to the barrier height implemented a huge current density variation has been obtained. The current density can basically be described by the thermionic-emission theory. This holds for both, Schottky and n-n diodes. The n-n diode with low barrier height may be used as microwave device for rectification and mixing and has the clear potential to outperform currently used Schottky diodes at low signal levels. References [1] C. L. Allyn, A. C. Gossard and W. Wiegmann; New rectifying semiconductor structure by molecular beam epitaxy, Appl. Phys. Lett. 36(5) , [2] Werner Prost; Technologie der III/V-Halbleiter, Springer Verlag, [3] David W. Winston; SimWindows, University of Colorado. [4] Klaus Heime; Skript zur Vorlesung Festköper Elektronik, Universität Duisburg, 1987.

107 Device and Circuit Simulation, Measurement and Modeling Unipolar Heterostructure Diode for Small Signal Rrectification and DC Power Supply in RFID Transponders Scientist Technical Assistance: B. Münstermann, A. Poloczek, W. Prost, T. Feldengut (Fraunhofer-Institute (IMS) Duisburg R. Geitmann, A. Eckhardt Introduction The current density J 0 across an electronic barrier is given by thermionic emission and may vary by several orders of magnitude depending on its barrier height q B. In a number of applications such as small signal rectification, a high current density at small amplitudes is required. Allyn et al [1] demonstrated that the band gap discontinuity at a heterojunction may be used an electronic barrier with as a tunable barrier height and hence tunable I-V charateristic. In this contribution, we will investige the performance of nn-heterostrucuture diodes with a low barrier height for small-signal RF detection. Especially, the possible application for RF-to-DC power conversion in ultra high frequency radio frequency identification (RFID) transponders [2-3] will be discussed. InP-based unipolar nn-diode N-n-heterostructure diodes consist of a saw tooth type of conduction band barrier sandwiched between two highly n-doped contact layers. On InP-substrate, we used quaternary In 0.52 (Ga y Al 1-y ) 0.48 As layer, which is for all Al-compositions y lattice matched to InP. The barrier height can be adjusted by the maximum Al-content y max in the barrier. In this work y max = 0.7 is investigated. According to Anderson s model a barrier height of ΔW L = 0.35 ev is provided. Energy E top contact InGaAs 1E nm W F (z) (a) depth z (b) W L W 0 n-contact InGaAs 1E nm spacer InGaAs - 5 nm saw tooth InGaAlAs - d B barrier spacer InGaAs - 5 nm n-contact InGaAs 1E nm n+-contact InGaAs 1E19 20 nm substrate InP:Fe (100) 350 µm (c) Fig. 1 Nn-diode: (a) symbol and polarity, (b) conduction band evolution, (c) layer stack on InP-substrate. The saw tooth barrier thickness d B was 200 nm and the maximum Alcontent was y max = 0.7 (DU 863)

108 102 Bi-Annual Report 2008/ Solid-State Electronics Department The layer stack was grown by molecular beam epitaxy in a Varian GenII apparatus on s. i. InP:Fe substrate (cf. fig. 1c). During growth of the In 0.52 (Ga y Al 1-y ) 0.48 As barrier (0 < y 0.7, the Indium cell BEP was kept constant at Torr. The sum of the Al- and Ga-cell BEP was also kept constant while both, the Ga- and the Al- cell temperature were inversely ramped in order to reach an outmost linear slope of the Al-/Ga-composition within the whole saw tooth barrier. The device processing was done with optical contact lithography, wet chemical etching, and lift-off. A coplanar contact pattern enabling on-wafer RF measurements is used. DC/RF characteristics and Device model The nn-diode I-V characteristic is dominated by the barrier height due to the conduction band discontinuity ΔW L at the In 0.52 (Al 0.7 Ga 0.3 ) 0.48 As/In 0.53 Ga 0.47 As heterojunction. The best fit of simulated data to experimental reverse and forward I-V characteristics is obtained for a barrier height of 0.25 ev which is about 0.1 ev less than the nominal data. To analyze the device capacitance a small signal equivalent circuit as shown in fig. 2 was used including the parasitic capacitance C pad = 20 ff and the inductance L s = 45 ph. The intrinsic diode is described by the series resistor R and the capacitance C(V D ), and the parallel resistance R(V D ). The device capacitance C(V D ) has been determined by fitting the parameters to the measured rfdata. The extracted values increases from 0.8 ff/µm 2 to 1.1 ff/µm 2. For a first guess of the switching speed of the device, the speed-index s might be used: t V I C (2) s ps / V. The nn-diode with y max = 0.7 reached a speed index of s = 50 ps/v at a bias as low as V D = 0.15 V which shows its potential for low-signal microwave applications. Based on the DC and small-signal data a large-signal device model has been developed. The device model is based on a standard pnjunction model included in the Advanced Design System software and shows good agreement between measured and modeled DC and RF characteristics (800 MHz to 6 GHz). The scalability of the derived model has been tested on emitter sizes between 16 µm 2 and 120 µm 2 and can be used to predict the behavior of the needed low capacitance devices for application in RFID-rectifiers. pad L S = 45 ph R S intrinsic device V D C pad 20 ff V D,int R(V D ) C(V D ) Fig. 2 Small Signal equivalent model of an InP-based unipolar n-n-heterostructure diode Radio frequency identification transponder In Radio Frequency Identification (RFID) systems the required power for driving the transponder circuits has to be generated by the received RF-signal power. Therefore voltage rectifier circuits are needed to convert the high frequency signal into a stable DC supply voltage [4, 5]. Several stages

109 Device and Circuit Simulation, Measurement and Modeling 103 are implemented in a cascaded charge-pump structure in order to generate sufficient DC voltage for the operation of integrated circuits (cf. fig. 3). The power efficiency and the minimum input voltage requirements of the rectifier determine the maximum distance between the remotely powered device and the base station. For efficient rectification diodes with relatively high switching speed at a low forward bias are required. The investigated nn-heterostrucuture diode exhibits at V D = 0.15 V an ideality factor of n = 1.2, a current density of 20 µa/µm², and a rectification factor of G R = 30. Fig. 3 UHF voltage multiplier/rectifier In fig. 4 a transient simulation of the ac current i d (V d (t)) within the initial 10 µs is compared to the device DC I-V characteristics with 5 µm² emitter area. The observed voltage drop in forward direction is reduced to 150 mv, while in the negative regime the blocking effect is illustrated. The maximum current of 100µA (20µA/µm 2 ) is used to load the following capacitor in the charge-pump architecture. Optimization has shown that a drastic reduction of the emitter size to 5µm 2 of the diodes increases V in and provides a voltage supply of 1.5 V for a minimum received rf-power of - 13,6 dbm. Fig. 4 I-V-characteristics and transient diode current of the device in the rectifier circuit. The observed forward voltage drop is 150 mv for a 5 µm2 emitter area device

110 104 Bi-Annual Report 2008/ Solid-State Electronics Department In tab. 1 the performance of the multistage rectifier using nn-diodes is compared with previous publications based on Si-Schottky diodes. The maximum operating range of the FRID for a basestation which transmits 3.28 W RF power at a carrier frequency of 864 MHz has been calculated. Using the nn-diodes the operating range of the system can be improved by 30%. The conversion efficiency is for the given load conditions is 17%, which is an excellent value compared to the conventional rectifiers. min RF-Power for 1.5 V, 5µA max. distance to base station RF to DC efficiency this work -13,6 dbm 7,5 m 17 % [10] -10,5 dbm 5,4 m 12 % [11] -11,3 dbm 5,74 m 10 % Tab. 1 Performance data of the investigated cascaded charge-pump circuit for remote RFID DC power supply based on nn-diodes in comparison to works using Si-Schottky diodes [10, 11]. Conclusion A unipolar nn-heterostructure diode on InP-substrate is developed with an In 0.52 (Ga y Al 1-y ) 0.48 As saw tooth barrier layer with 0 < y < 0.7. The electronic transport across the barrier can be described by thermionic emission theory. In this study the device with a low barrier height is investigated for AC-to-DC conversion in remote powered RFID requiring high current densities and high rectification factors at low bias. In comparison to a standard Si-Schottky diode 3 dbm less RFpower is needed while the efficiency increases from 12 % to 17 %. References [1] C. L. Allyn, A. C. Gossard and W. Wiegmann; New rectifying semiconductor structure by molecular beam epitaxy, Appl. Phys. Lett. 36(5) , [2] U. Karthaus, M. Fischer; Fully Integrated Passive UHF RFID Transponder IC With µw Minimum RF Input Power ; IEEE J Sol.-State Circ.. vol. 38, no. 10, [3] R. E. Barnett, J. Liu, S. Lazar; A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders, IEEE J. Sol.-State Circ.. vol. 44, no. 2, [4] J.-P. Curty, N. Joehl, C. Dehollain, and M. J. Declercq; Remotely Powered Addressable UHF RFID Integrated System, IEEE Sol.-State Circ. Vol. 40, no. 11, p. 2193, [5] T. Feldengut, R. Kokozinski, S. Kolnsberg; A UHF Voltage Multiplier Circuit Using a Threshold-Voltage Cancellation Technique, PRIME Conf. Proc., p July 2009.

111 Device and Circuit Simulation, Measurement and Modeling High Frequency Measurements on InAs Nanowire Field- Effect Transistors Scientist K. Blekker, B. Münstermann Introduction The low-band-gap, high mobility InAs semiconductor is well suited for nanowire devices. So far, fascinating DC characteristics of InAs nanowire field-effect transistors (NW-FETs) [1],[2] have been shown, whereas the high speed potential is not yet demonstrated. The major challenges towards a reliable RF characterization of single nanowire transistors, regardless of the material system, are the dominant parasitic capacitances and the small signal power. We report here on high frequency measurements based on a coplanar waveguide contact pattern for on-wafer characterization. Small signal scattering parameter measurements are performed on-wafer. The process of de-embedding will be discussed and a preliminary small signal model will be given. Experimental and DC results The InAs nanowires of this study were synthesized by MOVPE using the VLS growth mode (for details, see [1]). InAs NW-FETs are fabricated by removing the wires from the growth substrate onto s. i. GaAs substrates with an additional 150 nm silicon-nitride (SiN x ) layer for improved isolation and a reduced effective dielectric constant. Drain and source pads are patterned using electron beam lithography followed by deposition of the metal system Ti/Au. The nanowires are covered with 30 nm SiN x gate dielectric deposited in an ECR-PECVD apparatus at room temperature. Finally, a self-aligned Ti/Au gate overlapping both, drain and source electrode, was formed (see Fig. 1 a). The omega-shaped gate is partly wrapped around the nanowire and, therefore, offers an excellent control over the channel charge. A further improvement in signal power is achieved due to the two-finger gate configuration. The realised NW-FETs exhibit n-channel characteristics with very good saturation and a high output current. Fig. 1 b shows the output characteristics I ds -V ds of a single n-inas NW-FET in RF configuration with a nanowire diameter of d nw = 35 nm and a gate length of 1.4 µm. The maximum extrinsic transconductance is about g m = 45 µs corresponding to 640 ms/mm per gate finger as normalized with respect to the nanowire diameter. On Wafer RF-Characterization For on-wafer RF measurements a coplanar waveguide pattern with a characteristic impedance of 50 Ω was used according to the requirements of scattering parameter measurements. A coplanar tip of 50 µm pitch was selected to reduce contact pad size and therefore signal-to-ground capacitance. The self-aligned two finger gate overlapping drain and source electrodes (see Fig. 1 a) contributes to the parasitic capacitances. Nevertheless, the self-aligned technique avoids high series resistance due to non-gated regions so that a higher output current is achievable.

112 106 Bi-Annual Report 2008/ Solid-State Electronics Department a b 80µ V gs =-0.5 V - 2 V: steps 0.5 V d nw = 35 nm drain current I ds (A) 60µ 40µ 20µ L g =1.4µm drain-source voltage V ds (V) 2.0 Fig. 1 SEM micrograph of an InAs self-aligned two-finger gate NW-FET with a gate length of 1.4 µm (a) and belonging output characteristics (b) The contact pattern gives a lower limit for the parasitic load, still present in case of further optimized layout of the inner device contacts. Compared to the typical intrinsic gate-source capacitance of about a few hundred ato Farad estimated by electrostatic field simulation, the parasitic capacitance is at least one order of magnitude higher. A detailed study on the layout of the coplanar contact pattern is given in The RF-power of the incident wave was set high to 7 db in order to excite a detectable signal at the output port within the dynamic range of the measurement system. With use of dedicated open and short structures, the parasitics could be de-embedded from the DUT-measurements resulting in corrected S-parameters exhibiting typical field-effect transistor behaviour. A maximum stable gain higher than 30 db at low frequency and a maximum oscillation frequency of 15 GHz are obtained. It should be noted that the current gain, given as h 21 S 21 could not be 1 S11 1 S22 S12S21 a b Fig. 2 Small signal equivalent circuit (a) and the extracted transconductance g m (b)

113 Device and Circuit Simulation, Measurement and Modeling 107 reliable calculated using the as measured S-parameters. Due to the highly capacitive pad environment, S11 is close to unity, such that according to the equation even marginal inaccuracies with respect to S11 have a major impact on the extracted current gain cut-off frequency f T. Meanwhile, it was shown that the current gain can be sufficiently extracted by applying the Cascade-Open-Short-Thru (COST) de-embedding technique [3],[4] as presented in 4.x.x. Due to a lack of the specific Thru calibration element needed for the COST de-embedding, f T was calculated from the transconductance and the intrinsic gate-source capacitance. Both were extracted using the small signal equivalent circuit of Fig. 2 a. An intrinsic gate-source capacitance per unit gate length C gs /L g of about 340 af/µm was figured out for 30 nm SiN x gate dielectric in good agreement with electrostatic field simulation. Fig. 2 b shows the extracted transconductance g m versus frequency. The transconductance is about 45 µs, as derived from DC measurements, in a broad frequency range up to 2 GHz. The decrease beyond is believed to be due to an insufficient accuracy of the small signal equivalent circuit at higher frequencies and the increasing influence of the input-to-output coupling capacitance C gd. Using the values derived with the small signal equivalent circuit, the intrinsic unity current gain cut-off frequency of the transistor presented above is calculated to f T = 7.5 GHz. Conclusion This study underlines the potential of InAs nanowire FET for low-voltage, low-power and highspeed applications. A maximum stable gain higher than 30 db at low frequency and a maximum oscillation frequency of 15 GHz are demonstrated for a long channel device. However, due to the low intrinsic device capacitance in comparison to the environment, the RF calibration has to be carried-out very precisely. A determination of the parasitic environment prior to a reliable deembedding remains difficult and will require further work on the transistor design, the measurement conditions and, the de-embedding technique. Acknowledgement This work was supported by SFB 445 and SPP References: [1] Q.-T. Do, K. Blekker, I. Regolin, W. Prost, and F.-J. Tegude, High transconductance MISFET with a single InAs nanowire channel, IEEE Electron Device Letters, vol.28, no.8, pp , August [2] K.Blekker, Q.-T-Do, I. Regolin, W. Prost, and F.-J. Tegude, Scalable Transconductance of Single n-doped Nanowire Transistors by Variation of Gate Dielectric Thickness, Nanoelectronics Days Aachen, September 2006 [3] M.-H. Cho, G.-W. Huang, C.-S. Chiu, K.-M. Chen, A.-S. Peng, Y.-M. Teng; A Cascade Open-Short-Thru (COST) De-Embedding Method for Microwave On-Wafer Characterization and Automatic Measurement ; IEICE Transactions on Electronics 2005 E88-C(5): , Mai [4] K. Blekker, A. Matiss, B. Münstermann, I. Regolin, B. Li, Q. T. Do, W. Prost, F. J. Tegude; Coplanar Contact Pattern for single InAs Nanowire FET ; 66 th Device Research Conference, Santa Barbara, CA, June 23-25, 2008.

114 108 Bi-Annual Report 2008/ Solid-State Electronics Department On the Temporal Behavior of DC and RF Characteristics of InAs Nanowire MISFET with SiN x Gate Dielectric Student Scientist Y. Otsuhata (Sophia University, Tokyo, Japan) K. Blekker, T. Waho (Sophia University, Tokyo, Japan), W. Prost Introduction Nanowire devices have drawn increasing attention as one of the most promising candidates for logic switches. Recently; III-V nanowire MISFETs have been fabricated exhibiting extremely high transconductance [1, 2]. However, there are only a very few works on their applicability in high speed monolithic integrated circuits [3-5]. In this contribution, the temporal behavior of their dc and rf characteristics has been studied as a prerequisite for the set-up of reliable device models. Experiments and Results In this work InAs nanowire transistors were investigated. The vapor-solid growth mode using Au nanoparticles as a seed was used for the growth of the nanowires on InAs substrates [2]. In order to fabricate top-gate transistors the nanowires were transferred to a Si/SiO 2 host substrate. The host substrate was pre-patterned with contacts by optical lithography and Ti/Au deposition. These contacts were used for field-assisted controlled deposition of the InAs nanowires (Fig. 1a) [3] followed by the patterning of the coplanar source and drain contacts. The deposition of the gate isolation dielectric is a crucial step within the fabrication process due to thermal budget limitations of about 250 C. We have investigated room-temperature deposition of 30 nm SiN x using electronresonance source for chemical vapor deposition with N 2 and SiH 4 precursors which provides the S G InAs nanowire S D a) b) highest transconductance [2]. DC drain current I D (µa) b V DS slew rate = mv/s mv/s M drain-source voltage V DS (V) 1.5 V 1.0 V 0.5 V 0.0 V V GS Fig. 1. InAs nanowire MISFET (d = 110 nm): (a) SEM micrograph of coplanar contact pattern and (b) output I-V characteristics. V DS swept from 0 V to 1.5 V with 15 mv/s or 3.8 mv/s.

115 Device and Circuit Simulation, Measurement and Modeling 109 Drift and hysteresis were observed in the dc output characteristics (fig. 1b). Two types of hysteresis, counter-clockwise (CCW) and clockwise (CW), were found, for both the output and transfer characteristics, if the sweep rates were fast and slow, respectively. For comparison, a standard InGaAs/InP heterostructure field-effect transistor with the same SiN x gate isolation layer between gate metal and recessed gate surface has been fabricated with a gate width of W G = 40 µm. The gate length of both devices is about L G 1.1 µm. A detailed study on the temporal behavior of DC and small-signal characteristics of both devices has been carried out. Fig. 2a shows the dc drain current I D of the nanowire MISFET obtained at a fixed bias of V DS = 0.7 V and V GS = 0.9 V as a function of the elapsed time. Under this open channel condition an increase of the drain current relating to the CCW hysteresis was found up to 400 seconds (cf. fig. 2a). Above that a decrease in the dc drain current, corresponding to the CW hysteresis, was observed which is probably S due to the InAs/SiN x interface traps and may remain active for a long term. C gs (ff) g m (µs) DC drain current I D (µa) M 4065, V GS = 0.9 V, V DS = 0.7 V Discussion In order to study the effect of the drift on the rf performance, the small-signal parameters were studied. The transconductance gm, and the Fig. 2 elapsed time (s) DC drain current (a), and small-signal parameters g m (b), C gs (c), of an InAs nanowire MISFET (L G = 1.1 µm, d = gate-source capacitance C gs were deduced by 110 nm) versus elapsed time in a semilog plot. In Fig. 2c the gate capacitance fitting the measured rf scattering parameters C from 45 MHz to 10 GHz to a small-signal gs divided by 20 of an InGaAs/InP MISFET (L G = 1.1 µm, W G = 40 µm) is equivalent circuit model [4]. The given for comparison. [3] transconductance g m is substantially lower at rf frequencies indicating a contribution of low mobile carriers to the transport. gm increases with the elapsed time (fig. 2b), indicating that the CCW hysteresis is not related to a degradation in the rf performance. The parallel increase of both I D and g m in this region is due to an improved gate control via the SiN x gate dielectric. Up to 200 s elapsed time the InGaAs/InP MISFET exhibits the same drift behavior. This drift comes along with a steady increase of C gs proving the better gate control. This effect could not directly been proven in the nanowire MISFET because a capacitance of ff is difficult to a b c C gs /20 MISHFET M 3892, V GS = 0.6 V, V DS = 0.5 V

116 110 Bi-Annual Report 2008/ Solid-State Electronics Department extract precisely (fig. 2c). The origin of the decay in the drain current above 200 s (fig. 2a) is found in the nanowire MISFET only, and deserves further investigations. Summary The temporal behavior of InAs nanowire MISFET with SiN x gate dielectric was investigated. Severe timing effects were observed on both the small- and large signal parameters, respectively. The drift towards a higher drain current could be identified as an improved gate control which is available up to GHz frequencies. On the other hand, a substantial decay on the rf transconductance was found indicating the need of an improved gate dielectric within the limitations of the limited thermal budget of about 250 C. References [1] C. Thelander, L. E. Fröberg, C. Rehnstedt, L. Samuelson, L.-E. Wernersson, Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor with 50-nm Wrap Gate, IEEE Electron Device Lett., vol. 29, no. 3, p. 206, (2008). [2] Q. T. Do, K. Blekker, I. Regolin, W. Prost, F. J. Tegude, High Transconductance FET with a Single InAs Nanowire Channel, IEEE Electron Device Lett., vol. 28, no. 8, pp , [3] Yutaka Otsuhata, Takao Waho, Kai Blekker, Werner Prost, and Franz-Josef Tegude; On the temporal behavior of DC and rf characteristics of InAs nanowire MISFET, ISDRS 2009, December 9-11, 2009, College Park, MD, USA [4] K. Blekker, B. Münstermann, A. Matiss, Q. T. Do, I. Regolin, W. Brockerhoff, W. Prost, F. J. Tegude, High Frequency Measurements on InAs Nanowire Field-Effect Transistors Using Coplanar Waveguide Contacts, accepted to IEEE Trans. Nanotechnology, [5] S. A. Dayeh, C.Soci, P.K.L. Yu, E.T.Yu, D.Wang, "Transport properties of InAs nanowire field effect transistors: The effects of surface states," J. Vac. Sci. Technol. B, vol. 25, no. 4, p. 1432, Acknowlegdement Yutaka Otsuhata (1986) is currently a master student in Electrical and Electronics Engineering under supervision of Prof. Takao Waho at Sophia University Tokyo, Japan. This work was partly carried out during his summer internship at the University Duisburg Essen in August and September The work was jointly supported by the Deutsche Forschungsgemeinschaft (DFG Pr 515/11-1) and Japanese Science and Technology Agency (JST) within the Yutaka Otsuhata Japanese/German programme on Nanoelectronics. The project is called Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems.

117 Conference Contributions Conference Contributions 1. Electrical Integration of Semiconductor Nanowires K. WEGENER (1), S. MÜLLER (1), D. STICHTENOTH (1), W. DEWALD (1), C. RONNING (1), C. GUTSCHE, A. LYSOV, W. PROST (1) IV. Inst. of Physics, University of Goettingen, Germany DPG Frühjahrstagung, Berlin, (Poster) 2. Ion Implanted GaAs Nanowire pn Junctions K. WEGENER (1), D. STICHTENOTH (1), C. RONNING (1), C. GUTSCHE, W. PROST, F.-J. TEGUDE (1) IV. Inst. of Physics, University of Goettingen, Germany DPG Früjahrstagung, Berlin, Ion Implanted GaAs-Nanowires C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (1), K. WEGENER (1), M. SEIBT (1), C. RONNING (1) (1) II. Inst. of Physics, University of Goettingen, Germany Nanoelectronic Days 2008 (ND), Aachen, Germany, Gate Length Scaling of InAs Nanowire Field-Effect-Transistors K. BLEKKER, I. REGOLIN, W. PROST, F.-J. TEGUDE Nanoelectronic Days 2008 (ND), Aachen, Germany, High Frequency Characterisation of Single InAs Nanowire Field-Effect Transistor K. BLEKKER, Q.T. DO, A. MATISS, W. PROST, F.-J. TEGUDE IEEE Int. Conf. on InP and Related Materials 2008 (IPRM), Versailles, France, Monostable-Bistable Threshod Logic Elements in a Fully Complementary Optical Receiver Circuit for High Frequency Applications A. MATISS, A. POLOCZEK, W. BROCKERHOFF, W. PROST, F.-J. TEGUDE IEEE Int. Conf. on InP and Related Materials 2008 (IPRM), Versailles, France, Doping of GaAs Nanowires via VLS-Mechanism A. LYSOV, I. REGOLIN, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE IC MOVPE, Metz (France), III-V Nanowires - Doping and RF - W. PROST, F.-J. TEGUDE Seminar at Harvard University, Dep. of Chemistry, Prof. Ch. Lieber, Coplanar Contact Pattern for single InAs Nanowire FET K. BLEKKER, A. MATISS, B. MÜNSTERMANN, B. LI, I. REGOLIN, Q.T. DO, W. PROST, F.-J. TEGUDE 66th Annual Device Research Conference (DRC), Santa Barbara, CA, USA,

118 112 Bi-Annual Report 2008/ Solid-State Electronics Department 11. Electrical and Structural Characterization of Ion Implanted GaAs Nanowires C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (1), K. WEGENER (1), M. SEIBT (1), C. RONNING (1), (2) (1) II. Inst. of Physics, University of Goettingen, Germany (2) Inst. for Solid-State Physics, University of Jena, Germany Electronic Materials Conference, Santa Barbara, Local Electrical Analysis of a Single Semiconductor Nanowire by Kelvin Probe Force Microscopy S. VINAJI (1), A. LOCHTHOFEN (1), W. MERTIN (1), G. BACHER (1), I. REGOLIN, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE (1) Dept. of Materials for Electrical Engineering, University Duisburg ICPS (International Conference on the Physics of Semiconductors), Rio de Janeiro (Brazil), Kelvin Probe Force Microscopy as a Tool for the Characterization of Single Semiconductor Nanowires S. VINAJI (1), A. LOCHTHOFEN (1), W. MERTIN (1), G. BACHER (1), I. REGOLIN, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE (1) Dept. of Materials for Electrical Engineering, University Duisburg Nanowire Growth Workshop (NGW), Duisburg, Germany, Doping of (In)GaAs Nanowires I. REGOLIN, A. LYSOV, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE Nanowire Growth Workshop (NGW), Duisburg, Germany, Large-Signal Performance of Resonant Tunneling Diodes in K-Band Oscillators B. MÜNSTERMANN, A. MATISS, W. BROCKERHOFF, F.-J. TEGUDE Europ. Microwave Week / GAAS, EuMC, ECWT 2008 (EuMW), Amsterdam, The Netherlands, Ion Beam Induced Alignment of Semiconductor Nanowires C. BORSCHEL (1), R. NIEPELT (1), S. GEBURT (1), C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (2), D. SCHWEN (3), C. R ONNING (1) (1) Inst. for Solid-State Physics, University of Jena, Germany (2) II. Inst. of Physics, University of Goettingen, Germany (3) Dept. of Materials Science and Engineering, University of Illinois, USA MRS Fall Meeting, Boston, USA, Ion Beam Induced Alignment of Semiconductor Nanowires C. BORSCHEL (1), R. NIEPELT (1), S. GEBURT (1), C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (2), D. SCHWEN (3), C. R ONNING (1) (1) Inst. for Solid-State Physics, University of Jena, Germany (2) IV. Inst. of Physics, University of Goettingen, Germany (3) Dept. of Materials Science and Engineering, University of Illinois, USA Towards Reality in Nanoscale Materials (TRNM), Levi, Finland, Kontrollierte Zink Dotierung von GaAs Nanodrähten A. LYSOV, I. REGOLIN, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE DGKK Workshop, Braunschweig, Germany,

119 Conference Contributions Ion Beam Induced Alignment of Semiconductor Nanowires C. BORSCHEL (1), R. NIEPELT (1), S. GEBURT (1), C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (2), D. SCHWEN (2), C. RONNING (1) (1) Inst. for Solid-State Physics, University of Jena, Germany (2) II. Inst. of Physics, University of Goettingen, Germany (3) Dept. of Materials Science and Engineering, University of Illinois, USA MRS Fall Meeting, Boston, USA, III/V-Nanodrähte für die Nanoelektronik und die Licht/Strom-Wandlung W. PROST Seminar, Friedrich-Schiller-Universität Jena, Institut für Festkörperphysik, (INVITED) 21. Local electrical analysis of a single semiconductor nanowire S. VINAJI (1), A. LOCHTHOFEN (1), W. MERTIN (1), I. REGOLIN, C. GUTSCHE, K. BLEKKER, W. PROST, F.-J. TEGUDE, G. BACHER (1) (1) Dept. of Materials for Electrical Engineering, University Duisburg DPG Frühjahrstagung, Dresden, Germany, Ion Beam Induced Alignment of Semiconductor Nanowires C. RONNING (1), C. BORSCHEL (1), R. NIEPELT (1), S. GEBURT (1), C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (2), D. SCHWEN (3) (1) Inst. for Solid-State Physics, University of Jena, Germany (2) II. Inst. of Physics, University of Goettingen, Germany (3) Dept. of Materials Science and Engineering, University of Illinois, USA DPG Frühjahrstagung, Dresden, Germany, Rf-characterization of III-V-Nanowire FET: Problems and Results (invited) F.-J. TEGUDE, W. PROST DPG Frühjahrstagung, Dresden, Germany, Wavelenght-Sensitivity Receiver for Simultaneous =1.3µm and =1.55µm RF Optical Transmission A. POLOCZEK, B. MÜNSTERMANN, I. NANNEN, I. REGOLIN, F.-J. TEGUDE IEEE Int. Conf. on InP and Related Materials (IPRM), Newport Beach, CA, USA, Recent Progress in Dilute Nitride-Antimonide Materials for High Speed Photonics and Electronics S.F. YOON, K.H. TAN, W.K. LOKE, S. WICAKSONO, K.L. LEW, Z. XU, Y.K. SIM, T.K. NG, A. STÖHR, S. FEDDERWITZ, M. WEISS, A. POLOCZEK, D. J ÄGER, N. SAADSAOUD, E. DOGHECHE, M. ZEGAOUI, J.F. LAMPIN, D. DECOSTER, C. TRIPON- CANSELIET, S. FACI, J. CHAZELAS, J.A. GUPTA, S.P. M CALLISTER 215th Electrochemical Society Meeting 2009, San Francisco, CA, USA,

120 114 Bi-Annual Report 2008/ Solid-State Electronics Department 26. Axial doping profile in VLS grown GaAs:Zn nanowires I. REGOLIN, C. GUTSCHE, A. LYSOV, W. PROST, M. MALEK, S. VINAJI (1), W. MERTIN (1), G. BACHER (1), M. OFFER (2), A. LORKE (2), F.-J. TEGUDE (1) Dept. of Materials for Electrical Engineering, University Duisburg Dept. of Materials for Electrical Engineering, University Duisburg (2) Dept. of Experimental Physics, University Duisburg-Essen Dept. of Experimental Physics, University Duisburg-Essen Europ. Workshop on MOVPE and Rel. Growth Techniques (EW MOVPE), Ulm, Germany, Ion Beam Induced Alignment of Semiconductor Nanowires C. BORSCHEL (1), R. NIEPELT (1), S. GEBURT (1), C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (2), D. SCHWEN (3), C. RONNING (1) Inst. for Solid-State Physics, University of Jena, Germany (2) IV. Inst. of Physics, University of Goettingen, Germany (3) Dept. of Materials Science and Engineering, University of Illinois, USA XVIII Int. Materials Research Congress 2009 (MRS), Cancun, Mexico, InP-based Unipolar Heterostructure Diodes for Vertical Integration and Level Shifting W. PROST, D. ZHANG, B. MÜNSTERMANN, A. POLOCZEK, F.-J. TEGUDE Topical Workshop on Heterostructure Microelectronics, Nagano, Japan InAs Nanowire Transistors with GHz Capability Fabricated Using Electric Field Assisted Self- Assembly K. BLEKKER, B. MÜNSTERMANN, I. REGOLIN, A. LYSOV, W. PROST, F.-J. TEGUDE Topical Workshop on Heterostructure Microelectronics, Nagano, Japan InAs nanowire MISFET: fabrication and characterization K. BLEKKER Seminar on Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems, Sophia University, Tokyo, Japan, Growth and Properties of III/V Nanowires C. GUTSCHE, I. REGOLIN, K. BLEKKER, A. LYSOV, W. PROST, F.-J. TEGUDE SFB 445 Klausurtagung / Workshop Historisch- Ökologische Bildungsstätte, Papenburg Axial Zinc doping profile in GaAs Nanowires A. LYSOV, I. REGOLIN, C. GUTSCHE, K. BLEKKER, M. OFFER (1), Z.-A. LI (1), M. SPASOVA (1), W. PROST, F.-J. TEGUDE (1) Dept. of Experimental Physics, University Duisburg-Essen Nanowire Growth Workshop, Paris, On the temporal behavior of DC and RF characteristics of InAs nanowire MISFET Y. OTSUHATA (1), T. WAHO (1), K. BLEKKER, W. PROST, F.-J. TEGUDE (1) Dept. of Electrical and Electronics Eng., Sophia University, 7-1 Kioicho, Chiyoda-ku, Tokyo, Japan Int. Semiconductor Device Research Symposium (ISDRS), College Park, MD, USA,

121 Conference Contributions Wachstum und Dotierung von InP Nanodrähten A. LYSOV, C. GUTSCHE, I. REGOLIN, K. BLEKKER, Z.-A. LI (1), M. SPASOVA (1), W. PROST, F.-J. TEGUDE (1) Dept. of Experimental Physics, University Duisburg-Essen 24. DGKK Workshop 'Epitaxie von III/V- Halbleitern', Berlin n-dotierung von GaAs Nanodrähten mittels TESn I. REGOLIN, C. GUTSCHE, A. LYSOV, K. BLEKKER, W. PROST, F.-J. TEGUDE 24. DGKK Workshop 'Epitaxie von III/V- Halbleitern', Berlin

122 116 Bi-Annual Report 2008/ Solid-State Electronics Department 4.5 Publications 1. Electrical Characterization of Spin Transistors Based on InAs Nanowires K. KONISHI (1), K. BLEKKER, W. PROST, K. YOH (1) (1) Division of Electronics for Informatics, Hokkaido University, Japan Proc. 'Japan Society of Applied Physics Spring Meeting, Funabashi, Japan, ' 2. High Frequency Characterisation of Single InAs Nanowire Field-Effect Transistor K. BLEKKER, Q.T. DO, A. MATISS, W. PROST, F.-J. TEGUDE Proc. 'IEEE Int. Conf. on InP and Related Materials 2008 (IPRM), Versailles, France, ' 3. Monostable-Bistable Threshod Logic Elements in a Fully Complementary Optical Receiver Circuit for High Frequency Applications A. MATISS, A. POLOCZEK, W. BROCKERHOFF, W. PROST, F.-J. TEGUDE Proc. 'IEEE Int. Conf. on InP and Related Materials 2008 (IPRM), Versailles, France, ' 4. Large-Signal Performance of Resonant Tunneling Diodes in K-Band Oscillators B. MÜNSTERMANN, A. MATISS, W. BROCKERHOFF, F.-J. TEGUDE Proc. 'Europ. Microwave Week / GAAS, EuMC, ECWT 2008 (EuMW), Amsterdam, The Netherlands, ' 5. P-Type Doping of GaAs Nanowires D. STICHTENOTH (1), K. WEGENER (1), C. GUTSCHE, I. REGOLIN, F.-J. TEGUDE, W. PROST, M. SEIBT (2), C. RONNING (3) (1) II. Inst. of Physics, University of Goettingen, Germany (2) IV. Inst. of Physics, University of Goettingen, Germany (3) Inst. for Solid-State Physics, University of Jena, Germany Appl. Physics Letters, Vol. 92, Multigigabit 1.3µm GaNAsSb/GaAs Photodetectors S. FEDDERWITZ (1), A. STÖHR (1), S.F. YOON (2), K.H. TAN (2), M. WEISS (1), W.K. LOKE (2), A. POLOCZEK, S. WICAKSONO (2), D. JÄGER (1) (1) Dept. of Optoelectronics, University Duisburg-Essen (2) School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore Appl. Physics Letters, Vol. 93, Wavelenght-Sensitivity Receiver for Simultaneous =1.3µm and =1.55µm RF Optical Transmission A. POLOCZEK, B. MÜNSTERMANN, I. NANNEN, I. REGOLIN, F.-J. TEGUDE Proc. 'IEEE Int. Conf. on InP and Related Materials (IPRM), Newport Beach, CA, USA, '

123 Publications Recent Progress in Dilute Nitride-Antimonide Materials for High Speed Photonics and Electronics S.F. YOON, K.H. TAN, W.K. LOKE, S. WICAKSONO, K.L. LEW, Z. XU, Y.K. SIM, T.K. NG, A. STÖHR, S. FEDDERWITZ, M. WEISS, A. POLOCZEK, D. J ÄGER, N. SAADSAOUD, E. DOGHECHE, M. ZEGAOUI, J.F. LAMPIN, D. DECOSTER, C. TRIPON-CANSELIET, S. FACI, J. CHAZELAS, J.A. GUPTA, S.P. M CALLISTER Proc. '215th Electrochemical Society Meeting 2009, San Francisco, CA, USA, ' 9. Alignment of Semiconductor Nanowires Using Ion Beams C. BORSCHEL (1), R. NIEPELT (1), S. GEBURT (1), C. GUTSCHE, I. REGOLIN, W. PROST, F.-J. TEGUDE, D. STICHTENOTH (2), D. SCHWEN (3), C. RONNING (1) (1) Inst. for Solid-State Physics, University of Jena, Germany (2) IV. Inst. of Physics, University of Goettingen, Germany (3) Dept. of Materials Science and Engineering, University of Illinois, USA Small, Vol. 5, No. 22, 2009, pp Material and Doping Transitions in Single GaAs-Based Nanowires Probed by Kelvin Probe Force Microscopy S. VINAJI (1), A. LOCHTHOFEN (1), W. MERTIN (1), I. REGOLIN, C. GUTSCHE, W. PROST, F.- J. TEGUDE, G. BACHER (1) (1) Dept. of Materials for Electrical Engineering, University Duisburg Nanotechnology, Vol. 20, GHz GaNAsSb Unitraveling-Carrier 1.3µm Photodetectors Grown by RF Plasma- Assisted Nitrogen Molecular Beam Epitaxy K.H. TAN, S.F. YOON (1), S. FEDDERWITZ (2), A. STÖHR (2), W.K. LOKE (1), S. WICAKSONO (1), T.K. NG (1), M. WEISS (2), A. POLOCZEK, V. R YMANOV (2), A. PATRA (2), E. TANGDIONGGA (3), D. JÄGER (2) (1) School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore, (2) Dept. of Optoelectronics, University Duisburg-Essen (3) Faculty of Electrical Eng., Eindhoven University of Technology, Eindhoven, The Netherlands IEEE Electron Device Letters, Vol. 30, No. 6, June 2009, pp µm GaNAsSb GaAs UTC-Photodetectors for 10-Gigabit Ethernet Links S. FEDDERWITZ (1), A. STÖHR (1), K.H. TAN (2), S.F. YOON (2), M. WEISS (1), A. POLOCZEK, W.K. LOKE (2), S. WICAKSONO (2), T.K. NG (2), V. R YMANOV (1), A. PATRA (1), E. TANGDIONGGA (3), D. JÄGER (1) (1) Dept. of Optoelectronics, University Duisburg-Essen (2) School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore, (3) Faculty of Electrical Eng., Eindhoven University of Technology, Eindhoven, The Netherlands IEEE Photonics Technology Letters, Vol. 21, No. 13, pp Controllable p-type Doping of GaAs Nanowires During Vapor-Liquid-Solid Growth C. GUTSCHE, I. REGOLIN, K. BLEKKER, A. LYSOV, W. PROST, F.-J. TEGUDE Journal of Applied Physics, 105, 2009

124 118 Bi-Annual Report 2008/ Solid-State Electronics Department 4.6 Research Projects Nano Particles from the Gas Phase Sonderforschungsbereich 445 (SFB 445) supported by Deutsche Forschungsgemeinschaft (DFG) together with other departments at the University Duisburg-Essen Nano Wires and Nano Tubes supported by Deutsche Forschungsgemeinschaft (DFG) RTD/HBT-Kombinationsbauelemente für Oszillatoranwendungen für die Satellitenkommunikation im Ku- und Ka-Band supported by German Aerospace Center (DLR) Optoelektronische Digitalschaltungen auf der Basis von Resonanztunneldioden und Photodioden den-arrays supported by Deutsche Forschungsgemeinschaft (DFG) NaSoL - Halbleiter-Nanodrähte für Solarzellen und Leuchtdioden supported by European Union Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems supported by Deutsche Forschungsgemeinschaft (DFG)

125 Bi-Annual Report 2008/ Solid-State Electronics Department Other Activities

126 120 Bi-Annual Report 2008/ Solid-State Electronics Department rd Nanowire Growth Workshop 2008 Introduction W. Prost (NWG Conference Chair 2008) The self-assembled growth of nanowires is presently a highly active research area, with a rapidly increasing amount of experimental data and theoretical modelling becoming available. However, the basic principles and mechanisms behind nanowire growth are still not completely understood. It is the mission of the Nanowire Growth Workshop to stimulate discussions and understanding of the general mechanisms and structural features behind self-assembled nanowire growth within the wide range of materials systems. The 3rd Nanowire Growth Workshop took place in Duisburg on Sept The sessions were held at the TECTRUM TOWER, a modern technology center and conference site build by Sir Norman Foster, which has hosted more than 60 nanowire researchers from all over the world. Scientific Programme The programme focused on the fundamental growth mechanism of: III-V and ZnO nanowires on various substrates such as III/V, Si, and other. The points of interest were the seeding aspects, the crystallinity, the doping, and novel approaches of self-assembly. More than 30 presentations were given in the sections of the workshop: (1) synthesis, (2) wurtzite to zinc-blende transition, (3) coreshell structures, (4) doping, and (5) ZnO and GaN. 200 nm Fig. 1 left: Logo of the Nanowire Growth Workshop: A set of GaAs nanowire seeded from an ultra thin and annealed Au-layer. They look like a couple of people talking to each other right: Cesare Soci and Lars Samuelson (Chairman) in front of the NWG 2008 audience.

127 3rd Nanowire Growth Workshop The workshop started with a detailed analysis of the MOVPE synthesis of GaAs and InAs nanowires by C. Soci from University of California at San Diego. The most intensively discussed topic of the workshop was the wurtzite to zinc-blende transition of III/V nanowires. The groups from Lunds University, Philips Eindhoven, CNRS Marcoussis, and University Duisburg Essen, achieved substantial progress in controlling and understanding crystal phase transitions in InAs, GaAs, and InP nanowires. The core-shell nanowire approach holds the promise to provide unique radial heterostructures for future optoelectronic and electronic applications. Recent progress was presented in various combinations: GaAs/AlGaAs (Juelich, Trondheim) InGaP/GaAs (Hamilton, Canada), InGaAs/GaAs (Trieste), and even GaN/ZnO (Ulm). The organizers of the NWG 2008 spend considerable attention to the doping of nanowires. Due to the low growth temperatures and the different growth schemes, the doping techniques of standard epitaxial growth are no longer valid and new approaches have to be developed. The current status of doping, both in the InP (Magnus T. Borgström, Lund) and in the GaAs (Ingo Regolin, Duisburg) material system was reviewed, while Daniel Stichtenoth (Göttingen) presented the additional doping capabilities of ion implantation. For a wide range of applications from optoelectronics to spintronics, Ga(In)N and ZnO are highly attractive materials especially at the nanoscale. Hence, seven papers -starting with Raffaella Callorco s presentation on MBE grown GaInN nanowires - intensively discussed the present status and future trends. Support We enjoyed being the host of 3rd Nanowire Growth Workshop 2008 in Duisburg. We hope that both the stimulating workshop site and the social events around the scientific program, has contributed to its obvious success. Let me finally thank those who made it easy for us to be your host: The Center of Excellence SFB 445 within its international exchange program, the European Integrated Project NODE, and the company Aixtron AG, Aachen, contributed substantially to this workshop. The Future This workshop followed the Lund Wire Growth Workshops in 2006 and 2007 mainly organized by Knut Deppert and his team. One of the important achievements of the 3 rd Nanowire Growth was the establishment of an international steering committee. Kenji Hiruma, Jean-Christophe Harmand, Erik Bakkers, Knut Deppert, Faustino Martelli, Anna Fontcuberta y Morral, Lutz Geelhaar, Stephen Hersee, Michael Heuken, Werner Prost, Helge Weman, and Margit Zacharias are commited to serve for the future of the workshop. The 4th Nanowire Growth Workshop will take place at CNRS, Paris, on Oct and will be organized by Jean-Christophe Harmand. Good Luck Jean Christophe and looking forward seeing you next October in Paris.

128 122 Bi-Annual Report 2008/ Solid-State Electronics Department Nanowire Growth Workshop 2008 Scientific Programme Synthesis Advances in Understanding the Synthesis of GaAs and InAs Nanowires by MOCVD; (invited) Cesare Soci, Shadi A. Dayeh, Xin-Yu Bao, and Deli Wang, University of California at San Diego Competitive growth process of tetrahedrons and hexagons during GaAs nanowire formation by metal organic vapour-phase epitaxy; K. Hiruma, K. Ikejiri, T. Sato, H. Yoshida, S. Hara, J. Motohisa, and T. Fukui, Hokkaido University, Sapporo, Japan. Influence of nitrogen carrier gas on SA-MOVPE of InAs nanowires; M. Akabori, K. Sladek, H. Hardtdegen, Jülich-Aachen Research Alliance, Juelich, Germany. SiO x -based growth of InAs 1-x P x nanowires; B. Mandl 1, J. Stangl 1, G. Bauer 1, E. Hilner 2, A. Mikkelsen 2, A. A. Zakharov 3, K. Deppert 4, L. Samuelson 4, M. Huber 5, 1 University Linz, Austria, 2 Synchrotron Radiation 3 MAXLAB, 4 Solid State Physics, 2-4 Lund University, Sweden, 5 RWTH Aachen, Germany. Pulsed Chemical Vapor Deposition of Single- Crystalline Antimony Selenide Nanowires, R. B. Yang, J. Bachmann, E. Pippel, A. Berger, J. Woltersdorf, U. Gösele, K. Nielsch*, Max Planck Institute of Microstructure Physics, Halle, *University of Hamburg, Germany InGaAs/InP lateral wire growth on SiO 2 /InP(00 1 ) masked substrates; M. Akabori, V. A. Guzenko, Th. Schäpers, H. Hardtdegen, Jülich-Aachen Research Alliance, Juelich, Germany. A novel effect of Sb on the crystalline structure of GaAs nanowires grown by MBE, D. L. Dheeraj, H. Zhou, B.O. Fimland, H. Weman, G. Patriarche 1, J.C. Harmand 1, University of Science and Technology,Trondheim, Norway, 1 CNRS-LPN, Marcoussis, France. Materials interactions during the growth of hybrid group III-V group IV nanowires; F. M. Ross, M. C. Reuter, K. A. Dick 1, T. J. Watson Research Center, Yorktown Heights, USA, 1 Lund University, Sweden. Nanowire Simulations from atomistic tool development to deployed tools on nanohub.org; G. Klimeck, M. Luisier, S. Mehrota, X. Wang, S.G. Kim, N. Neophytou, A. Paul, B. Haley, Network for Computational Nanotechnology, Purdue University, USA Wurtzite to Zinc-Blende Effects of supersaturation on the crystal structure of gold seeded III V nanowires; J. Johansson, K.A. Dick, J. Bolinsson, B.A. Wacaser, K. Deppert, L. Samuelson, 1 L.S. Karlsson, Solid State Physics, 1 Polymer & Materials Chemistry, Lund University, Sweden. Controlling the crystal structure of InAs nanowires: a wurtzite to zinc-blende transition; P. Caroff, K. A. Dick, J. Johansson, M. Messing, K. Deppert, and L. Samuelson, Solid State Physics, Lunds University, Sweden. Surface atomic structure of InAs nanowires as indicator of zincblende or wurtzite crystalline segments; P.Kratzer, University of Duisburg-Essen, Germany. Twinning superlattices in InP nanowires; R.E. Algra 1-3, M.A. Verheijen 1, M.T. Borgström 1, E.P.A.M. Bakkers 1, W.J.P. van Enckevort 3, E. Vlieg 3, 1 Philips Research Labs Eindhoven and Cedova, 2 Materials Innovation Institute, Delft, 3 Radboud University, Nijmegen, The Netherlands, 4 Solid State Physics, Lunds University, Sweden. Twinning during VLS growth of zincblende-structure nanowires; L.F. Feiner, R.E. Algra, and E.P.A.M. Bakkers, Philips Research Labs, Eindhoven, The Netherlands.

129 3rd Nanowire Growth Workshop Wurtzite to zinc-blende phase transition in GaAs nanowires induced by epitaxial burying; J.-C. Harmand, G. Patriarche, F. Glas, C. Sartel, L. Largeau, G. E. Cirlin 1, CNRS-LPN, Marcoussis, France, 1 Russian Academy of Sciences, St. Petersburg, Russia. Core-Shell Epitaxial growth of ZnO-GaN Hetero-Nanorods and GaN Nanotubes; F. Scholz 1, S.B. Thapa 1, J. Hertkorn 1, T.Wunderer 1, F. Lipski 1, A. Reiser 2, Y. Xie 2, M. Feneberg 2, K. Thonke 2, R. Sauer 2, M. Dürrschnabel 3, L.D. Yao, D. Gerthsen 3, 1 Optolektronik, 2 Semiconductor Physics, 1-2 Universität Ulm, 3 Inst. of Electron Microscopy, University of Karlsruhe, 1-3 Germany. InGaP Core-Shell Nanowires Grown by Molecular Beam Epitaxy; A. Fakhr 1, Y. M. Haddara 1, R. R. LaPierre 2, 1 Electrical & Computer Eng. and 2 Eng. Physics, 1-2 McMaster University, Hamilton, Canada. Growth, structural and optical characterizations of GaAs/AlGaAs core-shell nanowires grown by molecular beam epitaxy; H. Zhou 1, D.L. Dheeraj 1, T.B. Hoang 1, A.F. Moses 1, B.O. Fimland 1, H. Weman 1, A.T.J. van Helvoort 1,L. Liu 2 and J.C. Harmand 2, 1 University of Science and Technology,Trondheim, Norway, 2 CNRS-LPN, France. MOVPE of modulation doped GaAs/AlGaAs core-shell nanowires using alternative source materials, K. Sladek, V. Klinger, M. Akabori, H. Hardtdegen, and D. Grützmacher, Juelich-Aachen Research Alliance, Juelich, Germany. InGaAs/GaAs core shell nanowire by molecular beam epitaxy: Growth and optical characterization; F. Jabeena, S. Rubini, V. Grillo, L. Felisari, and F. Martelli, University of Trieste, also with Sinchrotron Trieste, Italy. Doping Growth and impurity doping of compound semiconductor nanowires; (invited) M. T. Borgström, Solid State Physics, Lunds University, Sweden. Ion implantation for the doping of compound semiconductor nanowires; (invited) D. Stichtenoth, S. Müller, K. Wegener, S. Geburt, C. Ronninga, University of Göttingen, anow with University of Jena, Germany. Doping of GaAs Nanowires; (invited) I. Regolin, A. Lysov, C. Gutsche, W. Prost, F.J. Tegude, CeNIDE, University Duisburg-Essen, Germany. Kelvin probe force microscopy as a tool for the characterization of single, semiconductor nanowires; S. Vinaji, A. Lochthofen, W. Mertin, G. Bacher, I. Regolin, C. Gutsche, K. Blekker, W. Prost, F.J. Tegude, CeNIDE, Universität Duisburg-Essen, Germany. ZnO and GaN Growth and characterization of Si and Mg doped GaN and InN nanowires, (invited) R. Calarco, T. Stoica, R.J. Meijers, T. Richter, K. Jeganathan 1, R. K. Debnath, M. Marso, Th. Schäpers, Ch. Blömers, S. Estevez Hernàndez, R. D. Frielinghaus, H. Lüth, E. Sutter 2, Research Centre Jülich, Germany, 1 also Bharathidasan University, India, 2 Brookhaven National Laboratory, Upton, USA. In situ-monitoring of the nucleation in catalyst-assisted growth of GaN nanowires, C. Chèze 1, L. Geelhaar 1, A. Trampert, H. Riechert 1, Paul Drude Institute, Berlin, 1 also Namlab Dresden and Qimonda Munich, Germany. Fabrication of ZnO Nanopillars in a Scalable AIXTRON CCS Reactor; A. Behrends, A. Bakin, A.Waag, B. Schineller 1, M. Heuken 1, TU Braunschweig, 1 AIXTRON, Aachen, Germany.

130 124 Bi-Annual Report 2008/ Solid-State Electronics Department Growth of GaN NanoLED structures on D patterned Silicon substrates by MOVPE, S. Li 1, S. Fündling 1, Ü. Sökmen 1, E. Peiner 1, H.-H. Wehmann 1, A. Waag 1, P. Hinze 2, T. Weimann 2, U. Jahn 3, A. Trampert 3, H. Riechert 3, 1 TU, 2 PTB, 1-2 Braunschweig, Paul-Drude-Institut, Berlin, Germany. A fast solution-based method for the large scale synthesis of ZnO; M. Palumbo, S.J. Henley, T. Lutz, C. Opoku, M. Shkunov, and S.R.P. Silva, University of Surrey, U.K. Effect of growth temperature on MOCVD grown ZnO nanostructures on silicon; J.-P. Biethan, L. Considine, D. Pavlidis, Darmstadt University of Technology, Germany. Au catalyst- and ZnO seed-assisted growth of ZnO nanowires; A. Reiser, V. Raeesi, Y. Xie, R. Frey, R. Sauer, and K. Thonke, Halbleiterphysik, Universität Ulm, Germany

131 Prof. Waho - Visiting Report Visiting Report: Prof. Takao Waho: A Nanoelectronic Circuit Designer from Sophia University, Tokyo Introduction W.Prost Sophia Univeristy is a private catholic school in the very city center of Tokyo. Its main campus at Yotsuya is located just between the imperal palace, the Tokyo station, and the sky scribers of Shinjuku. Sophia is a leading private University in Japan and was the first one with English taught programs. This University holds a very well established and famous faculty on Engineering and Applied Science. Prof. Takao Waho is one of its distinguished members. Scientific Programme Prof. Waho s research focussed on the circuit design of analog-to-digital converter. This converter is the key subcircuit in our analog world with its digital data processing. Despite tremendous efforts, the recent performance increase ot these circuits is limited. Prof. Waho s special research interest is to estalish emerging nanoelectronic devices such as resonant tunneling diodes, for further improvement in speed, resolution, and power consumption. In the summer 2008, he spent six weeks at the Solid-State Electroncis Department in order to figure out, what kind of role the novel ultra high gain InAs nanowire transistor may play in the field of analog-to-digital converter. Fig. 1 Prof. Takao Waho und Dr. Werner Prost characterising nanowire transistors in the lab of the Solid-State Electronics Department.

132 126 Bi-Annual Report 2008/ Solid-State Electronics Department The most important question at this early stage of development are: (1) what is the possible contribution of nanowire transistors to analog-to-digital converters (2) what are the challenges in order to make these devices ready for ciruit implementation. The Future It was a very lucky coincidence that during the stay, we received the information that the common proposal Nanowire/CMOS Heterogeneous Integration for Next-Generation Communication Systems was co-accepted by the Japanese Science and Technology Agency, and the Deutsche Forschungsgemeinschaft. The proposal was submitted by Prof. Takao Waho to the Strategic Japanese-German Cooperative Program on Nanoelectroncis. The collaborators are Prof. Koichi Maezawa (Toyama University), Dr. Werner Prost, and Prof. Dr. F.-J. Tegude (Solid-State Electronics Department). The project is devoted to the development of innovative approaches of heterogeneous integration of InAs nanowire MISFETs onto Si CMOS technology platform. The project includes fabricating InAs nanowire FETs and understanding nano-scale device physics. It also includes designing circuit based on device models reflecting the nanowire electronic properties, and creating a novel circuit architecture that exploits nanowire device unique characteristics. Acknowledgement: The Center of Excellence SFB 445 has substantially supported Prof. Takao Waho research stay in Duisburg.

133 Schueler Ingenieur Akademie / Junior-Ingenieur-Akademie Schueler-Ingenieur-Akademie / Junior-Ingenieur-Akademie I. Nannen, W. Brockerhoff Introduction The very small number of pupils who actually decide to start an engineering study becomes an increasing problem for the national economics. To increase the number of pupils interested in technical subjects the Schueler-Ingenieur-Akademie (SIA) as well as the Junior-Ingenieur- Akademie (JIA) were founded and supported by the German Telekom Foundation for three years.. The Schueler-Ingenieur-Akademie is focused to pupils in the 12th and 13th school year while the Junior-Ingenieur-Akademie adresses young people in the 8th and 9th school year. Within one run about 15 pupils from the Max-Planck Gymnasium, the Franz-Haniel Gymnasium and the Steinbart Gymnasium at Duisburg have the chance to get an overview about engineering activities at the university once per week for two years. Beside the Solid-State Electronic Department (HLT) departments of the Mechanical Engineerings as well as the Material Sciences are involved in this project. Parallel to practical exercises the group visits various laboratories within the department to get acquainted with research activities like the scanning electron microscopy, the e-beam technology, the facilities of the Center of Semiconductor and Optoelectronics (ZHO). The Task The project starts at the Solid-State Electronic Department. The task of the group is to realize an alarm system with a photoelectric barrier as alarm sensor. Fig. 1 shows a schematic including the components of the alarm system. alarm system activation switch-on delay input output alarm sensor light barrier Set analysis bistable logic signaler I light Reset key pad Reset signaler II acoustic Fig. 1 Schematic of the alarm system

134 128 Bi-Annual Report 2008/ Solid-State Electronics Department With the switch-on delay it is possible to start the system with an adjustable time delay. After this time delay the other components are activated. The photoelectric barrier consists of a white LED and a phototransistor. Interruption of the optical barrier leads to a switching of a flip flop as bistable gate. The alarm is displayed by a LED blinking light as well as by an acoustic signaler consisting of a hooter. A keypad is used to reset the alarm system; the user has to enter a code of three digits. The project starts with the fabrication of simple LED circuits to train the skills of soldering electronic parts and to work with semiconductor electronic devices. Fig. 2 Soldering one part of the alarm signal Within the next part several groups - consisting of 2 or maximum 3 pupils - are defined, each one with the task to realize one of the modules. In teamwork, the participants fabricates the circuits including handmade layout, computer-aided layout, etching and assembly of the boards. Fig. 3 shows the realized circuits.

135 Schueler Ingenieur Akademie / Junior-Ingenieur-Akademie 129 Fig. 3 Picture of the realized alarm system Fig. 4 Participants of the second "Schueler-Ingenieur-Akademie" from the Steinbart Gymnasium, Franz-Haniel Gymnasium and Max-Planck Gmynasium at Duisburg

136 130 Bi-Annual Report 2008/ Solid-State Electronics Department Guide to the Solid-State Electronics Department (HLT) Z entrum für H albleitertechnik und O ptoelektronik Lotharstr. 55, D Duisburg, Gebäude LT Travel by car: The Solid-State Electronics Department (HLT) at the ZHO (Zentrum für Halbleitertechnik und Optoelektronik) can be reached by car via various highways: A3 from the South, A40 from the Netherlands and the East, A2/A3 from the North. Exit: Duisburg-Kaiserberg or Duisburg-Wedau (see map). Travel by plane: After arriving at the Düsseldorf Airport (the next airport to Duisburg) take one of the various trains (S, RE, RB) from Düsseldorf Airport Train Station to Duisburg Main Station (Hauptbahnhof (Hbf). For further information see: Travel by train: The Duisburg Main Station (Hauptbahnhof (Hbf)) is in 25 min walking distance from the Solid-State Electronics Department (HLT)and the ZHO (see map). Take the bus lines 933, 936 or 924 to Universität/Städtische Kliniken and get off at Universität(Uni-Nord) or take the subway line 901 to Mülheim and get off at Universität.