Single-chip Cloud Computer IA Tera-scale Research Processor

Transcription

1 Single-chip Cloud Computer IA Tera-scale esearch Processor Jim Held Intel Fellow & Director Tera-scale Computing esearch Intel Labs August 31,

2 Agenda Tera-scale esearch SCC Architecture Software environment Co-travelers Program Summary 2

3 Performance Scaling Challenges Energy Efficiency Design Complexity Programming Models Emerging Applications 3

4 Tera-scale esearch Applications Identify, characterize & optimize Programming Empower the mainstream System Software Scalable services Memory Hierarchy Feed the compute engine Interconnects High bandwidth, low latency Cores power efficient general & special function 4

5 21.72mm Teraflops esearch Processor Technology Transistors Die Area PLL I/O Area 12.64mm I/O Area single tile 1.5mm C4 bumps # 2.0mm 65nm, 1 poly, 8 metal (Cu) 100 Million (full-chip) 1.2 Million (tile) 275mm 2 (full-chip) 3mm 2 (tile) 8390 TAP Goals: Deliver Tera-scale performance Single precision TFLOP at desktop power Frequency target 5GHz Bi-section B/W order of Terabits/s Link bandwidth in hundreds of GB/s Prototype two key technologies On-die interconnect fabric 3D stacked memory Develop a scalable design methodology d design approach Mesochronous clocking Power-aware capability 5

6 Within-Die Variation-Aware DVFS and scheduling Max Frequency variation per core 28% at 1.2V 62% at 0.8V No correlation die to die individual characterization required Improved performance or energy efficiency with: Multiple frequency islands Dynamic scheduling of processing to core 6 Dighe, S, et al., Within-Die Variation-Aware Dynamic Voltage-Frequency Scaling, Core Mapping and Thread Hopping for an 80-Core Processor, in Proceedings of ISSCC 2010 (IEEE International Solid-State Circuits Conference), Feb. 2010

7 Cloud datacenters: Cloud Computing Today 1000s of networked computers Millions of threads & petabytes of data Opportunity: Lower power, higher density via integration Greater efficiency and better programmability 45 Mb/s T3 to Internet (x4) (x4) (x4) (x8) (x4) (x4) (x4) Example: Intel s Open Cirrus testbed Intel Labs Pittsburgh (x2x5 p2p) (x8 p2p) (x4) (x4x4 p2p) (x4x4 p2p) (x15 p2p) (x15 p2p) (x15 p2p) 7

8 Motivations for SCC Many-core processor research High-performance power-efficient fabric Fine-grain power management Message-based programming support Parallel Programming research Better support for scale-out server model Operating system, communication architecture Scale-out programming model for client Programming languages, runtimes An experimental processor, not a product! 8

9 5.2mm 21.4mm Single-chip Cloud Computer Experimental Processor 3.6mm 26.5mm L2$1 Core1 outer MPB L2$0 Core0 DD3 MC DD3 MC PLL TILE TILE DD3 MC DD3 MC JTAG Technology Interconnect 45nm Hi-K CMOS 9 Metal (Cu) VC System Interface + I/O Transistors Die: 1.3B, : 48M Area 18.7mm 2 Die Area 567.1mm 2 9

10 Memory Controller Memory Controller Memory Controller Memory Controller Architectural Overview 2 nd Generation Intel Labs experimental processor IA-based software research vehicle Cluster-on-die architecture 48 Pentium Processor cores (P54C - x87fp only) L2$1 Core 1 outer MPB L2$0 Core 0 System I/F 10 Howard, J, et al., A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS, in Proceedings of ISSCC 2010 (IEEE International Solid-State Circuits Conference), Feb. 2010

11 Freq (GHz) On-die Interconnect Architecture 6x4 2D Mesh NOC 16B wide data links + 2B sideband 8 Virtual Channels in 2 classes Fixed (X-Y) routing Performance Target freq: 1.1V Link Bandwidth 64GB/s 4 cycle latency Power Management Independent Frequency & Voltage control Sleep mode, clock gating, low power F V 60MHz 50 C 0.94V 1.4GHz 0.73V 300MHz 0.94V 0.9GHz Supply (V) 1.34V 2.6GHz 1.32V 1.3GHz outer Core 11

12 Memory Memory Architecture Up to 64GB DD3 via 4 memory 21.3GB/s 16KB SAM in each tile as Message Passing Buffer (MPB) Caching 32KB L1 per core (16KB I,D), 12MB L2 cache (256KB/core) No HW cache-coherent shared memory Addressing Core physical to system physical addresses in 16MB sections Memory mapped configuration & control registers Core Physical Address Space Core Physical Address Space Physical-Physical Mapping Physical-Physical Mapping 12 System Physical Address Space

13 Memory Controller Memory Controller Memory Controller Memory Controller Power Management Configurable MC, Mesh, SIF Voltage & Frequency Software-controlled DVFS* of cores Fine-grain voltage control at 4 tile cluster level (6.25mV) Frequency control at tile level (16bit divider) Closed loop - thermal sensors per tile, current through BMC V F 0 n V F n 1 F n F n DVFS gives wide operating range: 1.14V 1GHz 0.7v 125MHz System I/F 13 *Dynamic voltage and frequency scaling

14 Measured full chip power 14 14

15 Power breakdown MC & DD % Full Power Breakdown Total W Cores 69% MC & DD % Low Power Breakdown Total W outers & 2Dmesh 10% Global Clocking 2% outers & 2Dmesh 5% Global Clocking 5% Cores 21% Clocking: 1.9W outers: 12.1W Cores: 87.7W MCs: 23.6W Cores-1GHz, Mesh-2GHz, 1.14V, 50 C Clocking: 1.2W outers: 1.2W Cores: 5.1W MCs: 17.2W Cores-125MHz, Mesh-250MHz, 0.7V, 50 C 15 15

16 ocky Lake SCC platform eplacement for evaluation board 100 boards with more I/O, more robust, less expensive BIOS/Firmware in definition 16

17 SCC Chipset System Interface FPGA Connects to SCC Mesh interconnect IO capabilities like PCIe, Ethernet & SATA Bitstream is part of scckit distribution Board Management Controller (BMC) JTAG interface for Clocking, Power etc. USB Stick with FPGA bitstream Network interface for User interaction via Telnet Status monitoring Firmware is part of scckit distribution 17

18 SCC Software Software Environment Bare Metal Customized Linux CCE communication & power management API Tools Selected Intel tools (e.g., icc, ifort,...) Microsoft research release of SCC extensions to Visual Studio Management Console PC Software PCIe driver with integrated TCP/IP driver Programming API for communication with SCC platform GUI for interaction with SCC platform Command line tools for interaction with SCC platform 18

19 CCE Communication API A compact, lightweight communication environment. SCC and CCE were designed together side by side: a true HW/SW co-design project. A research vehicle to understand how message passing APIs map onto many core chips. For experienced parallel programmers willing to work close to the hardware. Static SPMD Execution Model: identical UEs created together when a program starts (this is a standard approach familiar to message passing programmers) UE: Unit of Execution a software entity that advances a program counter (e.g. process of thread). 19

20 SCC Disclosure Demos Financial Analytics w/ shared virtual memory Microsoft Visual Studio Advanced Power Management JavaScript Physics Modeling HPC Parallel Workloads Hadoop Web Search 20

21 SCC Co-Travelers Program Currently building SCC software research community 100 systems total, with 40 in Oregon Datacenter esearch partners for 2010 have been selected SCC community website available today Communities.intel.com/community/marc To share ideas, HowTo s, code, tools 21

22 Summary SCC provides a unique experimental platform for many-core research Better support for Cloud data center servers Scale-out programming model for client We are sharing SCC with selected researchers in academia and industry Documentation and presentations

23 SCC Team Jason Howard, Saurabh Dighe, Yatin Hoskote, Sriram Vangal, David Finan, Gregory uhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabrice Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael iepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, ob Van Der Wijngaart, Timothy Mattson 23

24 24 Questions?

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