The System Designer's Guide to VHDL-AMS

Transcription

1 The System Designer's Guide to VHDL-AMS Analog, Mixed-Signal, and Mixed-Technology Modeling Peter J. Ashenden EDA CONSULTANT, ASHENDEN DESIGNS PTY. LTD. VISITING RESEARCH FELLOW, ADELAIDE UNIVERSITY Gregory D. Peterson UNIVERSITY OF TENNESSEE DarrellA. Teegarden MENTOR GRAPHICS CORPORATION MORGAN KAUFMANN PUBLISHERS AMST AN IMPRINT OF ELSEVIER

2 Contents Preface xix Fundamental Concepts 1.1 Modeling Systems Domains and Levels of Modeling 5 Digital Modeling Example 5 Analog Modeling Example 10 Mixed-Signal Modeling Example 12 Energy Domains and Conservation Modeling Languages VHDL-AMS Modeling Concepts 15 Elements of Behavior 16 Elements of Structure 18 Mixed Structural and Behavioral Models 21 Test Benches 21 Analysis, Elaboration and Execution Learning a New Language: Lexical Elements and Syntax Lexical Elements 27 Syntax Descriptions 32 Exercises Scalar Data Types, Natures and Operations 2.1 Constants and Variables 40 Constant and Variable Declarations 40 Variable Assignment Scalar Types 43 Type Declarations 43 Integer Types 44 Floating-Point Types 46 Physical Types 48 Enumeration Types IX

3 x Contents 2.3 Type Classification 57 Subtypes 57 Type Qualification 60 Type Conversion Scalar Natures 61 Nature Declarations 6l Standard Natures 64 Subnatures Attributes of Scalar Types and Natures Expressions and Operators 70 Exercises 72 3 Sequential Statements If Statements Case Statements Null Statements Loop Statements 86 Exit Statements 87 Next Statements 90 While Loops 91 For Loops 93 Summary of Loop Statements Assertion and Report Statements 96 Exercises 102 4t Composite Data Types and Operations Arrays 106 Multidimensional Arrays 111 Array Aggregates 113 Array Attributes Unconstrained Arrays 118 Strings 120 Real Vectors 120 Bit Vectors 121 Standard-Logic Arrays 121 String and Bit-String Literals 121 Unconstrained Array Ports Array Operations and Referencing 123 Array Slices 125 Array Type Conversions Records 127 Record Aggregates 131 Exercises 132

4 Contents XI Digital Modeling Constructs Entity Declarations Architecture Bodies 138 Concurrent Statements 139 Signal Declarations Digital Behavioral Descriptions 141 Signal Assignment 141 Signal Attributes 144 Wait Statements 146 Delta Delays 150 Transport and Inertial Delay Mechanisms 153 Process Statements 160 Concurrent Signal Assignment Statements 161 Concurrent Assertion Statements 167 Entities and Passive Processes Digital Structural Descriptions 170 Component Instantiation and Port Maps 170 Exercises 179 Analog Modeling Constructs Free Quantities 188 Quantity Ports Terminals and Branch Quantities 192 Terminal Declarations 192 Branch Quantity Declarations 193 Terminal Ports Attributes of Terminals and Quantities 201 Attributes of Terminals 202 Attributes of Quantities 202 Quantity Attributes of Signals Simultaneous Statements 217 Simple Simultaneous Statement 218 Simultaneous If Statement 221 Simultaneous Case Statement 224 Simultaneous Null Statement Analog Structural Descriptions Discontinuities and Break Statements 232 Concurrent Break Statements Step Limit Specifications Mixed-Signal Descriptions 247 Analog-to-Digital Conversion 248 Digital-to-Analog Conversion Mixed-Technology Descriptions 253 Exercises 256.

5 Xll Contents 8 10 Design Processing 7.1 Analysis 262 Design Libraries, Library Clauses and Use Clauses 7.2 Elaboration 269 Requirements for Solvability Execution 277 Exercises 280 Case Study 1: Mixed-Signal Focus 8.1 System Overview Command and Control System Design 282 Control Sticks 283 Digitize/Encode Block 283 Decoder/Pulse-Width Block 290 Pulse-Width/Analog Converter Design Trade-Off Analysis 294 Converter Accuracy 295 System Analysis 296 Exercises 299 Subprograms 9.1 Procedures 304 Return Statement in a Procedure Procedure Parameters 310 Signal Parameters 314 Default Values 317 Unconstrained Array Parameters 319 Summary of Procedure Parameters Concurrent Procedure Call Statements Functions 325 Functional Modeling 327 Pure and Impure Functions 327 Functions in Simultaneous Statements 329 The Function Now Simultaneous Procedural Statements Overloading 338 Overloading Operator Symbols Visibility of Declarations 341 Exercises 345 Packages and Use Clauses 10.1 Package Declarations 350 Subprograms in Package Declarations 355 Constants in Package Declarations

6 Contents xiii 10.2 Package Bodies Use Clauses The Predefined Package Standard IEEE Standard Packages 364 Std_Logic_ll64 Multivalue Logic System 364 '""" Standard VHDL Synthesis Packages 366 Standard VHDL Mathematical Packages 366 Proposed Standard Analog Packages 371 _ Exercises Aliases Aliases for Data Objects Aliases for Non-Data Items 383 Exercises Generic Constants Parameterizing Behavior Parameterizing Structure 394 I Exercises 398 j 13 Frequency and Transfer Function Modeling Frequency-Based Modeling 402 j Spectral Source Quantities Noise Modeling Laplace Transfer Functions Discrete Transfer Functions and Sampling 423 Zero-Order Hold (ZOH) 423 Z Transfer Function (ZTF) 426 Summary of Transfer Function Attributes 428 Z-Domain Sampling 431 Exercises 433 j.. '! 14 Case Study 2: Mixed-Technology Focus 437 j 14.1 Rudder System Overview 438 Rudder System Specifications and Development 439 I Domain Implementation 440 j Servo Controller 441 i Motor Model 444 Gearbox 446 \ Rudder Load Domain System Performance 447 j Mixed Mechanical/5-Domain Implementation 454 \ Servo/Amplifier 455 Motor Model 455

7 xiv Contents Gearbox 457 Control Horn Assembly 458 Rudder Model Design Trade-Off Analysis 461 Deriving Z-Domain Coefficients 463 Implement Compensator as Difference Equations 464 Exercises Resolved Signals Basic Resolved Signals 470 Composite Resolved Subtypes 474 Summary of Resolved Subtypes IEEE Std_Logic_ll64 Resolved Subtypes Resolved Signals and Ports 481 Resolved Ports 483 Driving Value Attribute Resolved Signal Parameters 485 Exercises 487 1() Components and Configurations Components 494 Component Declarations 494 Component Instantiation 495 Packaging Components Configuring Component Instances 498 Basic Configuration Declarations 498 Configuring Multiple Levels of Hierarchy 501 Direct Instantiation of Configured Entities 504 Generic and Port Maps in Configurations 505 Deferred Component Binding Configuration Specifications 514 Incremental Binding 515 Exercises 521 IT Generate Statements Generating Iterative Structures Conditionally Generating Structures 536 Recursive Structures Configuration of Generate Statements 543 Exercises Case Study 3: DC-DC Power Converter Buck Converter Theory and Design 558 Selecting a Switching Regulator Topology 558

8 : i Contents XV 18.2 Modeling with VHDL-AMS 565 : Capacitor Model 565 Ideal Switch Model Voltage-Mode Control Averaged Model Closing the Loop 571. Compensation Design 572 Load Regulation 576 Line Regulation Design Trade-Off Study 578 Exercises Guards and Blocks Guarded Signals and Disconnection 586 The Driving Attribute 591. Guarded Ports 591 Guarded Signal Parameters Blocks and Guarded Signal Assignment 595 Explicit Guard Signals 598 Disconnection Specifications Using Blocks for Structural Modularity 601 Generics and Ports in Blocks 604 Configuring Designs with Blocks 605 Exercises Access Types and Abstract Data Types Access Types 6l4 Access Type Declarations and Allocators 614 Assignment and Equality of Access Values 617 Access Types for Records and Arrays Linked Data Structures 620 Deallocation and Storage Management Abstract Data Types Using Packages 626 Container ADTs 631 Exercises Files and Input/Output Files 644 File Declarations 644 : ; Reading from Files 645 Writing to Files 648 Files Declared in Subprograms 651 Explicit Open and Close Operations 653 File Parameters in Subprograms 656

9 xvi Contents Portability of Files The Package Textio 658 Textio Read Operations 660 Textio Write Operations 664 Reading and Writing User-Defined Types 667 Exercises 667 Attributes and Groups 22.1 Predefined Attributes 672 Attributes of Scalar Types 672 Attributes of Scalar Natures 673 Attributes of Array Types and Objects 673 Attributes of Signals 674 Attributes of Terminals 675 Attributes of Quantities 675 Attributes of Named Items User-Defined Attributes 683 Attribute Declarations 683 Attribute Specifications 684 The Attribute Foreign Groups 696 Exercises 699 Case Study 4: Communication System 23.1 Communication System Overview Frequency Shift Keying FSK Detection 708 Non-Coherent Detection 709 Phase-Locked Loop Detection Trade-Off Study 714 Exercises 716 Miscellaneous Topics 24.1 Buffer and Linkage Ports Conversion Functions in Association Lists Postponed Processes Shared Variables 730 Exercises Integrated System Modeling 25.1 Top-down Design System Specification Partitioning the System

10 Contents xvii 26 B C D E 25.4 Refining the Design Model Calibration System Verification Synthesis and Reuse Design Trade-Offs and Optimization 746 Architectural Trade-Offs 747 Parametric Analysis 747 Optimization 747 Response Surface Models 748 Exercises 749 Case Study 5: RC Airplane System 26.1 RC System Overview Interfacing Command and Control to the Rudder System System Power Supply Effects 754 Supply Level and Servo Error 755 Rudder Servo with Buck Converter Propeller System 762 Propeller System Performance Human Controller 770 Modeling the Human 770 System Accuracy Summary 773 Exercises 774 Using SPICE Models in VHDL-AMS A.1 SystemVision/ADMS (Mentor Graphics Corporation) 777 A.2 VeriasHDL (Synopsys, Inc.) 780 A3 Auriga (FTL Systems, Inc.) 782 The Predefined Package Standard IEEE Standard Packages C.l' Std_Logic_ll64 Multivalue Logic System 789 C.2 Standard VHDL Mathematical Packages Related Standards D.I IEEE VHDL Standards 797 D.2 Other Design Automation Standards 801 VHDL-AMS Syntax E.I Design File 809 E.2 Library Unit Declarations

11 xviii Contents E.3 Declarations and Specifications 811 E.4 Type Definitions 813 E.5 Concurrent Statements 814 E.6 Simultaneous Statements 816 E.7 Sequential Statements 817 E.8 Interfaces and Associations 819 E.9 Expressions 819 F Answers to Exercises 821 G CD-ROM Guide 851 References 853 Index 857