Maciej Ciesielski Ph.D. in Electrical Engineering, University of Rochester, Department of Electrical

Transcription

1 Maciej Ciesielski URL: University of Massachusetts Department of Electrical & Computer Engineering Amherst, MA phone: (413) , Fax: (413) PROFESSIONAL EXPERIENCE: 1987-present 2003-present Professor (since 2003). University of Massachusetts, Department of Electrical & Computer Engineering, Amherst, MA. Conducting research in computer-aided design, design automation and verification for integrated circuits and systems. Teaching graduate and undergraduate courses in CAD, VLSI design, hardware design, computer architecture, freshmen engineering. Supervising VLSI CAD laboratory. Founder of LogicMill Technology, LLC, an Electronic Design Automation (EDA) company developing software for synthesis and verification of integrated circuits and systems. Web information: Assistant Professor. University of Lowell, Computer Science Department, Lowell, MA. Taught senior and graduate level courses in Computer Architecture and a two-semester senior level course in VLSI Design. Initiated research in VLSI physical design automation, performance optimization, and VLSI interconnect modeling Senior Member of Technical Staff. GTE Laboratories, Computer Science Laboratory, Waltham, MA. Conducted research in physical design automation for SILC silicon compiler Research Fellow and Teaching Assistant. University of Rochester, Department of Electrical Engineering. Performed research in computer-aided layout design for VLSI circuits. Instructed the lab for the graduate level VLSI Design course Senior Assistant and Lecturer. Institute of Electron Technology, Warsaw Technical University, Warsaw, Poland. Taught undergraduate courses and lab in Semiconductor Devices Theory and Design of Analog Integrated Circuits. Conducted research in computer aided design of analog ICs, modeling of bipolar devices and layout design methods for analog and hybrid electronic circuits. EDUCATION: 1983 Ph.D. in Electrical Engineering, University of Rochester, Department of Electrical Engineering, Rochester, N.Y M.S. in Electrical Engineering, Institute of Electron Technology, Warsaw Technical University, Warsaw, Poland. 1

2 RESEARCH PROFILE: Electronic Design Automation and CAD for VLSI circuits and systems. Specifically, the research is being conducted in the following directions: Design validation and formal verification. Behavioral and logic synthesis from high-level specifications. Physical design automation, VLSI layout synthesis. Ph.D. DISSERTATIONS SUPERVISED: 1. Zhihong Zeng, Word-level Satisfiability in Semi-formal Verification Oct Priyank Kalla, An Infrastructure for RTL Validation and Verification, May Congguang Yang, BDD-based Logic Synthesis System, Nov Balakrishnan Iyer, Performance-driven Synthesis of Sequential Circuits, Oct Maya Yajnik (Co-advisor), Measurement and Modeling of Packet Loss in the Internet, Oct Pramavir Bahl (Chair/co-advisor), Real Time Visual Communication over Broad-Band Wireless Radio Network, May, Chang-Jin Suh (Chair/co-advisor), Switched Delay using Multiple-length Delay Lines in Optical Network, Ph.D. dissertation, University of Massachusetts, Dec Zafar Hasan, High Performance Issues in Sequential Optimization, Ph.D. dissertation, University of Massachusetts, Feb Donald A. Joy, Clock Period Minimization with Wave Pipelining, Ph.D. dissertation, University of Massachusetts, Aug Saeyang Yang, Analytical Approach to VLSI Logic Synthesis, Ph.D. dissertation, University of Massachusetts, Feb TEACHING: courses taught at the University of Massachusetts 1. VLSI Design Principles (undergraduate version), Advanced VLSI Design (graduate version), and VLSI Design Project sequence. 2. CAD Techniques for VLSI synthesis, graduate level; developed a new course with manuscript. 3. Hardware Organization and Design; undergraduate. 4. Computer Architecture; undergraduate and graduate levels. 5. Logic Synthesis and Verification; graduate level. 6. Switching Theory, senior/graduate level. 7. Introduction to Engineering; freshmen engineering course for ECE students. Developed the course in 1996, and prepared a set of manuscripts; supervised its pilot version in 1996 and taught it in 1996 and Logic Synthesis, a short summer course offered by National Technological University, Another version of the course was taught at Texas A&M University in Logic Synthesis Tutorial, a 2-day course offered at Digital Equipment Corporation in

3 10. Physical Design Synthesis for VLSI, a short summer course offered by National Technological University, Physical Design Automation for VLSI. Developed a new course, registered under ECE Synthesis and Verification of Digital Systems. Proposed as a new course, registered under ECE 667. RESEARCH GRANTS 1. National Science Foundation, Covalidation of Timing Faults in Hardware-Software Systems, Award No. CCF , subaward from Univ. of California Irvine, $ 63,794, 08/31/03-08/31/ National Science Foundation, International NSF/CNRS/DAAD Grant, US-France/Germany Cooperative Activity: Behavioral and RTL Verification based on Taylor Expansion Diagrams, PI, $22,060, Feb July (foreign collaborators receive separate funding from their respective agencies). 3. National Science Foundation, Design Automation Program, Award No. CCR , Taylor Expansion Diagrams, a Word-level Representation for RTL Verification, Sole PI, Oct Sept. 2005, $280, Avery Design Systems, industrial grant, Functional Testing. Sole PI, , $77, National Science Foundation, Design Automation Program, Award No. CCR , Logic- Layout Co-synthesis for PTL/CMOS Logic Sole PI, Sept Aug. 2002, $250, National Science Foundation grant EIA ($470,000) and the University of Massachusetts ($266,106 match), Multimedia Systems: An Integrated Modular Curriculum. PIs: Burleson, Ciesielski, Ganz, Harris, Koren, Krishna. Aug Jul National Science Foundation, GOALI program, Award No. MIP New Directions in Sequential Synthesis and Optimization, sole PI, , $278, Compaq, Alpha Development Group, industrial grant, Datapath Layout Synthesis. Sole PI, , $42, National Science Foundation, Award No. MIP , High-Performance VLSI Synthesis with Wave Pipelining Co-PI with W. Burleson, $252,380, Sept Aug NSF, Award No. INT , with W. Burleson, International Cooperation for High- Performance VLSI Synthesis with Wave Pipelining, $16,230, Funding for international cooperation with researchers in Pusan, Korea. 11. Faculty Research Grant, Healy Endowment, University of Massachusetts, VLSI Logic Synthesis with Implicit Retiming, $5,000, PI, Sept Aug Faculty Teaching Grant, UMASS Center for Teaching, International Collaboration for Electronic Design via the World Wide Web, with W. Burleson, $1,500, Professional Development Grant for Instructional Technology in Academic Development. UMASS President s Office, International Collaboration for Electronic Design via the World Wide Web, with W. Burleson, $4,000, 6/1/96-5/31/97. 3

4 14. NSF, Award No. CDA , Co-PI with six other faculty in ECE Dept., CSE group. CISE Instrumentation, Equipment grant for VLSI testing and workstations, $40,000, April Oct National Science Foundation, Award No. MIP , FSM Decomposition for Area and Performance Optimization, PI, with Israel Koren as Co-PI, $151,500, March Aug National Science Foundation, Research Initiation Grant, Award No. MIP , Interconnect Delay and Clock Skew Minimization in VLSI Circuits, PI, $60,000, Sept Feb SIGDA-ACM Design Automation graduate scholarship award, Clock Period Minimization in Standard Cell Layout, $12,000, academic year 1990/ Faculty Research Grant, University of Massachusetts, Award No , Multiple-valued Minimization of Boolean Functions, $5,000, PI, Nov Oct SOFTWARE DEVELOPED BDS, a BDD-based Logic Synthesis System. This fast and efficient logic synthesis tool is based on the original theory of BDD-based logic decomposition. It provides both algebraic and Boolean decomposition of Boolean logic. BDS-1.2 is available at the following link: TEDify, a CAD software to generate and optimize Taylor Expansion Diagrams (TED), a novel, canonical, graph-based representation for arithmetic expressions of data flow designs. TEDs can be used for verification and optimization of mathematical expressions derived from DSP designs and other high-level design specifications. TEDify is available on the web at: PROFESSIONAL ACTIVITIES Senior Member of the IEEE, Circuits and Systems Society. Member of the CNRS (Centre National de Recherche National) accreditation team evaluating LIRMM (Laboratoire de l Informatique, Robotique et Microelectronique de Montpellier), a research lab associated with the University of Montpellier, France, June Member of NSF proposal review panel (CAREER award), 2001, Frequent reviewer of NSF proposals. International Conference on Electronics, Circuits and Systems, ECECS-2002, Program Committee Topics Chair, IFIP Intl. Conference on Very Large Scale Integration, VLSI-SOC 2001, VLSI 99, VLSI 97, Technical Program Committee, session chair. Invited two-day course in Logic Synthesis, Digital Equipment Corporation, Hudson, MA, Jan Invited short course in Logic Synthesis, Texas A & M University, May Intl. Symposium on Circuits and Systems, London, 1994, Co-organizer and member of the panel, Is Wave-Pipelining Practical. 4

5 IFIP Intl. Workshop on Architectural and Logic Synthesis, Grenoble, France, , Member of Technical Program Committee and Session Organizer. International Conference on Computer-Aided Design (ICCAD), , Member of Technical Program Committee and Session Chairman, International Conference on Computer Design (ICCD), 1992, Member of Technical Program Committee. International Workshop on Logic Synthesis, 1991, 1993, Technical Program Committee and Session Chairman (1991). International Symposium on Circuits and Systems (ISCAS), 1989, invited Tutorial VLSI Logic Synthesis. Short summer course VLSI Logic Synthesis, NTU Satellite Network, Short summer course CAD Techniques for VLSI: Theory & Applications, NTU Satellite Network, Guest lecturer, VLSI Design, GE Technical Lecture Series, Feb Reviewer of various journals: IEEE Trans. on CAD, IEEE Trans. on Computers, IEEE Trans. on VLSI Systems, Journal of ACM, ACM Trans. on Design Automation of Electronic Systems; conferences: ICCAD, DAC, ICCD, IWLS, IWLAS, VLSI; and books: McGraw-Hill, Kluwer, PWS. Presenter, invited talks and seminars: Universities: University of California: Berkeley, San Diego, Santa Barbara; University of Souther California, Los Angeles; Carnegie-Mellon University, Pittsburgh; University of Washington, Seattle; University of Rochester, NY; Boston University, MA; Tufts University, MA; University of Montpellier, France; Ecole Nationale Supérieure de Télécommunication, TELECOM Paris; Institute National Politechnique de Grenoble, France; Catholic University of Louvain, Belgium; University of Karlsruhe, Germany; Eindhoven University of Technology, Holland; Pusan National University, Korea; Warsaw Technical University, Poland; Laboratoire d Informatique, Robotique et Microelectronique, Université de Montpellier, France; Unviersité de Bretagen Sud, Lorient, France; Institut Supérieur d Electronique de Paris, ISEP, France. Industry and Research Labs: IBM T.J. Watson Research Center, Yorktown Heights, N.Y.; Intel, Portland, OR; Advanced Micro Devices, Austin, TX; Cadence Design Systems, Chelmsford. MA; Synopsys, Portland, OR. AT&T Bell Labs, Murray Hill, N.J.; Digital Equipment Corporation, Hudson, MA; Compaq Computer Corporation, Shrewsbury, MA. Mentor Graphics, Billerica, MA. Micro Networks, Worcester, MA; Philips Research Labs. Brussels, Belgium; Philips Research Labs. Eindhoven, Holland; Compass Design Automation, San Jose, CA, and Sophia Antipolis, France; Samsung, Soeul, Korea; Soedu, Soeul, Korea; Electronics and Telecommunications Research Institute (ETRI), Taejon, Korea; 5

6 PATENTS M. Ciesielski, S. Askar, and E. Boutillon, Behavioral Synthesis based on Taylor Expansion Diagrams, University of Massachusetts, Amherst, Provisional Patent, No. 60,633,025, No. UMA-8426, Dec. 03, M. Ciesielski, S. Askar, E. Boutillon, and J. Guillot, Behavioral Transformations for Hardware Synthesis and Code Optimization based on Taylor Expansion Diagrams US Utility patent, USSN 11/292,493, filed 12/02/2005, and PCT application PCT/US05/43860, filed 12/03/2005. PUBLICATIONS Journals and Book Chapters 1. M. Ciesielski, P. Kalla, and S. Askar, Taylor Expansion Diagrams: A Canonical Representation for Verification of Dataflow Designs, IEEE Transactions on Computers, in 2nd review (2004, 2005). 2. Z. Zeng, K.R. Talupuru, and M. Ciesielski, Functional Test Generation based on Word-level SAT, in Journal of Systems Architecture, Elsevier Publishers, Vol. 51, Issue 8, August 2005, pp M. Ciesielski, S. Askar, S. Levitin, Analytical Approach to Layout Generation of Datapath Cells, IEEE Trans. on Computer-Aided Design, Vol. 21, No. 12, pp , Dec C. Yang, M. Ciesielski, BDS: A BDD-based Logic Optimization System, IEEE Trans. on Computer- Aided Design, Vol. 21, No. 7, pp , July P. Kalla, M. Ciesielski, A Comprehensive Approach to Partial Scan Problem using Implicit State Enumeration, IEEE Trans. on Computer-Aided Design, Vol. 21, No. 7, pp , July Z. Zeng, M. Ciesielski, B. Rouzeyre, Functional Test Generation using Constraint Logic Programming, in SOC Design Methodologies, Kluwer Academic Publishers, pp , P. Kalla, Z. Zeng, M. Ciesielski, Strategies for Solving the Boolean Satisfiability Problem using Binary Decision Diagrams, in Journal of Systems Architecture, Vol. 47/6, pp , Sept M. Fujita, Y. Matsunaga, M. Ciesielski, Multi-Level Logic Optimization, in Logic Synthesis and Verification, Kluwer Academic Publishers, ed. by T. Sasao and S. Hassoun. Chapter 2, pp , Aug (invited book chapter). 9. S. Bommu, N. O Neill, M. Ciesielski, Retiming-Based Factorization for Sequential Logic Optimization ACM Trans. on Design Automation on Electronic Systems, July Vol.5, Issue 3, pp P. Kalla, M. Ciesielski, Logic Testing, invited article. Wiley Encyclopedia of Electrical and Electronics Engineering, Vol. 11, John Wiley & Sons, pp , W. Burleson, M. Ciesielski, F. Klass, W. Liu. Wavepipelining: A Tutorial and Survey of Recent Research, IEEE Transactions on VLSI, Vol.6, No.3, Sept. 1998, pp S.K. Bommu, M. Ciesielski, N. O Neill, P. Kalla, Sequential Logic Optimization with Implicit Retiming and Resynthesis in VLSI: Integrated Systems on Silicon, ed. R. Reis, L. Claesen, Chapman & Hill, 1997, pp Z. Hasan and M. Ciesielski, FSM Decomposition and Functional Verification of FSM Networks, VLSI Design: An International Journal of Custom-Chip Design, Simulation and Testing, Gordon and Breach Publishers, Vol.3, No. 3-4, pp ,

7 14. Z. Hasan, M. Ciesielski, On Multi-Cycle False Paths in Sequential Circuits, in Logic and Architecture Synthesis; State-of-the Art and Novel Approaches, Chapman & Hall, 1995, pp D. Joy and M. Ciesielski, Clock Period Minimization with Wave Pipelining, IEEE Trans. on Computer-Aided Design, Vol.12, No.4, pp , April Z. Hasan, D. Harrison, and M. Ciesielski, Fast Partitioning Method for PLA-Based FPGAs, IEEE Design & Test of Computers, pp , Dec M. Ciesielski and S. Yang, PLADE: A Two-Stage PLA Decomposition, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp , Aug D. Joy and M. Ciesielski, Layer Assignment for Printed Circuit Boards and Integrated Circuits, Proceedings of the IEEE, pp , Feb S. Yang and M. Ciesielski, Optimum and Suboptimum Algorithms for Input Encoding and its Relationship to Logic Minimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.10, N0.1, pp. 4-12, Jan M. Davio and M. Ciesielski, State Assignment Using Programmable Counters, Electronics Letters, Vol. 27, No. 1, Jan. 1991, pp M. Ciesielski, Layer Assignment for VLSI Interconnect Delay Minimization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8, No. 6, pp , June M. Ciesielski, E. Kinnen, Digraph Relaxation for 2-D Placement of IC Blocks, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-6, No. 1, January 1987, pp M. Ciesielski, Two-Dimensional Routing for the Silc Silicon Compiler, IEEE Trans. on Computer- Aided Design of Integrated Circuits and Systems, Vol. CAD-4., No. 3, July 1985, pp R. Kubiak, M. Ciesielski, Placement Algorithm for Automatic IC Layout Design System, Journal of Design Automation and Fault Tolerant Computing, July 1978, pp M. Ciesielski, A. Szepieniec, Selected Problems in Computer-Aided Design of IC Topology, IET Reports, No. 20, August 1975, pp (in Polish). Refereed Conference Proceedings 1. J. Guillot, E. Boutillon, D. Gomez-Prado, Q. Ren, and M. Ciesielski, Application of Taylor Expansion Diagrams to Factorization of Algebraic Expressions, submitted to Intl. Design Automation Conference, DAC-06, July J. Guillot, E. Boutillon, D. Gomez-Prado, S. Askar, Q. Ren, and M. Ciesielski, Efficient Factorization of DSP Transforms using Taylor Expansion Diagrams, Design, Automation and Test Conference in Europe, DATE 06, March F. Xin, M. Ciesielski, I. Harris, Design Validation of Behavioral VHDL Descriptions for Arbitrary Fault Models, European Test Symposium, May A. Mishchenko, S. Chatterjee, R.K. Brayton, M. Ciesielski, Multi-Objective Optimization during Technology Mapping, IEEE Intl. Workshop on Logic Synthesis, IWLS-05, June Z. Wo, I. Koren, M. Ciesielski, An ILP Formulation for Yield-driven Architectural synthesis, Defect and Fault Tolerance in VLSI Systems Symposium, D. Gomez-Prado, Q. Ren, S. Askar, M. Ciesielski, E. Boutillon, Variable Ordering for Taylor Expansions Diagrams, IEEE Intl. High Level Design Validation and Test Workshop, HLDVT-04, pp , Nov

8 7. S. Park, S. Cho, S. Yang, and M. Ciesielski, A New State Assignment Technique for Testing and Low Power, Proc. ACM/IEEE Design Automation Conference, DAC-2004, pp , June Q. Zhang, Z. Zeng, M. Ciesielski, A Range-Based BDD Minimization Algorithm, IEEE Intl. Workshop on Logic Synthesis, IWLS-04, pp , June Grschwin Fey, Rolf Drechsler and Maciej Ciesielski, Algorithms for Taylor Expansion Diagrams, Proc. IEEE International Symposium on Multi-Valued Logic (ISMVL 2004), Toronto, D. Pradhan, S. Askar, M. Ciesielski, Mathematical Framework for Representing Discrete Functions as Word-level Polynomials, IEEE Intl. High Level Design Validation and Test Workshop, HLDVT-03, pp , Nov Z. Zeng, Q. Zhang, I. Harris, M. Ciesielski, Fast Computation of Data Correlation using BDDs, Design Automation and Test in Europe Conference, DATE-2003, pp , March P. Kalla, M. Ciesielski, E. Boutillon, E. Martin, High-Level Design Verification Using Taylor Expansion Diagrams: First Results, IEEE Intl. High Level Design Validation and Test Workshop, HLDVT-02, pp , Oct M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification, Design Automation and Test Conference, DATE-2002, pp , March M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, Taylor Expansion Diagrams: A New Representation for RTL Verification, IEEE Intl. High Level Design Validation and Test Workshop (HLDVT 01), pp , Nov Z. Zeng, M. Ciesielski, B. Rouzeyre, Functional Test Generation using Constraint Logic Programming, in Proc. IFIP VLSI-SOC Conference, Dec P. Kalla, Z. Zeng, M. Ciesielski, Symbolic Algebraic Multi-Terminal Binary Decision Diagrams with Applications to RTL Verification, Proc. Intl. Workshop on Logic Synthesis, pp , June Z. Zeng, P. Kalla, M. Ciesielski, LPSAT: A Unified Approach to RTL-Satisfiability, Design and Test in Europe, DATE-2001, (Best Paper Award candidate) pp , March S. Askar, M. Ciesielski, Final Layout Generation for Custom Datapaths, XV Conference on Design of Circuits and Integrated Systems, DCIS 2000, pp , C. Yang, M. Ciesielski, BDS: A BDD-Based Logic Optimization System, Proc. ACM/IEEE Design Automation Conference, DAC-2000, pp , June P. Kalla, Z. Zeng, M. Ciesielski, C. Huang, BDD-based Satisfiability Infrastructure using the Unate Recursive Paradigm, Proc. Design, Automation and Test in Europe Conference, DATE-2000, pp , March C. Yang, M. Ciesielski, Synthesis for mixed CMOS/PTL Logic, Poster, presented at Design, Automation and Test in Europe Conference, DATE C. Yang, M. Ciesielski, BDD Decomposition for Efficient Logic Synthesis, Proc Intl. Conference on Computer Design, ICCD 99, pp , Oct S. Askar, M. Ciesielski, Analytical Approach to Custom Datapath Design, Intl. Conference on Computer-Aided Design, ICCAD 99, pp , Nov C. Yang, M. Ciesielski, BDD Decomposition for Efficient Logic Synthesis, Intl. Workshop on Logic Synthesis, May C. Yang, M. Ciesielski, Synthesis for mixed CMOS/PTL Logic: Preliminary Results, Intl. Workshop on Logic Synthesis, May

9 26. D. Vahia, M. Ciesielski Transistor Level Placement for Full Custom Datapath Cell Design, International Symposium on Physical Design, ISPD-99, pp , P. Kalla, M. Ciesielski, Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence, Design, Automation and Test in Europe, DATE-99, pp , B. Iyer, M. Ciesielski, Reencoding for Cycle-Time Minimization under Fixed Encoding Length, Proc. of IEEE Intl. Conference on Computer Aided Design, ICCAD 98, pp , Nov P. Kalla, M. Ciesielski, A Comprehensive Approach to Partial Scan Problem using Implicit State Enumeration, Proc. International Test Conference, ITC 98, pp , I. Chlamtac, M. Ciesielski, A. Fumagalli, C. Ruszczyk, G. Wedzinga, CATO: A CAD tool for intelligent design of optical networks and interconnects, SPIE Conference, Dallas, Nov I. Chlamtac, M. Ciesielski, A. Fumagalli, C. Ruszczyk, G. Wedzinga, Intelligent Simulation for Computer-Aided Design of Optical Networks, Proc. IFIP Working Conference on Optical Network Design and Modelling, Vienna, February 24-25, S.K. Bommu, M. Ciesielski, N. O Neill, P. Kalla, Retiming-Based Factorization for Multi-level Synthesis Proc. International Workshop on Logic Synthesis, May 18-21, P. Kalla, M. Ciesielski, Testability of Circuits with Multi-cycle False Paths, Proc. 15th IEEE VLSI Test Symposium, pp , April, B. Iyer, M. Ciesielski, Metamorphosis: State Assignment by Retiming and Re-encoding, Proc. Intl. Conf. on Computer-Aided Design, ICCAD 96, pp , S.K. Bommu, M. Ciesielski, Sequential Logic Optimization with Implicit Retiming, 1996 Korean ASIC Design Workshop, pp , July T.S. Kim, W. Burleson, M. Ciesielski, Constrained Timing Synthesis and Delay Insertion with Application to Wave-pipelining, Proceedings of TAU 95, 1995 ACM International Workshop on Timing Issues, Nov Z. Hasan, M. Ciesielski, Elimination of Multi-Cycle False Paths by State Encoding, Proc. of European Design and Test Conference, Paris, 1995, pp W. Burleson, M. Ciesielski, W. Cotten and F. Klass, Is Wavepipelining Practical, A forum session, Proc. of the 1994 International Symposium on Circuits and Systems, London 1994, pp Z. Hasan, M. Ciesielski, On Multi-Cycle False Paths in High-level and Logic Synthesis, Notes of IFIP International Workshop on Logic and Architecture Synthesis, Grenoble, France, Dec T-S. Kim, W. Burleson, M. Ciesielski, Delay buffer insertion for Wave-pipelined Circuits, Notes of IFIP International Workshop on Logic and Architecture Synthesis, Grenoble, France, Dec T-S. Kim, W. Burleson, M. Ciesielski, Logic Restructuring for Wave-Pipelined Circuits, Proc. International Workshop on Logic Synthesis, Lake Tahoe, CA, May 1993, pp. 4b Z. Hasan and M. Ciesielski, Functional Verification and Simulation of FSM Networks, Proc. 11th IEEE VLSI Test Symposium, pp , M. Yajnik and M. Ciesielski, Finite State Machine Decomposition Using Multiway Partitioning, Proc IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp , Oct J.J. Shen, Z. Hasan, and M. Ciesielski, State Assignment for General FSM Networks, Proc. European Design Automation Conference, EDAC-92, pp , March M. Ciesielski, J.J. Shen, and M. Davio, A Unified Approach to Input-Output Encoding for FSM State Assignment, Proc. 28th Design Automation Conference, pp ,

10 46. D. Joy and M. Ciesielski, Placement for Clock Period Minimization with Multiple Wave Propagation, Proc. 28th Design Automation Conference, pp , Z. Hasan, D. Harrison, and M. Ciesielski, Fast Partitioning Method for PLA-based Architectures, Proc. 4th International ASIC Conference and Exhibit, pp , Sept D. Joy and M. Ciesielski, Clock Tree Design for Period Minimization in Standard Cell Layout, Proc. International Workshop on Layout Synthesis, MCNC, May S. Yang and M. Ciesielski, On the Relationship Between Input Encoding and Logic Minimization, Proc. 23rd Hawaii International Conference on System Sciences, pp , Jan S. Yang and M. Ciesielski, PLA Decomposition with Generalized Decoders, IEEE International Conference on Computer-Aided Design, Digest of Technical Papers, pp , Nov M. Ciesielski, S. Yang and M.Perkowski, Multiple-Valued Boolean Minimization Based on Graph Coloring, Proc. International Conference on Computer Design, pp , Oct M. Ciesielski, VLSI Logic Synthesis: A Tutorial, invited tutorial, 1989 International Symposium on Circuits and Systems, Portland, OR, May M. Perkowski, M. Ciesielski, et al., Integration of Logic Synthesis and High Level Synthesis into the DIADES Design Automation System, Proc. IEEE International Symposium on Circuits and Systems, pp , May S. Yang and M. Ciesielski, A Generalized PLA Decomposition with Programmable Encoders, Proc. International Workshop on Logic Synthesis, MCNC, May M. Ciesielski, Performance-Oriented Layer Assignment, Proceedings IEEE International Conference on Computer Design, pp , M. Ciesielski, A New Approach to Routing in Irregular Channels for the Silc Silicon Compiler, Proc. IEEE International Conference on Computer-Aided Design, 1984, Digest of Technical Papers, pp J. Blank, J. Fox, T. Blackman, M. Ciesielski, L. Markov, The Silc Silicon Compiler, Profile, GTE Laboratories, No. 3, September 1984, pp M. Ciesielski, E. Kinnen, Digraph Relaxation for CAD Layout of Cell Based Integrated Circuits, Computer Science and Computer Engineering Research Review, University of Rochester, 1983, pp M.Ciesielski, E. Kinnen, Digraph Relaxation Technique for Placement Modification, Proc. IEEE International Symposium on Circuits and Systems, 1983, pp M. Ciesielski, E. Kinnen, An Analytical Method for Compacting Routing Area in Integrated Circuits, Proc. 19th Design Automation Conference, 1982, pp M. Ciesielski, E. Kinnen, Optimum Layer Assignment for Routing in IC s and PCB s, Proc. 18th Design Automation Conference, 1981, pp M. Ciesielski at al., Layout Design System for High Power Hybrid Electronic Circuits, Proc. 25th Anniversary of Electrical Engineering Department Conference, Technical University of Warsaw, November 1977 (in Polish). 10