Product Specification for SD Memory Card / MultiMediaCard PC Card Adapter

Transcription

1 PC Card Adapter Rev Date of issue: June 28th, 2001 Mitsubishi Plastics, Inc. Electronics & High Performance Materials Division

2 Matters to be considered upon using this specification : 1. When and if any problem arises between a third party as a result of using the product of our Company, we shall not be liable to any of those other than the ones the construction or manufacturing process of our products are directly involved. 2. The specification, material used and construction may be changed without prior notice. When you use the product, please obtain the latest technical information and confirm the content. In the event that any damage occurs to the equipment provided in this specification as a result of omission of confirming the technical information, our Company shall not be liable for the damages. 3. Our Company shall not be liable for any damage arising from the erroneous or inappropriate use including the deviation from the cautions listed below. The products listed in this technical information have been designed and manufactured with the assumption that they will be used for OA equipment, instrument, machine tools, AV and household appliances, and communication equipment (other than trunk line) for general use. Therefore, if you wish to use our products in conjunction with the equipment which require high reliability and safety such as for the control of large computer or transportation equipment such as aircraft, train, etc. it is recommended to design them incorporating fail-safe or redundant feature in consideration of required reliability and safety. Please refrain from using for the equipment, which require extremely high reliability such as aerospace equipment, communication (trunk line), atomic power controller and medical equipment (directly related to human life). If there is a possibility of damage to human life or body of properties, please contact with us in advance. 4. Please keep in mind that our Company shall not be responsible for the damages and/or incidental loss of profit caused by the loss of data caused by the functional deficiency or repair. It is suggested to make sure that the important data should be filed with other recording media. 5. As to the applicability of the strategic products under Foreign Exchange and Foreign Trade Control Law of the products listed in this information, please contact us each time. 6. If you have any question regarding this information, please contact us. i

3 Revision record: Revision Date Revised items First release Product Specification for ii

4 1. OUTLINE OF PRODUCT PRODUCT NAME CHARACTERISTICS REFERENCE INTERFACE SPECIFICATION PHYSICAL SPECIFICATION ELECTRICAL SPECIFICATION PC CARD ATA/TRUE IDE INTERFACE TERMINAL ASSIGNMENT INTERFACE TIMING INTERFACE TIMING ATTRIBUTE MEMORY READ OPERATION ATTRIBUTE MEMORY WRITE OPERATION COMMON MEMORY READ OPERATION COMMON MEMORY WRITE OPERATION I/O INPUT TIMING I/O OUTPUT TIMING TRUE IDE MODE I/O READ TIMING TRUE IDE MODE I/O WRITE TIMING CONSTITUTION OF CARD ATTRIBUTE MEMORY FEATURE CONFIGURATION OPTION REGISTER CARD CONFIGURATION STATUS REGISTER PIN REPLACEMENT REGISTER SOCKET COPY REGISTER I/O TRANSFER FEATURE COMMON MEMORY TRANSFER FEATURE COMMON MEMORY FEATURE TRUE IDE MODE TRANSFER FEATURE TRUE IDE MODE I.O FEATURE ATA REGISTER ERROR REGISTER (ADDRESS 1F1{171}; OFFSET 1,0DH READ ONLY) FEATURE REGISTER (ADDRESS 1F1{171}; OFFSET 1, 0DH WRITE ONLY) SECTOR COUNT REGISTER (ADDRESS 1F2{172}; OFFSET 2) SECTOR NUMBER REGISTER (ADDRESS 1F3{173}; OFFSET 3) CYLINDER LOW REGISTER (ADDRESS 1F4{174}; OFFSET 4) CYLINDER HIGH REGISTER (ADDRESS 153{175}; OFFSET 5) DRIVE HEAD REGISTER (ADDRESS 1F6{176}; OFFSET 6)...33 iii

5 STATUS REGISTER (ADDRESS 1F7{177}; OFFSET 7) ALTERNATE STATUS REGISTER (ADDRESS 3F6{376}; OFFSET E) DEVICE CONTROL REGISTER (ADDRESS 3F6{376}; OFFSET E) COMMAND REGISTER ATA COMMAND CHECK POWER MODE ( 98H, E5H) EXECUTE DRIVE DIAGNOSTIC ( 90H ) ERASE SECTOR(S) (C0H) FORMAT TRACK ( 50H ) IDENTIFY DRIVE ( ECH ) IDLE ( 97H, E3H ) IDLE IMMEDIATE ( 95H, E1H ) INITIALIZE DRIVE PARAMETERS ( 91H ) READ BUFFER ( E4H ) READ MULTIPLE(C4H) READ LONG SECTOR(22H OR 23H) READ SECTOR(S) ( 20H, 21H ) READ VERIFY SECTOR(S) ( 40H, 41H ) RECALIBRATE ( 1XH ) REQUEST SENSE (03H) SEEK ( 7XH ) SET FEATURES ( EFH ) SET MULTIPLE MODE ( C6H) SET SLEEP MODE (99H OR E6H) STANDBY ( 96H, E2H) STANDBY IMMEDIATE ( 94H, E0H ) TRANSLATE SECTOR (87H) WEAR LEVEL (F5H) WRITE BUFFER ( E8H ) WRITE LONG SECTOR (32H, 33H ) WRITE MULTIPLE COMMAND (C5H) WRITE MULTIPLE WITHOUT ERASE (CDH) WRITE SECTOR(S) (30H, 31H ) WRITE SECTOR(S) WITHOUT ERASE (38H ) WRITE VERIFY SECTOR(S) (3CH ) ARRANGEMENT OF ERRORS CIS INFORMATION LABEL INFORMATION iv

6 7. HANDLING, TRANSPORTATION AND STORAGE REVISION OF THIS TECHNICAL INFORMATION v

7 1. Outline of Product By using this product, it is possible to operate SD Memory Card and MultiMediaCard just like ATA Standard conformity PC Card. This product may be used by any system supporting PC Card Type II or Type III slot. This document is described based on using SD memory card by SDA specification or MultiMediaCard by MMCA Specification. 1.1 Product Name Product Name:SD Memory Card/MultiMediaCard compatible PC Card Adapter. Type: SD0000CMNA 1.2. Characteristics Conforming PC card ATA Specification Operated on 3.3V / 5V Support Standby Mode 1.3. Reference PC Card Standard Release 7 February 1999 PCMCIA/JEIDA Volume 2 Electrical Specification Volume 3 Physical Specification Volume 8 PC Card ATA Specification Volume 10 Guidelines CompactFlash Specification Revision 1.4 SD Memory Card Specification Part 1 PHYSICAL LAYER SPECIFICATION Ver.1.0 MultiMediaCard System Specification Ver. 2.2 AT Attachment Interface for Disk Drives ANSI X Interface specification 2.1. Physical specification The socket configuration is such that 34 pins of 1.27 mm width in two rows. Please refer to Fig. 2-1 for outside dimensions and shape. 1

8 2 X 2. 50MAX /- 0.2 Pin# /- 0.1 Pin#1 2 X / Pin#6 Pin# picth x 33 = / Fig. 2-1 External dimension (Unit: mm) 2

9 2.2. Electrical specification Absolute Maximum Rating Item Symbol Rating Unit Power voltage Vcc -0.5 ~ 6.5 V Input voltage Vin -0.5 ~ Vcc V Operation Topr degree C 0 ~ 70 temp. Storage temp. Tstg -20 ~ 70 degree C Product Specification for Recommended Operating Conditions Item Symbol Min. Typ. Max. Unit Vcc(3.3) Power voltage V Vcc(5.0) Level H input Voltage Level L input Voltage Vih 2.4 V Vil 0.8 V Operating conditions Item Min. Max. Unit Operating temp degree C Storage temp degree C Humidity (Note) 5 95 %RH Vibration 15 G Shock 50 G Note : No condensation DC Characteristics Host Interface (Ta = 0 ~ 65 degree C) Item Symbol Condition Min. Typ. Max. Unit Level H output Ioh = Voh Voltage 400uA 2.6 V Level L output Iol = Vol Voltage 2.1mA 0.2Vcc V Read current 1 Icc1 50 ma Write current 1 Icc2 55 ma Standby current 1 Icc3 9 ma Note 1. These value are not included card current. SD Card / MultiMediaCard Interface (Ta = 0~65 degree C) Item Symbol Condition Min. Typ. Max. Unit Power Source Vdd 3.2 V Level H Output Voltage Vohc 2.4 V Level L Output Voltage Volc 0.4 V 3

10 System Performance Item Symbol Condition Min. Typ. Max. Unit Sleep to Write 1 Ms Sleep to Read Start Up Time Reset to Ready 700 Ms Power up to Ready Active to Sleep TBD ms delay Reset Pulse Width RSTwt 200 ns Reliability Item MTBF Period 1,000,000 hours Weight 30g 2.3. PC Card ATA/True IDE Interface Terminal Assignment The Adapter connected to the Host through 68 pin connector, which conform to PC Card Standard. Signals and Pin assignments are indicated in table 2-3, and meaning of signals is indicated in table 2-4. Signal names with mark # after the name are Low Active. Follows are type and name of terminals. Symbols Name Meaning I Input Input O Output Output I/O Input/Output Input/Output bi-direction DC DC Power, Ground N/C Not Connected Not Connected (Open) 4

11 Table 2-3 PC Card Interface Pin Assignment and Pin type PC Card Memory Mode PC Card I/O Mode True IDE Mode Pin Number Signal Name Pin Type Pin Number Signal Name Pin Type Pin Number Signal Name Pin Type 1 GND DC 1 GND DC 1 GND DC 2 D3 I/O 2 D3 I/O 2 D3 I/O 3 D4 I/O 3 D4 I/O 3 D4 I/O 4 D5 I/O 4 D5 I/O 4 D5 I/O 5 D6 I/O 5 D6 I/O 5 D6 I/O 6 D7 I/O 6 D7 I/O 6 D7 I/O 7 CE1# I 7 CE1# I 7 CS0# I 8 A10 I 8 A10 I 8 A10 2 I 9 OE# I 9 OE# I 9 ATASEL# I 10 N/C - 10 N/C - 10 N/C - 11 A9 I 11 A9 I 11 A9 2 I 12 A8 I 12 A8 I 12 A8 2 I 13 N/C - 13 N/C - 13 N/C - 14 N/C - 14 N/C - 14 N/C - 15 WE# I 15 WE# I 15 WE# 3 I 16 READY O 16 IREQ# O 16 INTRQ O 17 Vcc DC 17 Vcc DC 17 Vcc DC 18 N/C - 18 N/C - 18 N/C - 19 N/C - 19 N/C - 19 N/C - 20 N/C - 20 N/C - 20 N/C - 21 N/C - 21 N/C - 21 N/C - 22 A7 I 22 A7 I 22 A7 2 I 23 A6 I 23 A6 I 23 A6 2 I 24 A5 I 24 A5 I 24 A5 2 I 25 A4 I 25 A4 I 25 A4 2 I 26 A3 I 26 A3 I 26 A3 2 I 27 A2 I 27 A2 I 27 A2 I 28 A1 I 28 A1 I 28 A1 I 29 A0 I 29 A0 I 29 A0 I 30 D0 I/O 30 D0 I/O 30 D0 I/O 31 D1 I/O 31 D1 I/O 31 D1 I/O 32 D2 I/O 32 D2 I/O 32 D2 I/O 33 WP O 33 IOIS16# O 33 IOCS16# O 34 GND DC 34 GND DC 34 GND DC 5

12 PC Card Memory Mode PC Card I/O Mode True IDE Mode Pin Number Signal Name Pin Type Pin Number Signal Name Pin Type Pin Number Signal Name Pin Type 35 GND DC 35 GND DC 35 GND DC 36 CD1# O 36 CD1# O 36 CD1# O 37 D11 1 I/O 37 D11 1 I/O 37 D11 1 I/O 38 D12 1 I/O 38 D12 1 I/O 38 D12 1 I/O 39 D13 1 I/O 39 D13 1 I/O 39 D13 1 I/O 40 D14 1 I/O 40 D14 1 I/O 40 D14 1 I/O 41 D15 1 I/O 41 D15 1 I/O 41 D15 1 I/O 42 CE2# 1 I 42 CE2# 1 I 42 CS1# 1 I 43 VS1# O 43 VS1# O 43 VS1# O 44 RFU - 44 IORD# I 44 IORD# I 45 RFU - 45 IOWR# I 45 IOWR# I 46 N/C - 46 N/C - 46 N/C - 47 N/C - 47 N/C - 47 N/C - 48 N/C - 48 N/C - 48 N/C - 49 N/C - 49 N/C - 49 N/C - 50 N/C - 50 N/C - 50 N/C - 51 Vcc DC 51 Vcc DC 51 Vcc DC 52 N/C - 52 N/C - 52 N/C - 53 N/C - 53 N/C - 53 N/C - 54 N/C - 54 N/C - 54 N/C - 55 N/C - 55 N/C - 55 N/C - 56 N/C - 56 N/C - 56 CSEL# I 57 VS2# O 57 VS2# O 57 VS2# O 58 RESET I 58 RESET I 58 RESET# I 59 WAIT# O 59 WAIT# O 59 IORDY O 60 RFU - 60 INPACK# O 60 N/C - 61 REG# I 61 REG# I 61 REG# 3 I 62 BVD2 O 62 SPKR# O 62 DASP# O 63 BVD1 O 63 STSCHG O 63 PDIAG# O # 64 D8 1 I/O 64 D8 1 I/O 64 D8 1 I/O 65 D9 1 I/O 65 D9 1 I/O 65 D9 1 I/O 66 D10 1 I/O 66 D10 1 I/O 66 D10 1 I/O 67 CD2# O 67 CD2# O 67 CD2# O 68 GND DC 68 GND DC 68 GND DC Note 1 These signals are used for 16 bit access only, not for 8 bit access. To save the power consumption, please keep these signals as open. Note 2 Must be connected to Ground at the Host. Note 3 Must be connected to Power at the Host. 6

13 Table 2-4 Name of Signal A10 - A0 (PC Card Memory Mode) A10 - A0 (PC Card I/O Mode) A2 - A0 (True IDE Mode) BVD1 (PC Card Memory Mode) STSCHG# (PC Card I/O Mode) PDIAG# (True IDE Mode) BVD2 (PC Card Memory Mode) SPKR# (PC Card I/O Mode) DASP# (True IDE Mode) CD1#, CD2# (PC Card Memory Mode) CD1#, CD2# (PC Card I/O Mode) CD1#, CD2# (True IDE Mode) CE1#, CE2# (PC Card Memory Mode) CE1#, CE2# (PC Card I/O Mode) CS0#, CS1# (True IDE Mode) Explanation of signals Att rib ute I Terminal number 8, 11, 12, 22, 23, 24, 25, 26, 27, , 28, 29 I/O 63 I/O 62 O 36, 67 I 7, 42 Details By combining this signal with the state of REG#, it is possible to select the following address: I/O port address registers Memory mapped port address registers CIS Card configuration and status registers At the True IDE mode, A2 A0 is used for the selection of task file registers. Other address lines should be connected to GND. Fix at high as built-in battery is not needed. Send RDY signal to Host and indicate the change of Write Protect status. The operation of this signal (Enable/Disable) shall be done with Card Configuration Status Register. Used as Pass Diagnostic signal between Master/Slave. Fix at High as built-in battery is not needed. Fix at High as audio function is not supported. Disk active/slave present signal of Handshake protocol of Master and Slave. Connected with GND in the adapter and used for checking the condition of insertion by Host. Used for selection of adapter or the selection of access method (word or byte). By asserting CE2#, the odd byte of word information becomes accessible and by means of using CE1# in combination of A0 and CE2#, each of even byte and odd byte of word information become accessible. Likewise, by combining A0, CE1# and CE2#, it is also possible to access each of odd and even byte information on 8 bit system with only D0-D7. CS1# is used for the selection of Alternate Status Register and Device Control Register, and CS0# is used for the selection of other task file register. 7

14 Name of Signal N/C (PC Card Memory Mode) N/C (PC Card I/O Mode) CSEL# (True IDE Mode) D15 D0 (PC Card Memory Mode) D15 D0 (PC Card I/O Mode) D15 D0 (True IDE Mode) GND (PC Card Memory Mode) GND (PC Card I/O Mode) GND (True IDE Mode) RFU (PC Card Memory Mode) INPACK# (PC Card I/O Mode) N/C (True IDE Mode) RFU (PC Card Memory Mode) IORD# (PC Card I/O Mode) IORD# (True IDE Mode) RFU (PC Card Memory Mode) IOWR# (PC Card I/O Mode) IOWR# (True IDE Mode) OE# (PC Card Memory Mode) OE# (PC Card I/O Mode) ATASEL# (True IDE Mode) Att rib ute Terminal number I 56 I/O D C 41, 40, 39, 38, 37, 66, 65, 64, 6, 5, 4, 3, 2, 32, 31, 30, 1, 34, 35, 68 O 60 I 44 Details Not used at PC Card Memory Mode. Not used at PC Card I/O Mode. Used for setting of Drive 0 / 1. When this terminal is connected with GND, function as Drive 0 (Master). When this terminal is OPEN, function as Drive 1 (Slave). Data, status and commands are exchange between Host and Adapter with these signals. D0 corresponds to the LSB of even byte composing word and the D8 corresponds to LSB of odd byte. Access to Task Register is always performed with byte access using D7 - D0, and access to Data Register is always performed with word access using D15 - D0 Ground Not used at PC Card Memory Mode. Used for responding to I/O cycle read. Host uses this signal for recognizing the timing of receipt of data (preparation of data buffer between CPU and Adapter). Not used at True IDE mode. Not used at PC Card Memory Mode. Used as clock when data on data-bus is taken from adapter. Not used at PC Card Memory Mode I 45 Used as clock when data on data-bus is taken from Host. Clock is generated at the Negative to Positive (Trailing edge). I 9 Used as data read from the adapter. Used to read CIS, Card configuration and Status registers. This signal have to be connected with GND. 8

15 Name of signal READY (PC Card Memory Mode) IREQ# (PC Card I/O Mode) INTRQ (True IDE Mode) REG# (PC Card Memory Mode) REG# (PC Card I/O Mode) REG# (True IDE Mode) RESET (PC Card Memory Mode) RESET (PC Card I/O Mode) RESET# (True IDE Mode) Vcc (PC Card Memory Mode) Vcc (PC Card I/O Mode) Vcc (True IDE Mode) Attr ibut e Terminal number O 16 I 61 I 58 Details By setting this signal to High, Host is advised of the state of Ready and Busy by setting to Low. Host need to be installing a Pull-up resister in the socket. For the time from Reset/Power on to Ready, please refer to 2.2. System Performance If Power on/reset is indicated to Adapter, Adapter maintains this signal at Low (Busy) until Adapter finishes the task. During such time, any operation is not allowed. This signal is High if the following conditions are met:(kept as Disable). Reset signal is kept at high impedance or High Continuously from Power on. Adapter strobes this signal to Low when requested Pulse mode Interrupt and to Low when requested Level mode Interrupt. When Active High, becomes an interrupt signal to Host. Used for switching between Attribute memory and common memory. Common memory is selected when this signal is High and Attribute memory is selected when it is Low. While I/O address is valid, this signal must be Low. Not used at True IDE Mode. Host is able to command the execution of RESET to Adapter by making this to High. If this terminal keeps High or Open condition at the time of Power On, Adapter execute RESET. In addition, Host is able to instruct Adapter RESET by setting Soft Reset bit of Card Configuration Option Register 1. Active Hardware RESET from Host. DC 17, 51 Power source of +5V and +3.3V. 9

16 Name of Signal VS1#,VS2# (PC Card Memory Mode) VS1#, VS2# (PC Card I/O Mode) VS1#, VS2# (True IDE Mode) WAIT# (PC Card Memory Mode) WAIT# (PC Card I/O Mode) IORDY (True IDE Mode) WE# (PC Card Memory Mode) WE# (PC Card I/O Mode) WE# (True IDE Mode) WP (PC Card Memory Mode) IOIS16# (PC Card I/O Mode) IOCS16# (True IDE Mode) Att rib ut e O Terminal number 43, 57 O 59 I 15 O 33 Details Voltage detection signal VS1# is connected to GND and CIS of Adapter can be read at 3.3V. VS2# is open. Used to advise Host that the executing cycle ( Memory, I/O) is being delayed. Used to inform from the Adapter to Host that data is ready. Used as the clock to write into Data Register. Used as the clock to write into Card configuration register. This signal have to connected to Vcc Becomes High in case write protect switch of SD card is ON. In case this signal is Low, it is indicated that Host is capable of being accessed only 16 bit access or odd number access through specified port. This signal should be kept Low when word is being transmitted. 10

17 2.4. Interface Timing There are two timing sequences in the PC card interface, Direct Mapped I/O transmission and memory access. For details of these sequences, please refer to PC Card Standard Release 7. This product conforms to said standard Attribute Memory Read Operation The Read Access Time of attribute memory is specified as 300ns. For detail of timing, please refer to the following table. Attribute Memory Read Timing Items Symbol IEEE Min. Max. Unit symbol Read Cycle Time tc( R ) tavav 300 ns Address Access Time ta( A ) tavqv 300 ns Card Enable Access Time ta(ce) telqv 300 ns Output Enable Access Time ta(oe) tglqv 150 ns Output Disable Time from CE tdis(ce) tehqz 100 ns Output Disable Time from OE tdis(oe) tghqz 100 ns Address Setup Time tsu( A ) tavwl 30 ns Output Enable Time from CE ten(ce) telqnz 5 ns Output Enable Time from OE ten(oe) tglqnz 5 ns Data Valid from Address Change tv ( A ) taxqx 0 ns tc(r) An REG# ta(a) CE# tsu(a) ta(ce) tv(a) OE# Dout ten(ce) ten(oe) ta(oe) Valid tdis(ce) tdis(oe) Note : Dout means the data given to Host from Adapter. CE# signal or OE# signal and WE# signal should not be set during the continued cycle operation. 11

18 Attribute Memory Write Operation Write access time of Attribute Memory is specified as 250 nsec. For the details of timing, please refer to the following table: Note: For this product writing of CIS memory from the Host is not allowed. Only writing to Configuration Option Register is possible. Table: Attribute Memory Write Timing Items Symbols IEEE Min. Max. Unit symbol Write Cycle Time tc( W ) tavav 250 ns Write Pulse Width tw(we) twlwh 150 ns Address Setup Time tsu( A ) tavwl 30 ns Write Recovery Time trec(we) twmax 30 ns Data Setup Time for WE tsu(d-weh) tdvwh 80 ns Data Hold Time th ( D ) twmdx 30 ns tc(w) REG# An tsu(a) trec(we) WE# CE# tsu(d-weh) tw(we) th(d) OE# Din Din Valid Din indicates the data given to adapter from the Host. 12

19 Common Memory Read Operation Table: Common Memory Read Timing Items Symbol IEEE Min. Max. Unit Symbol Output Enable Time ta(oe) tglqv 125 ns Output Disable Time from OE tdis(oe) tghqz 100 ns Address Setup Time tsu(a) tavgl 30 ns Address Hold Time th(a) tghax 20 ns CE Setup before OE tsu(ce) telgl 0 ns CE Hold following OE th(ce) tgheh 20 ns Wait Delay Falling OE tv(wt-oe) tglwtv 35 ns Data Setup for Wait Release tv(wt) tqvwth 0 ns Wait Width Time (Default Speed) tw(wt) twtlwth 350 ns An tsu(a) th(a) REG# CE# tsu(ce) ta(oe) th(ce) OE# tw(wt) WAIT# Dout tv(wt-oe) tv(wt) Valid tdis(oe) Note: -The maximum load of WAIT is 1 LSTTL. total load is 50pF. Dout indicates the data given to Host from adapter. If the interval of OE# cycle exceeds Wait Width, WAIT# signal may be neglected. The maximum wait width (of minimum speed mode) can be determined from CIS. 13

20 Common Memory Write Operation Table: Common Memory write Timing Items Symbols IEEE Min. Max. Unit Symbol Data Setup before WE tsu(d-weh) tdvwh 80 ns Data Hold following WE th(d) tlwmdx 30 ns WE Pulse Width tw(we) twlwh 150 ns Address Setup Time tsu(a) tavwl 30 ns CE Setup before WE tsu(ce) telwl 0 ns Write Recovery Time trec(we) twmax 30 ns CE Hold following WE th(ce) tgheh 20 ns Wait Delay Falling from WE tv(wt-we) twlwtv 35 ns WE High from Wait Release tv(wt) twthwh 0 ns Wait Width Time (Default Speed) tw(wt) twtlwth 350 ns An tsu(a) trec(we) REG# tsu(ce) th(ce) CE# tw(we) WE# tw(wt) tv(wt) WAIT# Dout tv(wt-we) tsu(d-weh) th(d) Note : The maximum load of WAIT# is 1 LSTTL. total load is 50pF. Dout indicates the data given to Host from adapter. In case the interval of OE# cycle exceeds the Wait Width. WAIT# signal may be neglected. The maximum Wait Width (of minimum speed) can be determined from CIS. 14

21 I/O Input Timing Table: I/O Input Timing Items Symbol IEEE Min. Max. Unit symbol Data Delay after IORD td(iord) tlglqv 100 ns Data Hold following IORD th(iord) tlghqx 0 ns IORD Width Time tw(iord) tlgligh 165 ns Address Setup before IORD tsua(iord) tavigl 70 ns Address Hold following IORD tha(iord) tlghax 20 ns CE Setup before IORD tsuce(iord) teligl 5 ns CE Hold following IORD thce(iord) tlgheh 20 ns REG Setup before IORD tsureg(iord) trgligl 5 ns REG Hold following IORD threg(iord) tlghrgh 0 ns INPACK delay Falling from IORD tdfinpack(iord) tlglial 0 45 ns INPACK delay Rising from IORD tdrinpack(iord) tlgliah 45 ns IOIS16 Delay Falling from Address tdfiois16(adr) tavisl 35 ns IOIS16 Delay Rising from Address tdriois16(adr) tavish 35 ns Wait Delay Falling from IORD tdwt(iord) tlglwtl 35 ns Data Delay from Wait Rising td(wt) twthqv 0 ns Wait Width Time (Default Speed) tw(wt) twtlwth 350 ns An REG# tsua(iord) tsureg(iord) tha(iord) threg(iord) CE# tsuce(iord) thce(iord) IORD# INPACK# tw(iord) tdfinpack(iord) td(iord) tdrinpack(iord) tdriois16(adr) IOIS16# tdfiois16(adr) tw(wt) WAIT# tdwt(iord) th(iord) Dout Valid 15

22 Note: The maximum load of WAIT#, INPACK# and IOIS16# are 1 LSTTL and total load is 50pF. The minimum time from WAIT# High to IORD# High is 0ns but it is necessary to fulfill the minimum IORD# width. Dout indicates the data given to Host from adapter I/O Output Timing Table I/O write timing Items Symbol IEEE Min. Max. Unit Symbol Data Setup before IOWR tsu(iowr) tdviwh 60 ns Data Hold following IOWR th(iowr) tlwmdx 30 ns IOWR Width Time tw(iowr) ttwliwh 165 ns Address Setup before IOWR tsua(iowr) taviwl 70 ns Address Hold following IOWR tha(iowr) tlwhax 20 ns CE Setup before IOWR tsuce(iowr) teliwl 5 ns CE Hold following IOWR thce(iowr) tlwheh 20 ns REG Setup before IOWR tsureg(iowr) trgliwl 5 ns REG Hold following IOWR threg(iowr) tlwhrgh 0 ns IOIS16 Delay Falling from Address tdfiois16(adr) tavisl 35 ns IOIS16 Delay Rising from Address tdriois16(adr) tavish 35 ns Wait Delay Falling from IOWR tdwt(iowr) tlwlwtl 35 ns IOWR high from Wait High tdriowr(wt) twtjiwh 0 ns Wait Width Time (Default Speed) (Set Feature Speed <68mA) tw(wt) twtlwth ns An REG# tsua(iowr) tsureg(iowr) tha(iowr) threg(iowr) CE# tsuce(iowr) tw(iowr) thce(iowr) IOWR# tdfiois16(adr) tdriois16(adr) IOIS16# tsu(iowr) tw(wt) WAIT# Din tdwt(iowr) tdriowr(wt) th(iowr) 16

23 Note: The maximum load of WAIT#, INPACK# and IOIS16# are 1 LSTTL and the total load is 50pF. The maximum time from WAIT# High to IOWR# High is 0ns minimum, but it is necessary to fulfill the minimum IOWR# width. Din indicates the data given to adapter from Host. 17

24 True IDE Mode I/O Read Timing Table True IDE Mode I/O Read Timing Items Symbol IEEE Min. Max. Unit Symbol Data delay after IORD td(iord) tlglqv 100 ns Data Hold following IORD th(iord) tlghqx 0 ns IORD Width Time tw(iord) tlgligh 165 ns Address Setup before IORD TsuA(IORD) tavigl 70 ns Address Hold following IORD tha(iord) tlghax 20 ns CE Setup before IORD tsuce(iord) teligl 5 ns CE Hold following IORD thce(iord) tlgheh 20 ns IOIS16 Delay Falling from Address tdfiois16(adr) tavisl 35 ns IOIS16 Delay Rising from Address tdriois16(adr) tavish 35 ns An tsua(iord) tha(iord) CE# tsuce(iord) tw(iord) thce(iord) IORD# IOIS16# tdfiois16(adr) Dout td(iord) Valid tdriois16(adr) th(iord) Note: The maximum load of IOIS16# is 1 LSTTL and the total load is 50pF. The maximum time from WAIT# High to IORD# High is 0ns minimum, but the minimum IORD# width has to be fulfilled. Din indicates the data given to adapter from Host. 18

25 True IDE Mode I/O Write Timing Table True IDE Mode I/O Write Timing Items Symbols IEEE Min. Max. Unit Symbols Data setup before IOWR tsu(iowr) tdviwh 60 ns Data Hold following IOWR th(iowr) tlwhdx 30 ns IOWR Width Time tw(iowr) tlwliwh 165 ns Address Setup before IOWR tsua(iowr) taviwl 70 ns Address Hold following IOWR tha(iowr) tlwhax 20 ns CE Setup before IOWR tsuce(iowr) teliwl 5 ns CE Hold following IOWR thce(iowr) tlwheh 20 ns IOIS16 Delay Falling from Address tdfiois16(adr) tavisl 35 ns IOIS16 Delay Rising from Address tdriois16(adr) tavish 35 ns An tsua(iowr) tha(iowr) CE# tsuce(iowr) tw(iowr) thce(iowr) IOWR# tdriois16(adr) IOIS16# tdfiois16(adr) Dout tsu(iowr) Din Valid th(iowr) Note: The maximum load of IOIS16# is 1 LSTTL and total load is 50pF. The minimum time from WAIT# High to IOWR# High is 0ns, but the minimum IOWR# width has to be fulfilled. Dout indicates the data given to Host from adapter. 19

26 2.5. Constitution of Card This product is recognized by the information contained in CIS Card Information Structure. Table Selection of Register space and Memory space CE2# CE1# REG# OE# WE# A10 A9 A8-A4 A3 A2 A1 A0 Selected Space 1 1 x x X x x xx x x x x Standby x x 1 xx x x x 0 Configuration Registers Read x x xx x x x x Common Memory Read ( 8bit D7-D0 ) x x xx x x x x Common Memory Read ( 8bit D15-D8 ) x x xx x x x 0 Common Memory Read ( 16bit D15-D0 ) x x 1 xx x x x 0 Configuration Registers Write x x xx x x x x Common Memory Write ( 8bit D7-D0 ) x x xx x x x x Common Memory Write ( 8bit D15-D8 ) x x xx x x x 0 Common Memory Write ( 16bit D15-D0 ) x xx x x x 0 Card Information Structure Read xx x x x 0 Invalid Access (CIS Write) x x xx x x x 1 Invalid Access (Odd Attribute Read) x x xx x x x 1 Invalid Access (Odd Attribute Write) x x xx x x x x Invalid Access (Odd Attribute Read) x x xx x x x x Invalid Access (Odd Attribute Write) Table Selection of Configuration Register CE2# CE1# REG# OE# WE# A10 A9 A8-A4 A3 A2 A1 A0 Selected Register x Configuration Option Register Read x Configuration Option Register Write x Card Status Register Read x Card Status Register Write x Pin Replacement Register Read x Pin Replacement Register Write x Socket and Copy Register Read x Socket and Copy Register Write Note: Since these positions of future products may be changed, it is absolutely necessary to read the card setting register positions from CIS. Except the address of register for card setting, data can t be written to the Attribute Memory of adapter. All other address of Attribute Memory has been reserved. 20

27 2.5.1 Attribute Memory Feature Attribute Memory Feature is the space where discrimination information and setting information is stored. The unit of access is 8bit and only even number address can be accessed. Card setting register is also included in the Attribute Memory. Table Selection of Attribute Memory Function Mode REG# CE2# CE1# A9 A0 OE# WE# D15-D8 D7-D0 Standby Mode X H H X X X X High Z High Z Read Byte Access CIS ROM(8bits) Write Byte Access CIS ROM(8bits)(Invalid) Read Byte Access Configuration(8bits) Write Byte Access Configuration(8bits) Read Word Access CIS(16bits) Write Word Access CIS(16bits)(Invalid) Read Word Access Configuration(16bits) Write word Access Configuration(16bits) L H L L L L H High Z L H L L L H L High Z L H L H L L H High Z L H L H L H L L L L L X L H L L L L X H L L L L H X L H L L L H X H L Don t Care Not Valid Don t Care Not Valid Don t Care Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Even Byte Note: CE# signal or OE# signal and WE# signal should not be set during the continuous cycle operation Configuration Option Register (Address 200h in Attribute Memory) Configuration Option Register is used for card interface, address decoding or setting interruption. Also, it is used for effecting soft reset to adapter. Operation D7 D6 D5 D4 D3 D2 D1 D0 R/W SRESE T LevIREQ Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 SRESET Soft Reset. It is possible to set the product in Reset when set this bit to 1 and then return to 0 after the minimum reset width time has past. to set this bit to 1 means same as asserting RESET signal except SRESET bit will not be cleared. Once this bit has returned to 0, adapter will be set to the reset condition which same as after power up or after hardware reset 21

28 This bit can be set to 0 by power up or hardware reset. By using this reset, it will be recognized as hard reset by ATA command. Please refer soft reset on Device Control Register. LevIREQ This bit is set to 1 in case level Mode interrupt is selected, and set to 0 in case Pulse Mode is selected Also it will set to 0 after reset. Conf5-Conf0 It will set to 0 after executing Setting Index Reset. Operation mode is as follows. Table Card Configuration Conf5 Conf4 Conf3 Conf2 Conf1 Conf0 Disk Card Mode Memory Mapped I/O Mapped Any 16 byte system decoded boundary I/O Mapped, 1F0-1F7/3F6-3F I/O Mapped, / Card Configuration Status Register (Address 202h of Attribute Memory) Card Configuration Status Register is used for recording the information on the status of card. Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Change d SigChg Iois8 0 0 PwrDwn Int 0 Write 0 SigChg Iois8 0 0 PwrDwn 0 0 Changed This means CRdy and/or CWProt on Pin Replacement Register is set to 1. In case Changed bit is set, in case SigChg bit is set, and in case SigChg bit is set and adapter is set to I/O interface, STSCHG# pin (Pin No. 46) is set as Low. SigChg This bit is set or reset by Host, and make the status changing signal from status register enable or disable. Changed bit is effect setting of pin No. 46 which used for Changed Status signal. If status changing signal is not necessary, this bit have to set to 0. During the period that adapter is set to I/O mode, STSCHG# (Pin No. 46) signal is set to High Iois8 Adapter is set to 8 bit I/O mode, Host set this bit to 1. Adapter itself is always set to correspond both 8 bit I/O mode and 16 bit I/O mode, so this bit will be neglected. PwrDwn This bit indicates Host request adapter to set into Power save mode or 22

29 Active mode. In case bit is 1, adapter is in Power save mode, and when bit is 0 adapter is in Active mode. Once this bit is changed, Ready signal (Pin No. 37) becomes Busy, and then becomes Ready after received enough power. Adapter is automatically go into Power save mode when it is standby, and switched to Active mode when received command. Int This bit indicate inner status of interrupt requirement. This value can be used anytime without relationship of I/O interface setting. This signal is set to 1 when interrupt requirement will occur. In case interrupt is disabled by IEN# bit on Device Control Register, this bit is Pin Replacement Register (Address 204h in Attribute Memory) Pin Replacement Register is as follows. Operation D7 D6 D5 D4 D3 D2 D1 D0 Read 0 0 CRdy/-Bsy CWProt 1 1 Rdy/-Bsy RWProt Write 0 0 CRdy/-Bsy CWProt 0 0 MRdy/-Bsy MWProt CRdy/-Bsy In case status of CRdy/-Bsy bit will be changed, this bit is set to 1, and Host can write it also. CWProt In case the status of RWProt will be changed, this bit will set to 1, and Host can write it also. Rdy/-Bsy This bit is used to judge the inner status of Rdy/-Bsy signal. Rdy/-Bsy terminal is, in I/O mode, used for Interrupt Request, so it can use to determine status of Ready/Busy also. When writing, this bit will function as a mask when writing CRdy/-Bsy bit which correspond to Rdy/-Bsy. RWProt Since this adapter have no write protect function, this bit is set to 0 always. This bit will function as a mask when writing CWProt bit which correspond to RWProt. MRdy/-Bsy This bit function as a mask when writing CRdy/Bsy bit which correspond to MRdy/-Bsy. MWProt This bit function as a mask when writing CWProt bit, which correspond to MWProt. 23

30 Initial value Write by Host Final C Bit M Bit C Bit Comment 0 x 0 0 Unchanged 1 x 0 1 Unchanged X Cleared by Host X Set by Host Socket Copy Register (Address 206h of Attribute Memory) Socket Copy Register is used for recording supplemental setting information. This Register is set prior to the setting of Configuration Index Register. Operation D7 D6 D5 D4 D3 D2 D1 D0 Read Reserve d 0 0 Drive# Write Drive#(0) x x x x Reserved This bit is reserved for future standardization. Please set 0 to the software when writing this Register. Drive# If twin card setting is supported, this bit indicates the driver number. x This Adapter neglects the socket number I/O Transfer Feature I/O transfer between this Adapter can be done with both 8bit and 16bit. In case 16bit accessible port is addressed, this Adapter set IOIS16# signal and 16bit transfer will be done. In case IOIS16# will not be set, system side have to produce a pair of 8bit reference to access both even byte of word and odd byte of word. This Adapter can access to I/O address with both 8bit and 16bit. To response all address, IOIS16# is set on this Adapter. This Adapter can request to the Host to extend the length of input cycle by setting WAIT# signal at the beginning of cycle. Table I/O Function Function Mode REG# CE2# CE1# A0 IORD# IOWR# D15-D8 D7-D0 Standby Mode x H H x x x High Z High Z Byte Input Access (8bits) L L H H L L L H L L H H High Z High Z Even Byte Odd Byte Byte Output Access (8bits) L L H H L L L H H H L L Don t Care Don t Care Even Byte Odd Byte Word Input Access (16bits) L L L L L H Odd Byte Even Byte Word Output L L L L H L Odd Byte Even Byte 24

31 Access (16bits) I/O Read Inhibit H x x x L H Don t Care Don t Care I/O Write Inhibit H x x x H L High Z High Z High Byte Input Only L L H x L H Odd Byte High Z (8bits) High Byte Output Only (8bits) L L H x H L Odd Byte Don t Care 25

32 2.7. Common Memory Transfer Feature Common Memory Feature Common Memory transfer between this Adapter can be done with both 8bit and 16bit. By setting the WAIT# signal in the beginning of cycle, this Adapter can request to the Host to extend the memory read cycle, and memory write cycle. Table common Memory Feature Function Mode REG# CE2# CE1# A0 OE# WE# D15-D8 D7-D0 Standby Mode x H H x x x High Z High Z Byte Read Access L H L L L H High Z Even Byte (8bits) Byte Write Access (8bits) Word Read Access (16bits) Word Write Access (16bits) Odd Byte Read Only (8bits) Odd Byte Write Only (8bits) L L L H H H L L L H L H L H H H L L High Z Don t Care Don t Care Odd Byte Even Byte Odd Byte L L L x L H Odd Byte Even Byte L L L x H L Odd Byte Even Byte L L H x L H Odd Byte High Z L L H x H L Odd Byte Don t Care 26

33 2.8. True IDE Mode Transfer Feature True IDE Mode I.O Feature This Adapter can be set to perform operation in True IDE Mode. In order to set this Adapter in this mode, OE# input signal has to be set to GND at Host side. The setting or protocol of PC Card can not be used in True IDE Mode and only the I/O operation to Task file and Data register are allowed. In this case, access to memories or attribute register from Host side is not allowed. In case user issue Set Features command and set the Host side as 8bit mode, 8bit data access to the Adapter can be possible. Note: If this product is pulled out once and then insert again while power is on, this product is reconstructed from True IDE Mode to PC Card ATA mode. For setting True IDE mode again, please perform a power cycle while Adapter is inserted and OE# signal is GND. Table: I/O Feature in True IDE Function Code CE2# CE1# A0 IORD# IOWR# D15-D8 D7-D0 Invalid Mode L L x x x High Z High Z Standby Mode H H x x x High Z High Z Task File Write H L 1-7h H L Don t Care Data In Task File Read H L 1-7h L H High Z Data Out Data Register Write H L 0 H L Odd Byte In Even Byte In Data Register Read H L 0 L H Odd Byte Out Even Byte Out Control Register Write L H 6h H L Don t Care Control In Alt Status Read L H 6h L H High Z Status Out 27

34 3. ATA Register This product can be set as I/O device by using the following register. The communication between this Adapter will be done through Task File Register. Task File Register will provide all necessary register to store control and status information. PC Card interface will use 4 register to allocate and connect peripherals to the Host. I/O Configuration Config Index Mode Address Drive# Description 0 Memory 0-F,400-7FF 0 Memory Mapped 1 I/O Xx0-xxF 0 I/O Mapped 16 Contiguous Registers 2 I/O 1F0-1F7,3F6-3F 7 0 Primary I/O Mapped Drive 0 2 I/O 1F0-1F7,3F6-3F 7 1 Primary I/O Mapped Drive 1 3 I/O , Secondary I/O Mapped Drive 0 3 I/O , Secondary I/O Mapped Drive I/O Primary and Secondary address constitution REG# A9-A4 A3 A2 A1 A0 IORD#=0 IOWR#=0 Note 0 1F(17) Even RD Date Even WR Data 1,2 0 1F(17) Error Register Features 1 0 1F(17) Sector Count Sector Count 0 1F(17) Sector No. Sector No. 0 1F(17) Cylinder Low Cylinder Low 0 1F(17) Cylinder High Cylinder High 0 1F(17) Select Select Card/Head Card/Head 0 1F(17) Status Command 0 3F(37) Alt Status Device Control 0 3F(37) Not used Reserved Note: 1. Against the combination of odd byte and even byte(d15 - D0), if CE1# and CE2# are set as Low and A0 = Don t Care, it is accessible to register 0 as word register. Set CE1# as Low and CE2# as High, execute 1 pair of byte access to offset 0 and access to this register is also possible. This address area of word register is overlapped to Error byte width register in offset 1 and address area of feature byte with register, which please noted. Set CE1# as Low and access twice as byte register, first accessed byte will be even byte of word, and second accessed byte will be odd byte of same word. 2. Set CE1# as High and CE2# as Low, and byte access to register 0, accessible to error register (read) and feature register (write). 28

35 3.2. Continuous I/O Map Addressing When Host selects this Adapter and decoding the block adjacent to I/O register, the Register is addressed as follows by utilizing the block of I/O space decoded by Host. Contiguous I/O Decoding REG# A3 A2 A1 A0 Offset IORD# = 0 IOWR# = 0 Note Even RD Date Even WR Data Error Register Features Sector Count Sector Count Sector No. Sector No Cylinder Low Cylinder Low Cylinder High Cylinder High Select Card/Head Select Card/Head Status Command Dup. Even RD Data Dup. Even WR Data Dup. Odd RD Data Dup. Odd WR Data D Dup. Error Dup. Features E Alt Status Device Control F Not used Reserved Note: 1. Against the combination of odd byte and even byte(d15 - D0), if CE1# and CE2# are set as Low (and A0 = Don t Care), it is accessible to register 0 as word register. Set CE1# as Low and CE2# as High, execute 1 pair of byte access to offset 0 and access to this register is also possible. This address area of word register is wrapped to Error byte width register in offset 1 and address area of feature byte with register, which please noted. Set CE1# as Low and access twice as byte register, first accessed byte will be even byte of word, and second accessed byte will be odd byte of same word. Set CE1# as High and CE2# as Low and byte access to Register 0, accessible to error register (read) and feature register (write). 2. Register of offset 8, 9 and D are doubled to registers existing in offset 0 and 1 (but not overlapped). Register 8 is same as register 0. On the other hand, register 9 access to odd byte. When byte access to register 9 first and then to register 8, even byte Data will transfer first, and then even byte will follow. If byte access to register 8 or 0 repeatedly, it is possible to access byte in data buffer continuously. (even byte, odd byte, even byte ) Word access to 8, 9 or 0 registers, accessible to word in data buffer. It is not possible to byte access register 9 continuously, but byte access register 8 and then register 9, accessible to byte in data buffer continuously like even byte, odd byte, even byte, ) In case of byte access to register 9, accessible to odd byte in the data only. 3.When accessing all the Registers described in this Table, any address line, which is not indicated in this product, would be neglected. 29

36 3.3. Memory Mapped addressing When access have done to register of this adapter with using memory reference, register will allocated to common memory area within the range of 0 2K byte as follows. Memory Mapped Decoding REG# A10 A9-A4 A3 A2 A1 A0 Offset OE# = 0 WE# = 0 Notes 1 0 x Even RD Data Even WR Data x Error Register Features x Sector Count Sector Count 1 0 x Sector No. Sector No. 1 0 x Cylinder Low Cylinder Low 1 0 x Cylinder High Cylinder High 1 0 x Select Card/Head Select Card/Head 1 0 x Status Command 1 0 x Dup. Even RD Data Dup. Even WR Data x Dup. Odd RD Data Dup. Odd WR Data x D Dup. Error Dup. Features x E Alt Status Device Control 1 0 x F Not used Reserved 1 1 x x x x 0 8 Even RD Data Even WR Data x x x x 1 9 Odd RD Data Odd WR Data 3 Note: 1. Against the combination of odd byte and even byte(d15 - D0), if CE1# and CE2# are set as Low, it is accessible to register 0 as word register. Set CE1# as Low and CE2# as High, execute 1 pair of byte access to offset 0 and access to this register is also possible. This address area of word register is overlapped to Error byte width register in offset 1 and address area of feature byte with register, which please noted. Set CE1# as Low and access twice as byte register, first accessed byte will be even byte of word, and second accessed byte will be odd byte of same word. Set CE1# as High and CE2# as Low and byte access to Register 0, accessible to error register (read) and feature register (write). 2. Register of offset 8, 9,and D are doubled to registers existing in offset 0 and 1 (but not overlapped). Register 8 is same as register 0. On the other hand, register 9 access to odd byte. When byte access to register 9 first and then to register 8, even byte Data will transfer first, and then odd byte will follow. If byte access to register 8 or 0 repeatedly, it is possible to access byte in data buffer continuously. (even byte, odd byte, even byte ) Word access to 8, 9 or 0 registers, accessible to word in data buffer. It is not possible to byte access register 9 continuously, but byte access register 8 and then register 9, accessible to byte in data buffer continuously (like even byte, odd byte, even byte, ) In case of byte access to register 9, accessible to odd byte in the data only. 3.When accessing to even address within the range of 400h to 7FFh, access to register 8 will be done. If access to odd address within above range, access to 30

37 register 9 will be done. Data register and 1K byte of memory area correspond to this data register are provided to make the data register to shift memories from a Host side when register is existing in the memory area. The Host such as X86 processor, when executing Block shift between memory areas, it is necessary to increase address for both source attention. Some of PC card socket adapter have above feature and execute automatically. This address range will be useful to function such Hosts and adapters effectively. At the time of access, please make sure to access data register in FIFO method (First input first output). The random access to the data buffer in this product is not permitted True IDE Mode Addressing When this product is set to True IDE mode, I/O is decoded as follows: True IDE Mode I/O Decoding CE2# CE1# A2 A1 A0 IORD# = 0 IOWR# = 0 Note Even RD Date Even WR Data Error Register Features Sector Count Sector Count Sector No. Sector No Cylinder Low Cylinder Low Cylinder High Cylinder High Select Card/Head Select Card/Head Status Command Alt Status Device Control Not used Reserved 31

38 3.5. ATA Register Data Register (Address 1F0{170}; offset 0,8,9) Data Register is a Register of 16 bit and used for transfer data block between Data Buffer and Host. This register is overlap to Error register. Data Register CE2# CE1# A0 Offset Data Bus Word Data Register 0 0 x 0,8,9 D15-D0 Even Data Register ,8 D7-D0 Odd Data Register D7-D0 Odd Data Register 0 1 x 8,9 D15-D8 Error/Feature Register ,Dh D7-D0 Error/Feature Register 0 1 x 1 D15-D8 Error/Feature Register 0 0 x Dh D15-D Error Register (Address 1F1{171}; Offset 1,0Dh read only) When the bit 0 of Status Register indicates an error, an additional information concerning the cause of error is recorded in this Register. The bit is defined as follows: When CE1# is High, CE2# is Low and reading operation is executing to offset 0, it is possible to access to this register through data bit D15 D8. D7 D6 D5 D4 D3 D2 D1 D0 BBK UNC 0 IDNF 0 ABRT 0 AMNF Bit 7 (BBK) This bit will set when bad block is detected. Bit 6 (UNC) This bit will set when uncorrectable error has occurred. Bit 5 This bit is set to 0 Bit 4 (IDNF) Requested ID is not correct, or sector ID is not found. Bit 3 This bit is set to 0 Bit 2 (ABRT) This bit will set when command is cancelled, or invalid command is issued because of Adapter status, i.e. Not Ready, Write Fault, etc. Bit 1 This bit is set to 0 Bit 0 (AMNF) This bit will set when general error has occurred Feature Register (Address 1F1{171}; offset 1, 0Dh write only) This Register provides the information on the feature of this product, which Host can utilize. When CE1# is High, CE2# is Low and reading operation is executing to offset 0, it is possible to access to this register through data bit D15 D Sector Count Register (Address 1F2{172}; offset 2) In this register, the number of Sectors of data required to be transferred between Host and this product in the reading or writing operation is stored. When register value is 0,

39 sector will reserved. If command is completed correctly, register value will be 0 when all process completed. If command is not completed correctly, number of sectors to be transferred to complete command will be recorded Sector Number Register (Address 1F3{173}; offset 3) In this Register, the starting Sector number of this product which will be accessed by the subsequent command or bit 7-0 of Logic Block Address (LBA) is stored Cylinder Low Register (Address 1F4{174}; offset 4) In this Register, Low 8 bit of starting Cylinder address or bit 15-8 of Logic Block Address is stored Cylinder High Register (Address 153{175}; offset 5) In this Register, High 8 bit of starting Cylinder or bit of Logic Block Address is stored Drive Head Register (Address 1F6{176}; offset 6) This Register is used for the selection of Drive or Head. Also it is used for selecting LBA addressing in place of cylinder/head/selector addressing. The bit is defined as follows: D7 D6 D5 D4 D3 D2 D1 D0 1 LBA 1 DRV HS3 HS2 HS1 HS0 Bit 7 This bit is set to 1. Bit 6 Flag to select Cylinder/Head/Sector(CIS) or Logical Block Address Mode(LBA). If LBA=0, Cylinder/head/Sector will be selected. If LBA=1, Logical Block Address will be selected. In Logical Block Mode, Logical Block Mode will explained as follows. LBA07 LBA00: Sector Number Register D7 D0 LBA15 LBA08: Low Cylinder Register D7 D0 LBA23 LBA16: High Cylinder Register D7 D0 LBA27 LBA24: Drive/Head Register Bit HS3 HS0 Bit 5 This bit is set to 1. Bit 4(DRV) Indicate Drive No. In case DRV=0, Drive 0 is selected, if DRV=1, Drive 1 is selected. This Adapter is set to Card 0 or Card 1 by using copy field of PC card socket copy set register. Bit 3(HS3) Under operation of Cylinder/Head/Sector mode, indicate bit 3 as head number. Under operation of Logical Block Address mode, indicate LBA bit 27. Bit 2(HS2) Under operating at Cylinder/Head/Sector mode, indicate bit 2 as head 33

40 Bit 1(HS1) Bit 0(HS0) number. Under operation of Logical Block Sector mode, indicate LBA bit 26. Under operating at Cylinder/Head/Sector mode, indicate bit 1 as head number. Under operation of Logical Block Sector mode, indicate LBA bit 25. Under operating at Cylinder/Head/Sector mode, indicate bit 0 as head number. Under operation of Logical Block Sector mode, indicate LBA bit Status Register (Address 1F7{177}; offset 7) This Register records the status of this product. When the content in this Register is read, the reserved interruption is cleared. D7 D6 D5 D4 D3 D2 D1 D0 BUSY RDY DWF DSC DRQ CORR 0 ERR Bit 7(BUSY) If adapter is accessing to command buffer or register and disable to access from Host, this bit is set. In case this bit is 1, other bit in this register are invalid. Bit 6(RDY) This bit indicate that Host can execute operation or not. This bit will be cleared when power on, and keep this condition until the Adapter will be ready to receive command. Bit 5(DWF) This bit indicate that writing error has occurred. Bit 4(DSC) This bit means Adapter is ready to operate. Bit 3(DRQ) This bit request data when it is necessary to exchange information between Host through data register. Bit 2(CORR) When data error have occurred, and this data was corrected, this bit will set. In this case, multi-sector reading operation will not be cancelled. Bit 1(IDX) This bit is set to 0 always. Bit 0(ERR) This bit will set if some error have occurred on command execution. Additional information is contained in bit of error register Alternate Status Register (Address 3F6{376}; Offset E) This Register records the same content as in the Status Register. Even the content of this Register is read, the reserved interruption is not cleared Device Control Register (Address 3F6{376}; offset E) This Register is used for controlling the interruption demand of this product and effecting ATA soft reset to Adapter. Bit is defined as follows: 34