UIUC Pilawa Group 545-rk37Vu-57827

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1 UIUC Pilawa Group 545-rk37Vu Robert C.N. Pilawa-Podgurski, Assistant Professor University of Illinois at Urbana-Champaign, Urbana, Illinois, USA I. DESIGN OVERVIEW Our team has designed an inverter that meets all specifications outlined in the Little Box Challenge documentation. With a rectangular dimensions of 4.02 in 2.42 in 0.95 in and a total volume of 9.26 in 3, the experimentally verified power density (at 2 kw load) is 216 W/in 3. Our measured efficiency (CEC method) is 97%. A summary of the achieved specification is given in Table I. This document presents the overall structure of the inverter, high level description of the major components, as well as key experimentally measured results. Additional details regarding the design, implementation and operation of the inverter are presented in [1]. The overall schematics of the inverter are shown in Fig. 1. The power conversion stage consists of a 7-level flying capacitor multilevel converter, a line-frequency unfolder and an active energy buffer. Other components include start-up circuitry, auxiliary power supply, EMI filters and cooling fans. A photograph of the complete inverter PCB is shown in Fig. 7. TABLE I KEY PERFORMANCE SPECIFICATIONS Specifications Required Achieved Rated power 2 kva 2 kva Volume 40 in in 3 (156 cm 3 ) Power density 50 W/in W/in 3 (12.8 W/cm 3 ) Rated input voltage 450 V 450 V Rated output voltage 240 V RMS 240 V RMS Efficiency (CEC Method) 95.0% 97.0% Efficiency at rated power 95% 97.4% Load power factor Voltage THD 5% 0.3% Input current ripple 20% 15% Max. case temperature 60 C 57 C EMC FCC Class B FCC Class B II. 120 HZ INPUT RIPPLE DECOUPLING Shown in Fig. 3 is a schematic drawing of our proposed solution to the 120 Hz power ripple a seriesstacked partial power processing ripple compensating converter. Full operating details are described in [2], but here we provide a high-level overview, along with annotated photographs of our hardware prototype (Fig. 4). In this architecture, a GaN-based full-bridge converter with a ceramic buffering capacitors (C 2 ) is stacked in series with another high voltage ceramic capacitor (C 1 ). During operation, the output voltage of the buffer converter (across terminal a and b in Fig. 3) is controlled to vary in a complementary fashion to V C1 so that the dc bus voltage remains constant. Capacitor C 1 provides the majority of blocking voltage and power buffering, thereby enabling capacitor C 2 and the full-bridge converter to be implemented with low-voltage, high-speed transistors for an overall small dc-dc converter size. The semiconductors in the energy buffering converter are 100 V EPC GaN device, operating at a frequency in the hundreds of khz. This greatly reduces the size of the required inductors. At a high level, it combines the best features of a conventional ripple port converter [3] and the recently proposed stacked switched capacitor energy buffer [4]. A key advantage of this architectures is that the fullbridge dc-dc converter is only required to process a fraction of the total buffered energy, as C 1 provides the bulk of the power buffering without power conversion. Our proposed converter processes approximately 7% of the dc input power, as opposed to a total power of 2 π P DC processed by the conventional ripple port converter. On the other hand, our energy buffer requires only a few hundred µf of ceramic capacitance for C 1, and several hundred µf of ceramic capacitance for C 2 (at a reduced voltage rating). This represents a 9x volume reduction compared to a DC bus capacitance approach. Our team also performed extensive capacitor evaluations for a number of different technologies, which we have published [5] for the benefit of the community. A key innovation in the energy buffer is the sophisticated digital control loops that maintain the ripple to within specifications, and compensate for any dc offsets due to measurement errors and power losses. The digital control concept that enables this architectures was recently presented in [6] (COMPEL 2015 Best Paper Award).

2 Inverter RS VDC + Auxiliary Power Supply Start-up 12 V Converter 6.5 V Fig. 1. Buffer + Multilevel Vbus Converter and Unfolder - EMC Load Filter Schematic drawing of the inverter. Fig. 2. Photograph of the inverter PCB, with a deck of standard playing cards. Fig. 3. Schematic drawing of the active energy buffer architecture with high level control flow diagram. III. DC-AC CONVERSION We accomplished the dc-ac conversion through the use of a 7-level flying capacitor multi-level (FCML) converter, as shown in the schematic drawing of Fig. 5 and the annotated photograph of Fig. 6. While modu- Fig. 4. Annotated photograph of the series-stacked ripple compensation converter. lar multilevel (MMC) inverters are used extensively in medium and high voltage applications, they are inherently less power dense than the FCML topologies. We demonstrated the significant power density and efficiency benefits achievable in the low voltage range (hundreds of volts) by a state-of-the-art implementation of FCML converter prototype. The key advantage of the 7-level structure is the 6 times reduction of the ripple voltage seen by the inductor, and the 6 times increase in the ripple frequency. As a result, for a certain inductor current ripple, the inductor size can be reduced by as much as 36 times. With transistor switching at 120 khz, the effective ripple frequency of the inductor voltage was 720 khz, and the inductor value required is only tens of µh. The high switching frequency is achieved through the use of custom GaN modules. These modules consists of two pairs of GaN switches in half-bridge connection, and decoupling capacitors in close proximity. This significantly reduced the parasitic inductance in the commutation loop, thus minimizes drain-source voltage ringing of the

3 S 6A S 5A S 4A S 3A S 2A S 1A VDC + C 6 C 5 C 4 C 3 C 2 C 1 L V out S 6B S 5B S 4B S 3B S 2B S 1B Fig. 5. Schematic drawing of the 7-level flying-capacitor multi-level inverter used for this work. Unfolder at V out not shown. Fig. 7. Photograph of the complete inverter enclosure. Thermal contact is also ensured between the lower portion of the converter and the milled copper case. This provides cooling for the microcontroller and active buffer devices. Finally, it should be noted that the multi-level architecture is beneficial for its heat spreading properties, thereby minimizing risks of hot-spots. Even temperatures across the heatsinks of around 57 C was observed at peak load. A photograph of the enclosure is provided in Fig. 7. Fig. 6. Photograph of the inverter stacked above the energy buffer. Inverter GaN switching modules are clearly visible in red. transistors and related switching losses. The 7-level FCML converter generates a uni-polar waveform, and the full ac output is generated by an unfolder stage (included in Fig. 6), using silicon superjunction transistors, operated at line frequencies. IV. THERMAL MANAGEMENT Our team had two design goals for thermal management: 1) strive for a high efficiency design (substantially above the lower bound of 95%) to generate less heat; 2) strive for a flat design to maximize the surface-areato-volume ratio. Additionally, the inverter GaN modules (which represented the largest power loss elements in our design) were placed on the top side of the PCB, and was directly attached (with thermal compound) to a custom milled heatsink, which is also the top of the enclosure. In order to provide low thermal impedance to the heatsink, Gap Pad 5000S35 (with a thermal conductivity of 5 W/m-K) was used to establish thermal contact between the devices and the heatsink. To improve heat transfer, six low-profile fans were embedded in the heatsink to provide forced air cooling of the system. V. ELECTROMAGNETIC COMPLIANCE (EMC) The strategy for achieving EMC compliance was first and foremost to minimize any conducted and radiated EMI through careful layout and component placement. Our team went through several iterations of hardware prototypes in order to reduce common and differential mode EMI, as well as coupling between high dv/dt nodes and sensitive analog circuitry. Particular attention was paid to ground planes, with large copper fills where appropriate. All loops were kept to a minimum, and signals were routed directly above a return path, to minimize the chance of coupling, and unintended radiation of signals. The fast transients of the GaN devices were well managed by the custom GaN modules, which minimized both parasitic current loops, and large coupled capacitance which can lead to leakage currents. Overall, the multi-level architecture helped greatly to minimize EMI concerns, as each switching node only switched between potentials of 1 6 V DC, rather than between 0 and V DC, as is the case for conventional inverter structures. In addition to these efforts to minimize the generated EMI, common mode and differential mode EMI filters were placed at the converter output terminals. The size of these filters occupied less than 5% of the overall volume, thanks to the careful design consideration given above.

4 100 Efficiency [%] Buffer Efficiency Inverter Efficiency 94 Overall Efficiency Overall Efficiency including control and fans Output power [kw] Fig. 8. Current Ripple [A] Fig Converter efficiency at different power levels. Current Ripple 20% Limit Average Input Current [A] Input current ripple as a function of the average current. Finally, the custom milled copper case did an excellent job of shielding radiated EMI. VI. EXPERIMENTAL RESULTS The efficiencies of the FCML converter, the active energy buffer, as well as the whole inverter are shown in Fig. 8. The active energy buffer achieves a round-trip efficiency over 99%, and the FCML converter achieves an efficiency over 98.5% at the full power. The overall efficiency is above 97% for the majority of the load range. A plot of the measured input current ripples as a function of the average current is shown in Fig. 9. The current ripple is below the 20% limit except at very light conditions. The operation of the 7-level inverter can be seen in Fig. 10, which shows the switching node voltage as well as the output voltage and current. The output voltage is 240 V RMS and the output current is 8.3 A RMS at full load. The switching node features a high frequency PWM between two smaller voltage levels, with a 120 Hz envelope. The conducted EMI is measured and is given in Fig. 11. As shown, the EMI is below the FCC Class B limit for all frequencies in the specification. REFERENCES [1] Y. Lei, C. Barth, S. Qin, W. chuen Liu, I. Moon, A. Stillwell, D. Chou, T. Foulkes, Z. Ye, Z. Liao, and R. C. Pilawa-Podgurski, Fig. 10. Waveforms showing the output voltage, output current and the switching node voltage (V SW) of the 7-level inverter at full load. Measured EMI (dbuv) Fig Frequency (Hz) Measured FCC Class B Limit Conducted EMI measurement at full power (2kW). A single-phase, 7-level, gan inverter with an active energy buffer achieving 216 w/in 3 power density and 97.6% peak efficiency, in Applied Power Electronics Conference and Exposition (APEC), 2010 IEEE, [2] S. Qin, Y. Lei, C. Barth, L. W.C., and R. Pilawa-Podgurski, A high-efficiency high energy density buffer architecture for power pulsation decoupling in grid-interfaced converters, in IEEE Energy Conversion Congress and Exposition (ECCE), [3] P. Krein, R. Balog, and M. Mirjafari, Minimum energy and capacitance requirements for single-phase inverters and rectifiers using a ripple port, Power Electronics, IEEE Transactions on, vol. 27, pp , Nov [4] M. Chen, K. Afridi, and D. Perreault, Stacked switched capacitor energy buffer architecture, Power Electronics, IEEE Transactions on, vol. 28, pp , Nov [5] S. Barth, I. Moon, Y. Lei, S. Qin, and R. Pilawa-Podgurski, Experimental evaluation of capacitors for power buffering in single-phase power converters, in IEEE Energy Conversion Congress and Exposition (ECCE), [6] S. Qin, Y. Lei, C. Barth, W. Liu, and R. Pilawa-Podgurski, Architecture and control of a high energy density buffer for power pulsation decoupling in grid-interfaced applications, in IEEE Workshop on Control and Modeling for Power Electronics (COMPEL), 2014.

5 Robert Pilawa-Podgurski received dual B.S. degrees in physics, electrical engineering and computer science in 2005, the M.Eng. degree in electrical engineering and computer science in 2007, and the Ph.D. degree in electrical engineering in 2012, all from the Massachusetts Institute of Technology. He is currently an Assistant Professor in the Electrical and Computer Engineering Department at the University of Illinois, Urbana-Champaign, and is affiliated with the Power and Energy Systems group. He performs research in the area of power electronics. His research interests include renewable energy applications, energy harvesting, CMOS power management, and advanced control of power converters. Dr. Pilawa-Podgurski received the Chorafas Award for outstanding MIT EECS Master s thesis, the Google Faculty Research Award in 2013, and the 2014 Richard M. Bass Outstanding Young Power Electronics Engineer Award of the IEEE Power Electronics Society, for outstanding contributions to the field of power electronics before the age of 35. In 2015, he received the Air Force Office of Scientific Research Young Investigator Award. He is an Associate Editor for the IEEE Transactions on Power Electronics, and for the IEEE Journal of Emerging and Selected Topics in Power Electronics. He is co-author of four IEEE prize papers. Christopher Barth received the B.S. and M.S degrees in Electrical and Computer Engineering from University of Illinois at Urbana- Champaign in 2012 and 2014 respectively. He is currently pursuing a Ph.D. degree at UIUC. His research is in high power density inverters for PV and motor drive applications. Wen-Chuen Liu received the B.A. and M.S. degrees in Electrical Engineering from National Cheng Kung University, Taiwan, in 2010 and 2013, respectively. He is currently working toward the Ph.D. degree in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL. His research focuses on integrated circuit design for power converter with high performance, high power density and high conversion ratio. Shibin Qin received the B.E. degree in Electrical Engineering from Huazhong University of Science and Technology in 2012 and the M.S. degree in Electrical Engineering from University of Illinois at Urbana-Champaign in 2014, where he is currently pursuing a Ph.D. degree. His research is in high power density converters and photovoltaic applications. Intae Moon is a fourth year undergraduate student at the University of Illinois at Urbana- Champaign. He is currently working toward a Bachelor of Science in Electrical Engineering and expecting to graduate in May Between 2011 to 2013, he completed his military service in the Republic of Korea Air Force as a weapon loader and coordinator at Kunsan Airbase, South Korea. He is currently working as an undergraduate research assistant with the UIUC Power and Energy Systems group and is responsible for building and repairing the GaN switching modules used by the research group. He finds research experience very rewarding and looks forward to continuing work in field of power electronics, integrated circuit design, and renewable energy systems. Yutian Lei received the B.A. and M.Eng. degrees in Electrical Engineering and Information Science from University of Cambridge, UK, in He is currently working toward the Ph.D. degree in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, IL. His research focus includes the analysis and design of high performance switched-capacitor converters and multilevel converters. Andrew Stillwell graduated with a B.S. in Electrical Engineering and a B.S. in Computer Engineering from the University of Missouri- Columbia in He worked for National Instruments in Austin, Texas for 8 years as a Hardware Group Manager in Research and Development. His years in industry have given him a broad skillset in test and measurement automation, data logging, and project management. His research interests include power electronics, switchedcapacitor converters, series voltage domain applications, and in-home phasor measurement units. Andrew completed his M.S. in Electrical Engineering at the University of Illinois at Urbana-Champaign in 2015 and is currently pursuing his Ph.D. in Electrical Engineering.

6 Derek Chou graduated with a B.S. in Electrical Engineering and Computer Sciences and a minor in Mechanical Engineering from the University of California, Berkeley in May He is currently working towards an M.S. and Ph.D. in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. His research interests include high-density power electronics, photovoltaic applications, and applications in extreme environments. Zichao Ye received his B.S. degree in electrical engineering from University of Illinois at Urbana Champaign with highest honors, in May He is currently pursing his master degree in electrical engineering at the University of Illinois. His current research work is in the field of power electronics, with the focus on integrated power supply circuitry of gate drivers for Multi-level converters. Thomas Foulkes received his B.S. degree in Electrical Engineering with a minor in Applied Mathematics from Rose-Hulman Institute of Technology, Terre Haute, Indiana in He is currently pursuing his PhD degree in Electrical Engineering at the University of Illinois at Urbana-Champaign. His research examines advanced cooling techniques, EMI filtering methods, and multilevel switched-capacitor topologies in order to increase the power density of inverters for electric vehicle applications. Zitao Liao received his BS degree in Electrical Engineering from University of Illinois Urbana Champaign in He is currently pursuing his MS degree in Electrical Engineering, with a focus on highly efficient multi-level dc-dc step-up power converters using GaN transistors